USRE25120E

USRE25120E - holmes

Info

Publication number: USRE25120E
Authority: US
Priority date: 1954-12-08
Publication date: 1962-02-06
Also published as: US2874901A

Description

T. G. HOLMES TALLY INSTRUCTION APPARATUS FOR Feb. 6, 1962 AUTOMATIC DIGITAL COMPUTERS Original Filed Dec. 8, 1954 5 Sheets-Sheet 2 TQQ \umQ A E G E .PNQQ W n u E buhmw A T. G. HOLMES TALLY INSTRUCTION APPARATUS FOR Feb. 6, 1962 AUTOMATIC DIGITAL COMPUTERS 8. 1954 5 Sheets-Sheet 3 Original Filed Dec hnmwqQw %k I m UMQQ km kbnkbm United States Patent OfiFice Re. 25,120 Reissued Feb. 6, 1962 cation; matter printed in italics indicates the additions made by reissue.

The invention described herein may be manufactured and used by or for the Government of the United States for governmental purposes without payment to me of any royalty thereon.

Automatic digital computers have four basic components: the memory or storage component, the arithmetic component, the terminal component and the control component.

The memory or storage component consists of a number of storage locations or cells into which information can be inserted for storage and from which information can be extricated when needed by the computer. Numbers on which operations are to be performed, the results of such operations and instructions governing the operation of the computer are stored in the various memory cells. Each cell is identified by an address number.

The arithmetic component of the computer comprises all of the apparatus necessary to perform the arithmetic operations of addition, subtraction, multiplication and division.

The terminal component comprises all of the apparatus required to transfer information into and out of the computer.

Finally, the control component, with which this invention is concerned, comprises all of the apparatus required to take instructions from the memory, to analyze these instructions and to issue appropriate commands causing the computer to execute the instructions[.], the above three functions being defined as and being hereinafter referred to as a computer directive.

It is the object of this invention to simplify the instruction programing of iterative operations. Briefly, this is accomplished by providing, as part of the control component, apparatus operative in response to a special instruction, termed a tally instruction, to cause the computer to repeatedly refer to and carry out a single instruction stored in one of the cells of the memory. Both the address of the instruction to be repeated and the number of repetitions desired are designated in the tally instruction. The apparatus makes use of a special counter, referred to as the base counter, for keeping a tally of the number of times the designated instruction has been performed during execution of the tally instruction. Also, as will be explained in more detail later, one or more of the addresses in the repeated instruction are made relative to the base'counter, which is reset at each execution by the tally instruction, so that the tally instruction is able to effectively modify these addresses without altering the repeated instruction itself. number of repetitions specified inthe tally instruction the computer automa-tically refers to the next instruction in the sequence of instructions stored in the memory.

A more detailed description of the invention will be given in connection with the specific embodiment thereof shown in the accompanying drawing in which FIG. 1 illustrates the composition of an instruction word in the specific embodiment described, and

When the tally equals the,

designated a minor cycle.

FIG. 2 is a logical diagram of that part of the computer control component involved in execution of the telly instructiomand FIGS. 3 and 4 show timing diagrams for the execution of a tally instruction and an arithmetic instruction, respectively.

In the specific embodiment of the invention described herein a computer word, i.e. the group of digits representing a number or an ins-truction, consists of 48 binary digits in the form of a serial electrical pulse code having 1 a pulse frequency of 'one megacycle persecond. The component parts of both number and instruction words are shown in FIG. 1. Electrical pulses are present or absent at the time positions of digits P P depending upon whether the particular digit is a 1 or a 0. The length of a word is 48 microseconds, this period being Digits P P are not' normally used and may be regarded as zeros.

In the case of a number word, digit P represents the} sign or of the number and digits P P its abso*- lute value, P being the least significant digit. In the}:

* case of an instruction word,-digit P, has no significance instructions must be arranged in sequence in the memory and a control counter that is increased by one each time a an instruction is performed, is required to designate the. memory cell containing the next instruction. The'control counter may be'reset by certain logical operations including the tally instruction as will be seen later.

Inconventional instructions the numbers a, fland 7 may be absolute or they may be relative to a control counter C or a base counter C as determined bythe digits, a, b, c, d .of the relative address control group. Accordingly, the effective values m B and 'y, of these numbers are determined as follows:

where a, b and c are either 1 or and (C and (C represent the contents'of the control and base counters respectively. As summarized in the above equations, the elfective value of an address is its absolute value modified by the contents of either the control counter or the base counter. If the address isabsolute, its efiective value equals its absolute value. If relative, the eifective value equals its absolute value plus the contents of one of the counters. The digits a, b and c indicate whether the associated addresses alpha, beta and gamma are absolute (digit=0) or relative (digit=1). The' digitfd indicates the c'ounter'to which the address is relative (d=0 indicates control counter and d=1 indicates base counter). For example, in thecase of the alpha address the efi'ec-.. tive value equals alpha when the address is absolute (a=0). When relative (a,=1), the effective value equals alpha plus the conten-ts of the control counter (d=0) or alpha plus the contents of the base counter (d=1). The 2 function of the control counter has alreadybeen'de-J scribed. The base counter is an additional counterfused as an adjustable reference point for relative addresses and as a tally keeping device in the performance of the tally instruction. The base counter may be changed or reset by a tally instruction only, as will be seen later in the description of FIG. 2. The .term base is used simply to distinguish this counter from the control counter. Other than use, there is no essential difference in the two counters as will be apparent from the subsequent description of FIG. 2.

If the instruction calls for an arithmeticoperation, at and B, are the addresses in the memory of the two operands and w designates the memory cell in which the result is to be stored. In instructions calling for nonarithmetic operations these numbers may .or may not represent memory addresses depending upon the operation to be performed. For example, in an instruction to .read a specified number of words from a specified input device into the memory beginning with a specified memory cell, a may represent the number of words, )3, may designate the input device, and 'y may be the address of the memory cell receiving the first word.

The tally instruction differs from conventional instructions of the above type in that the relative address feature is more restricted. In the tally instruction on and 8, if relative, are always relative to the base counter, and 'y, if relative, is always relative to the control counter. Thus, in the tally instruction,

These equations characterize the tally instruction in the same manner that the preceding equations characterize conventional instructions. The digits a, b and c, which appear in the control group (CG) of the instruction (-FIG. 1)., determine whether the corresponding address is absolute or relative as explained for the preceding equations. The control digit d in this case does not designate the reference counter but serves a special purpose which will be explained later.

In the tally instruction, or designates the amount by which the base counter is increased each time the tally instruction is executed. Its value is usually one but may be greater than one .in certain cases as will be shown later. The B number is indicative of'the number of times the designated instruction is to be repeated. The 'y num-' her is the memory address, absolute or relative depending upon the value of c, ot the instruction to be repeated. v I

In executing the tally instruction the control component of the computer determines on fi and and compares the binary number ar with the binary number fi Depending upon this comparison one of the following two courses of action takes place:

(1) a fl z The base counter C is reset to m and the control counter C is reset to w Thecomputer therefore looks for its next instruction in the memory cell whose address is 7 I p 2) a fi z C is reset to a if d=0 and'to 0 if (i=1. One is added to the contents of the control counter .so that the computer is referred to the next instruction in the sequence of instructions.

As already mentioned or, B and 'y areeach 12-digit binary numbers. In order to abbreviate the writing of instructions as much as possible the hexadecimal system of binary notation is-used. In this system each of the sixteen .possible combinations of four binary digits are designated by hexadecimal digits as follows:

Binary 'Hex Binary Hex. 1 Binary l )1 ll i0 1010 tally instruction.

4 Thus the binary number 100011010110 becomes the hexadecimal number 8D6. In an instruction written in hexa decimal form a, 13 and 'y are "each represented by three hexadecimal digits and the relative address control group and operation code are each represented by one hexa decimal digit. A typical instruction therefore may be of the form a 3 7 C G OP'N 61B 032 00D B 3 As is apparent from the preceding table, the alpha address 61B is the binary number Code Operation Description 0 Input; Insert a number of words from as input unit into memory starting with n, memory cell. 3 Number 0011- (a) 3 even: Convert decimal number in a to version. binary and insert in (b) ,8 odd: Convert binary number in a to 7 decimal and insert in 4 Subtraction".-. Subtract contents of B! from contents of do and place the difference in 5 Addition Add the contents of as to the contents of Ba and place the sum in we. 9 Multiplication Multiply contents of a, by contents 018. and (rounded). place product, rounded to 44 binary digits,,

' 1n A..-" Tally Compares a, with 3.. It 68: Resets Cs to a and Cu to If a028,: Resets O to 0(b=1) or 1(b=0) Adds one to Ga.

(1) It is desired to add individually the 5 numbers in memory cells 012-016 to the 5 numbers in memory cells 00D-011 and place the sums in the 5 memory cells 00D- 011. The coding for this problem utilizing the tally instruction would be as follows, the necessary instructions being placed in cells 07A and 07B and the count in C being initially 000:

Cell# a a is 1 CG(abcd) 01m 012 qoDf 00D M1111). 5 001. 005 07A- 9 1001) A When the control counter reaches 07A the computer Operates in response to the instruction in this cell to add the contents of cell 012 to the contents of cell 00D ad place the sum in cell 00D, the sum replacing'the operand originally in this cell. The control'counter then advances to 07B which is the address of the cell containing the With C =000, m =001 and 3 005. Further, since C=0, 'y ='y=07A. Therefore in performing the tally instruction C is reset to 001 and C is reset to 07A. The computer as a result returns to themstruction in 07A.

As seen from the relative address control group of the instruction in 07A all of its addresses are relative (a, .b, c=l) and they are relative to the base counter (d=1). Since C was initially set to Zero, in the first execution of this instruction -a =a=012, p =s=00D and. ='y=00D. However, the second time this instruction is. referred to C ,=,00l and as a result .a =013, B =00Eand ,:00E. Therefore in the second execution, the number in 013 is added'to the number in DOE and the sum placed in DOE. The computer is then advanced by the control counter to the tally instruction in 07B for the second time.

In the second execution of the tally instruction the contents of C is 001 instead of 000 and therefore m the number to which C is reset, becomes 002. Since this number is still less than 005, C is again reset to 07A and-the computer-refers to the instruction in this cell for the third time. In the third execution of this instruction, with C =002, a =O14, B =F and v =00F.

The above process continues until at the fourth reference to the tally instruction following the fourth execution of the instruction in 07A, C =004 and ug=005. Since a now equals B the fourth execution of the tally instruction causes C to be reset to 0 ((1:1) and adds one to the contents of C (07B) thereby causing the computer to seek its next instruction in memory cell 07C.

(2) As a'second example assume that it is-desired to read ten data words from a specified input device into consecutive memory cells beginning with the cell whose address is 0A0. Since input devices usually supply number words in binary coded decimal form it is necessary that these words be converted to. true binary numbers. Utilizing the tally instruction and assuming the initial setting of the base counter C to be 000, the coding may be as follows:

The instruction in cell 001 calls for reading ten (00A) words from input device 001 into consecutive memory cells starting with the memory cell whose address is 0A0. When this operation has been performed the control counter advances the computer to memory cell 002. The instruction in this cell calls for converting the number in cell 0A0 to binary form and storing the converted number in cell 0A0. The a and 7 addresses in this instruction are relative to the base counter (a, c and d'=l) but, since the initial setting of C is zero, cc =a and 5: in the initial execution of the instruction.

The conversion of the remaining nine numbers is accomplished through the tally instruction in cell 003. When this instruction is reached for the first time C =O0O, =001 and B =00A. Since u fi C is reset to 7 and as a result the computer looks for its next instruction in ar which, being relative to the control counter (c=l), is 002 (FFF+0O3=002). Since C was reset to 001 by the tally instruction and since the on and 7 addresses of the instruction in 002 are relative to C the second execution of this instruction causes the number in 0A1 to be converted to binary form and inserted in 0A1.

The tally instruction is now reached for the second time. This time m =O02 which is still less than B and, by the above described process, results in C again being reset to 7. or 002. The instruction in this cell is therefore executed a third time. Since now C =002, the third execution results in the number in 0A2 being converted and stored in 0A2.

After the tenth execution of the instruction in 002 the count in the base counter C stands at 009. Therefore, in the ensuing execution of the tally instruction ar 0A0 [8 Consequently C is reset to 0 (d=1) and the control counter C is advanced by one to 004.

(3) Computing the algebraic sum of a plurality of numbers is another situation in which the tally instruction may be utilized to advantage. Assume it is desired to compute the algebraic sum of 15 numbers located in consecutive memory cells beginning with 07F. The

sum will be accumulated in cell 00D. Incontrast with the preceding problems it is assumed that the initial setting of the base counter C is 00A. The necessary instructions, located in

memory cells

005, 006 and 007, are as follows:

Cell a 5 -y GG(ahcd) OPN 005 FFF FFF 00D 0(00O0) 4 006 00D 075 00D 5(0101) 5 007 001 019 FFF B (1011) A The instruction in 005 clears 00D by subtracting the number in FFF from itself and placing the difierence which is zero in'OQD. Since the B address in the instruction in 006 is relative to C (b, d=l),

and the computer returns to the instruction in 006. In the second execution of this instruction the number in GOD is added to the number in 080 (075+00B) and the sum placed in 00D. I The above process continues until after the 15th execution of the instruction in 006 the final sum is in 00D and the count in C is 018. Consequently, in the next execution of the-tally instruction ag=001+018=019=/3, and the computer takes its next instruction from 008 (C +l),

C being reset to 0 (d=1).

(4) In the preceding examples a in the tally instruction was always 001. In certain situations a may be an integer larger than one. For example, assume that it is desired to clear every other memory cell starting with cell 021 and ending with cell 03F. If the count in C is initially zero the necessary instructions, stored in memory' cells IFO and IE1, are:

Cell)? 0: p 1 0G OPN (abcd) lFO FFF FFF 021 3(o011) 4 1F1 002 MR. lFO 9 1001 A In the instruction in lFO 'y is relative to C (c, d=1 Since initially C =000 the first execution of the instruction clears cell 021. In the second execution Cg=002 and cell 023 is cleared. After the last cell 03F has been cleared the count in C stands at 01E. Therefore in the following execution of the tally instruction u =020 which is greater than 01F and results in C being reset to 0 (d=1) and one being added to C so that the computer looks for its next instruction in 1P2.

(5) As a final example assume that it is desired to compute the value of the integral into 20 subintervals of .05 radians each the value of this integral is given by the expression 7. Assume'further that the required 20 valuesof 'y'=sin x are stored in consecutive memory cells starting with 100; that the fractions arestored in appropriate memory cells K K and K respectively; and that the initial setting of the base counter in these instructions without modifying the instructions in the performance of the tally instruction is shown in block form in FIG. 2. In this diagram only the gating means, the delaymeans, adders, etc. are illustrated. Fur-.

ther it is assumed that the only delays in the system are those occurring in the designated delay blocks. The ilis zero. The necessary instructions, stored in conlustrated circuit therefore difiers from a practical circuit. secutive..memory cells 020-028, are as follows: 10 in that inthe latter case it would be necessary to provide Cell)? a 6 '7 CG (abcd) OPN Remarks .05 020 K1 100 00c owner 9 y in 000 021 K1 114 FFF 0(0000 9 S 1n FFF 022. 00o FFF 00o 0 0000 (y +y 111000 I I in FFF 023 K; 101 FFF 5 0101 9 5? )+%2 024 00o. FFF- 00o 0 1000 5 3 Y" Y Repeats 023 and 024 until all 025 .002 013. FFE 13(1011) A {of y y yio appear in above sum.

' 1 FFF 02s K, 102 FFF 5(0101 9, E n

.05 2 -(Yn+y2o)+ (Y1+y:+ 027 00C FFF (G M11000) 5 1 -+Y19)+ Yi) '1=2,4,6. 1s; Repeats 0 s and 027 until all 028'. 002 011 FFE B11011) A 013 2, y4, yisappearsin preceding sum.

. The operation of the above instructions should be clear frornthe. accompanying remarks and the explanation of the tally instruction given in the preceding problems. The ,3. address of the instruction in ()23 is relative to the base counter. Since y y y 1 are located in alternate memory cells the effective 8 address: in this instruction must be increased by 002 each time the instruction is performed. This. is accomplished, by making a=002 in the tally instruction. A similar situation exists in connection with the instruction in 026 and the tally instruction 028.

After hasbeen added by the final performance of the instruction in 024 the base counter has a count of 012. In the subsequent execution of the tally instruction in 025, a =O14 which is greater than 54013). The base counter is therefore reset to 0 (d=1) and the control counter is increased to 026. Similarly, after has been added by the final execution of the instruction in 027 the base counter has a count of 010. In the subsequent execution of the tally instruction in 028, a =O12 which is greater than 19,,(011). Therefore, the base counter is reset to 0 (b=1) and the control counter is advanced to 029 where the computer seeks its next instruction.

From the above examples it is seen that the tally instruction affords a simplified and rapid way of (1) causing the computer to. repeat a set of instructions a specified number of times, and (2) changing the efiective addresses suflicient amplification at various points in the circuit to.

insure adequate signal levels, and the inherent delays produced by the various elements of the circuit such as amplifiers, gates, adders, etc. would have to be taken into account in the design of the delay elements. Since these are merely matters of design they are ignored in FIG. 2 for the sake of simplicity.

The gating means are illustrated in FIG. 2 as semi! circular blocks with the output line extending from the curved side and the input lines entering through the straightside. Two types of gates, designated in the computer art as and gates and or gates, are used. The construc-. tion and operation of such gates are well understood and are described in the literature such, for example, as the Computer Issue of the Proceedings of the Institute of Radio Engineers, vol. 41, No. 10, October 1953, pages 1300-1313 and 1381-1387. These gates may be realized in different ways, the construction of the gate being irn-. material in FIG. 2 provided the desired function is performed. Briefly, an and gate is one in which an input must appear simultaneously on each of the input lines in order for an output to be produced, and an or gate is one in which an input on one or more of the input lines will produce an output. Gate 45 is an example of an and gate and gate 12 is an example of an or, gate. The two are distinguished by having the input lines stop at the straight side in the case of an and gate and extend through to the curved side in the case of an or" gate. An and gate may also be of the inhibited type, an example of which is gate 66. In this type the inhibit input line is designated by a small circle at the point Where the line touches the straight side. In the case of the inhibited and gate, an output is produced only in the presence of signals on all input lines except the inhibiting input 9 line. A signal on the inhibiting line prevents an output under any condition.

The circuit of FIG. 2 makes use of dynamic flip-flop circuits, abbreviated FF, in several places. This type of circuit, also described on pages 1309-1310 of the above cited issue of the Proceedings of the I.R.E., has two stable conditions in one of which off it has no output and in the other of which on it has an output in the form of a one megacycle pulse train. The d FF of FIG. 2 is of this type. The circuit contains a 1 microsecond delay loop which includes or" gate 70, delay 71, and and gate 30. Assuming the FF to be 011" it may be t urned on by the application of a pulse from gate 27 to the input of gate 70. This pulse appears in the output of gate 70 and also travels around the delay loop to the input of gate 70, assuming an input to the T line of gate 30, so that 1 microsecond later a second pulse appears in the output of this gate. Similarly, this second pulse appears 1 microsecond later in the output of gate 70 as a third pulse, and so on. Therefore, as long as an input is maintained on the T line of gate 30 the FF is on and has a one megacycle pulse output. Removal of the input to gate 30 on the T line breaks the feedback loop and returns the FF to its oif condition.

' The adder 19 in FIG. 2 may be of any type capable of adding binary numbers represented by successively occurring electrical pulses. An example may be found in FIG. 13-6, page 274, of High-Speed Computing Devices, Engineering Research Associates, McGraw-Hill, 1950.

The operation of the circuit of FIG. 2 is governed by a number of control voltages which are described as follows:

F F F F These voltages represent the four phases or major cycles through which the computer passes in executing an instruction. Each is a train of one megacycle pulses and has a duration of one or more minor cycles of 48 microseconds as defined in FIG. 1.

B A train of 48 one megacycle pulses occurring during the first minor cycle of each phase.

T -T Each represents one pulse per minor cycle occurring at the time indicated. T 51 Each represents all 48 pulses of each minor cycle except the pulse occurring at the time indicated.

B: A train of one megacycle pulses on during performance of the tally instruction.

The B control voltage is generated by staticizer and decoder 1. The function of this device is to analyze the operation code of an instruction and energize appropriate control lines which condition the computer to carry out the operation called for by the code. The B control line is energized in response to the A operation code of the tally instruction and conditions the computer to execute the tally instruction. Such a decoder is an essential part of all stored program digital computers and is therefore a well known item in the computer art. See, for example, Fig. 5 on page 1303 and the paragraph starting at the bottom of this page in the Proceedings of the Institute of Radio Engineers, vol. 41, No. 10, October 1953. The remaining of the above described voltages are generated by apparatus generally indicated by

blocks

2, 3 and 4. Since the design of these elements forms no part of the invention they are not shown in detail.

The operation of FIG. 2 in response to a tally instruction is as follows:

As already mentioned the execution of an instruction takes place in four phases, F F F and R; of computer operation. The diagram in FIG. 3 illustrates the timing of the various operations taking place in the execution of the tally instruction and will be helpful in understanding the following description. In F, the tally instruction enters the instruction storage loop 5, abbreviated ISL, from the memory. The ISL comprises a 48 microsecond delay line 6, inhibited and gate 7 and or" gate 8. During the first minor cycle E, of F; the tally instruction arrives from the memory on line bal and enters the ISL through

gates

9 and 8, the digit P (FIG. 1) entering first. At the same time gate 7 is inhibited, E being on, so that anything already in the loop is erased. At the end of E,, which in this case is also the end of F the tally instruction is in the ISL. The operation code digits P P (FIG. 1), which for the tally instruction are A(1010), enter the ISL and are applied to the staticizer and decoder 1 at times T T of the first minor cycle (E of F Therefore, during F the B output line of the staticizer and decoder is energized.

During F (phase 2) pe=fi+ b) is generated and sent to the arithmetic unit. complished as follows:

One input of gate 10 in address selector circuit 11 is connected to the 10 microsecond tap of delay line 6 in the ISL. This gate passes every pulse appearing at this tap during F of B (tally) operation. The output of gate 10 passes through gate 12 to one of the inputs to gate 13 in the address gating circuit 14. The address gating FF 15 is turned on in F by gate 16 at T and off by inhibiting gate 17 at T The output of this FF therefore is a series of 12 one megacycl-e pulses occurring at times T -T of F which pulses are applied to another input of gate 13. Since the third input of gate 13 has the F, control pulses applied thereto, this gate passes all of the pulses occurring at tap 10 of delay line 6 at times Tgg-T43. As may be determined from FIG. 1, the digits appear at the 10 microsecond tap at times T -T and is thus gated through

gates

13 and 18 to adder 19.

The b digit of the relative address control group appears at the 22 microsecond tap of delay line 6 at T of F If a pulse appears at this time (b=1) it is passed through gate 20 of relative address FF 21 and turns this FF on. FF 21 is turned off by gate 22 at T Therefore, if b=l, the output of FF 21 is a train of one megacycle pulses occurring at T -T After a one microsecond delay by element 23 these pulses are applied to gate 24 of PF #25 at T -T FF #25 is turned on by gate 24 at T and off by gate 26 at T Therefore if b=1, the output of FF #25 is a train of 12 pulses at times T T of F If b=0 this FF has no output.

During F in the execution of the tally instruction (B on) the d FF is turned on by gate 27 at T and off by gate 30 at T The resulting output of this FF is a series of pulses from T to T which are applied to input circuits of

gates

31 and 32.

Gates

31 and 32 serve to gate the contents of the control counter C and the base counter C respectively, to the adder 19. During F, (and F however, C can not be so gated because of the inhibiting action of the output of the d FF on gate 31. The [3 address, therefore, if relative, must be relative to C If b=1, the l2-pu1se output of FF #25 permits the IZ-digit contents of C to be gated to adder 19 at T3-ZT43. If b=0, there is no output from FF #25, as already explained, and the contents of C do not reach the adder. The output of the adder is a l2-digit word at Tag-"T43 representing the desired sum which passes through gate 33 to the arithmetic unit 34, this gate being open during F (and F of the B or tally operation.

During F (phase 3) of the tally operation the sum e=+ b) is obtained and sent to the arithmetic unit; also C is reset to a This is accomplished as follows:

In F; the tally instruction is gated from the 46 microsecond tap of delay line 6 through gate 35 and gate 12 of the address selector circuit to gate 13 of the address gating circuit 14. Again, in F the address gating PF 15 is turned on by gate 16 at T and off by gate 17 at T Thisis ac- 1 1 and its output train of 12 pulses occurring at times Tag-T43 is applied to gate 13. Since the 12-digit a word appears at the 46 microsecond tap and at gate 13 at T -T this word is gated through

gates

13 and 18 to adder 19.

Gate 36 of the relative address FF 21 senses the relative address control digit a at the 22 microsecond tap of delay line 6 at T If a pulse is present at Tar, indicating that a=1, the relative address FF is turned on by gate 36 at T and off by gate 22 at T The output pulse train of this FF, after a one microsecond delay by element 23, is applied to gate 24 of FF #25 at T T As a result, FF #25 is turned on by gate 24 at T and off by gate 26 at T The resulting output pulse train, occurring at T r-T is applied to

gates

31 and 32 as before.

The operation of d" FF 28 is the same as in F Its output pulse train, occurring at Tq-Tqq, operates as in F to inhibit gate 31 but to act in the presence of an output from FF #25 (a=1) to apply the output of C through gate 32 to adder 19 during the interval T T The output of the adder therefore is a 12-digit word at T T representing the desired sum a =u+a(C which passes through gate 33 to the arithmetic unit 34. If a=0, there is no output from FF #25 and therefore gate 32 does not open since one of its inputs is. de-energized. In this case a only appears in the output of adder 19.

- The. base counter C is reset to on in the following manner:

The, count in C is always a 12-digit binary number. The counter comprises a 12 microsecond delay line 37 connected through gates 38 and 39 in a closed loop. A word once inserted in the counter circulates around this loop until erased. Words are inserted through gate 40 which is controlled by FF #41. This FF is turned on by gate 42 at T5 and ofl? by gate. 43 at T47. Therefore the 12 digits of any word that happens to be in the counter always appear at the Otap or input of line 37 at- T 411 However, since the 12 microsecond delay of the loop is only A minor cycle the word circulates, four times during each minor cycle and therefore its digits appear at the 0 tap also at the times T -Tm, T T and T -T From this it is apparent that the digits appear at the 9 microsecond tap of line 37 at the times T T T T T T Ti T the latter agreeing with the output of FF #25 which, as already explained, serves to gate the conents of; Cb hro ate 32 to add r 19- During the first minor cycle E of F FF #41 is turned on at T and off at T in the above. described manner. The resulting output, occurring at T 41 inhibits gate 38 du ngthis perio us er s ng e previous n and opens gate 40. to any pulses occurring during this period. ar occurs in the output of adder 19 at T -T and, after a 3 microsecond delay by element 44, is applied to gate 40 at T35-T45 through which it enters C thus resetting the base counter to on The arithmetic unit 34 subtracts B applied to it in F from or, applied to it in F If a p the difierence is negative and the ascp line is energized with a continuous train of one megacycle pulses. If a ifl the ascp line is not energized.

The arithmetic unit 34 is of course the arithmetic unit for the entire computer and in it are performed the arithmetic processes of addition, subtraction, multiplication and. division for all operations of the computer. An arithmetic unit is found in and is an essential component of all stored program automatic digital computers. Ln computers in which provision is made for a conditionaltranst'er operation, and such provision may be considered universal in modern computers, the arithmetic unit determines if the condition calling for the transfer exits. Conditional transfer, which also goes under such names as algebraic, comparison, absolute comparison, jump if minus t n ves a devia n. rom. the. r g lar stored.

12 sequence of instructions inthe computer; The condition calling for this deviation is usually that a first specified number be less than a second specified number. The arithmetic unit determines if this condition exists by subtracting the second number from the first and sensing the sign of the difference. If minus, a control circuit is energized calling for a transfer or jump to a specified instruction address. Arithmeticunits with means for sensing and signaling the conditional transfer situation are therefore well known in the art. An example is given in FIG.

4 on page 1303 of the Proceedings of the Institute of,

Radio Engineers, vol. 41,-No. 10, October 1953. Here the sign determining unit has a line designated to control unit which is energized when the number in memory address a is less than the number in memory address 5 and causes a conditional transfer operation to be performed. See the second paragraph of the second column on page 1303 and the descriptions of the comparison operations in Table I on page 1302. The tally instruction involves a conditional transfer in that if a j3 the computer refers to the instruction in the address w rather than the next instruction in the sequence of instructions. The arithmetic unit of FIG. 4 in the above cited reference can sense this condition and therefore can be used for block 34 in FIG. 2 in this application, the line marked to control unit corresponding to the ascp line in FIG. 2.

The computer now progresses to F (phase 4) in its execution of the tally instruction. In this phase one of two possible courses of action are taken depending upon whether ascp is energized (a ]9 or deenergized a fi If ascp is energized, C is reset to 'y If deenergized, one is added to C and C is reset to 0 if d=1 or left at m to which it was set in F if d=0. The operation is as follows:

During F the tally instruction is gated from the 22 microsecond tap of delay line 6 through

gates

45 and 12 of the address selector circuit to gate 46 of the address gating circuit. Also, FF #53 is turned on by gate 47 at T of F and remains on until the end of F when it is turned off by gate 48. The first pulse of the FF #53 output, after a delay of l microsecond, is applied to gate 49 of FF #50 and, after delay of an additional microsecond, is applied as an inhibiting pulse to the same gate. Therefore, only one pulse passes gate 49 which turns on FF #50 at T FF #50 is turned off at T by gate 51. This FF, therefore, is turned on only once during F its output E occurring at T -T of the first minor cycle of F This control voltage insures that the control counter will be reset only in F and then only once.

If the ascp line is energized (a }3 the address gating FF 15 is turned on in E; by gate 52 at T and off by gate 17 at T The 12-pulse output, occurring at T32T43, is applied to gate 46 and serves to gate '7, occurring also at T -T through

gates

46 and 18 to adder 19.

The c digit of the relative address control group is sensed at the 22 microsecond tap of delay line 6 at T by gate 54 of the relative address FF. If a pulse is present, indicating that c=l, PF 21 is turned on by gate 54 at T and off by gate 22 at T The resulting output, extending from T to T allows PF #25 to be turned on by gate 24 at T and 01f by gate 26 at T producing an output occurring at T -T The control counter C is similar to the base counter C already described, and has the same timing. The 12'- digit binary Word in .C circulates around a closed 12 microsecond loop consisting of 12 microsecond delay line 55 and gates 56 and 57. The count in C is changed by inserting the new count through gate 58 at T T while, at the same time erasing the preceding count by inhibiting gate 56. As in C gates 58 and 56 are controlled by the output ofFF #59 whichis turned on by gate 69 at T and off by gate 60 at T producing an output accurn'ng. at T -T As in the case of C the count appears at the 9 microsecond, tap of line 55, at T T The d FF 28 does not go on in F and, with no output from this FF, gate 31 is not inhibited and permits the contents of C to pass through this gate to added 19 provided FF #25 is on (C=l). The absence of an output from the d FF also blocks the application of the C contents to the added through gate 32. The output of adder 19 in phase 4, therefore, occurring i ea- 43, isv

'Ye='Y+ c) This address, which is the address in the memory from which the computer obtains its next instruction, is applied to the address comparator which performs the operations necessary to obtain the desired instruction from thememory. Also, the control counter C is reset to 7 which, after a 3 microsecond delay by element 44, is applied to gate 58 at T T Since, as already explained, E is on at T -T of the first minor cycle of F FF #59 is turned on by gate 69 at T and olf by gate 60 at T of thisminor cycle. The output of this FF serves to open gate 58 at T T for the new count and to simultaneously inhibit gate 56 for the purpose of erasing the old count.

The count in C which was set to m in F is not disturbed since FF #41 does not go on because of the inhibiting effect of the ascp signal on gate 63. With no output from FF #41, gate 38 of C is not inhibited and thecontents of the counter are not erased. Gate 40 is not open during P; so that no input to C can occur. v If 56 the ascp line is not energized. In this case address gate FF 15 is not turned on" by gate 52 and, therefore is not applied through address gating circuit 14 to adder 19. However, gate 61 lets one pulse through to the adder at T Further, regardless of the value of c, relative address PF 21 is turned on at the start of R; by gate 62, ascp being off, and its output enables PF #25 to be turned on at T and off at T4,; in the usual manner, -thus gating the contents of C to adder 19 through gate 31. The output of the adder, therefore, is C +l and the computer proceeds through the address comparator to seek its next instruction from this address. The control counter is also reset to C +1 in the same manner as for w described above.

One further operation must be carried out: that of setting C to if d=1. The control digit d appears at the 22 microsecond tap of line 6 at T If d=1 a pulse appears at T which is applied to gate 63 of FF #41 during the first minor cycle E of F With ascp not energized, FF #41 is turned on by this gate at T and an by gate 43 at T Gate 38 therefore is inhibited during the period Tzg-T46, and since the contents of C appear at this gate at T T C is cleared or reset to zero. If d had been 0 instead of 1, FF #41 would have not been turned on by gate 63 and the count in C would have remained at on to which it was set in F The operation of FIG. 2 in executing a conventional arithmetic instruction, such as one calling for the addition of two numbers, is as follows:

As already stated, in a conventional arithmetic instruction on and 5,, are the eflective addresses of the two operands and w is the effective address of the memory cell in which the result is to be stored. These addresses may be absolute or relative, depending upon 'whether a, b and c are 0 or 1, and they may each be realtive to a control counter C or a base counter C depending upon whether d=0, or d=1, respectively. In executing an instruction of this type B is determined in F a in F in F and C is advanced by one in F Reference to the timing diagram of FIG. 4 will aid in understanding the following description.

The instruction enters the ISL during E of F through

gates

9 and 8, the digit P (FIG. 1) entering first. The staticizer and decoder first senses the operation code (Pg-P5) and energizes the proper control line. or lines to 14 condition the computer to perform the arithmetical operation called for.

In F 13 is gated from the 10 microsecond tap of line 6 through

gates

10 and 12 of the address selector circuit 11 and gate 13 of the address gating circuit 14 to adder 19, address gating FF 15 having an output from T32-T43. The b digit is sensed at the 22 microsecond tap by gate 20 at T If b=l a pulse appears at T which initiates an output from relative address FF 21 at T -T which output in turn results in an output from PF #25 at ea- 43- The d PF 28 senses the d digit at the output of one microsecond delay element 29 at T If d=l a pulse appears at T and d FF 28 is turned on at T and off at T The d FF output inhibits gate 31 and prevents the contents of C,, from reaching adder 19. The contents of C however, may pass through gate 32 to the adder provided there is an output from FF #25 (b=1). If d=0, there is no output from the d FF, in which case C is gated through gate 31 to the adder if there is an output from PF #25 (b=1), and C is blocked at gate 32. The output of adder 19 in F fi therefore defle=fl+ b) This output occurs at T T of the first minor cycle of F and is the memory address of the first operand. This address is applied to the address comparator which operates to effect read-out of the operand from the corresponding memory cell.

In F at is obtained at the output of adder 19 and applied to the address comparator by a similar process to that described above for B The a portion of the instruction is gated from the 46 microsecond tap of delay line 6 through gates 64 and 12 of address selector circuit 11 and gate 13 of the address gating circuit 14 to adder 19,- address gating FF 15 being on in F as in F for the period Tag-T43- The control digit a is sensed at the 22 microsecond tap of line 6 by gate 65 at T The presence of a pulse, indicating that a=l, results in FF #25 being on for the period Tag-T43 as in F If a=1, either C or C is gated to adder 19 depending upon whether d=0 or d=1, the operation of the d FF being the same as in F The output of the adder in F therefore is:

(1:0 a =a+a(C b) The second operand is obtained in F from the memory cell corresponding to on by the address comparator, and the arithmetical process on the two operands also performed in this phase.

In F '7 is obtained at the output of adder 19 by a process similar in all respects to those described for fi and m The portion of the instruction is gated from the 22 microsecond tap through gates 66 and 12 of the address selector circuit and gate 13 of the address gating circuit to adder 19. The 0 digit is sensed at the 22 microsecond tap of delay line 6 by gate 67 of the address gating FF at T The d" digit is sensed by the d FF as before. As in the cases of b and a in F and F if c=1 either C or C is gated to the adder depending upon whether d=0 or d=1, respectively. The output of the adder in F therefore is Through operation of the address comparator the arithmetical result is read into the memory cell corresponding to 'y In F 1 is added to the control counter C to obtain the address of the next instruction. The process is as follows:

Neither the address selector 11 nor the address gating FF 15 15 has an output-in F However, FF #53 and PF #50 operate to produce E, at TT47 as explained in E, of the tally instruction. Therefore one pulse passes gate 61 of the adress gating circuit at T as is applied through gate 18 to adder 19.

The d FF does not go in F As a result gate 32 is closed and only the control counter C can be gated to adder 19. The relative address PF 21, however, is turned on at the start of F by gate 68, which results in PF #25 being on during the period T -T The count in C is therefore gated through gate 31 to adder 19 at T T where it is added to the 1 applied to the adder at T by the address gating circuit. The output of the adder therefore is C +1 which is applied to the address comparator as the address of the next instruction.

The control voltage E also allows FF #59 to be turned on by gate 69 at T and off by gate 60 at T C +l is applied through 3 microsecond delay 44 to gate 58 at T T Therefore the T T output of PF #59 inserts C +1 into the control counter and erases the previous count C,,. For any succeeding minor cycles in F, the count in the control counter remains at C +1 since gate 28 produces an output pulse at T only in the presence of E and, therefore, only in the first minor cycle of F Although the specific control circuits of FIG. 2 are designed for use with three-address instructions the invention is equally applicable to a computer using instructions of the four-address type. In the four-address system a control counter is not used to designate the next instruction as in the three-address system. Instead, a fourth address, designated the 6 address, is added to the instruction for this purpose. Therefore, a tally instruction of the four-address type would contain a, [3 and addresses serving the same purposes as in the three-address tally instruction and in addition a 6 address designating the location of the next instruction. Accordingly, in the execution of the instruction, the operation for the a l3 condition would be the same as in the threeaddress case while for the m ga, condition, instead of increasing C by one, the computer would seek its next instruction from the location indicated by the 6 address.

I claim:

1. In an automatic digital computer employing instructions having at least three addresses and a base counter to which said addresses may be relative: apparatus for executing a tally instruction, said apparatus comprising means for adding the numerical value of one of said addresses to the contents of said base counter, means for comparing the resulting sum with the numerical value of a second of said addresses, means associated with said comparing means and said base counter and operative when said sum is less than the numerical value of said second address to increase the count in the base counter by the numerical value of said one address and to seek the next instruction at the place indicated by said third address, and means associated with said comparing means and operative when said sum is equal to or greater than the numerical value of said second address to refer the computer to an instruction other than the instruction at the place indicated by said third address.

2. In anautomatic digital computer employing threeaddress instructions and having a control counter for designating the next instruction and a base counter, and in which each of said addresses may be relative to either of said counters: apparatus for executing a tally instruction, said apparatus comprising means for adding the numerical value of one of said addresses to the contents of saidbasecounter, means for comparing the resulting sum with the numerical value of a second of said addresses, and means,- associated with said comparing means and said control and base counters, operative when said sum is less than the numerical value of said second ad.- dress to increase the count in the base counter by the 16 numerical value of said one address and to reset said control counter to a value determined by the third of said addresses and operative when said sum is equal to or greater than the numerical value of said second address to increase the count of said control counter by numerical value of one of said addresses to the contents of said base counter, means for comparing the resulting sum with the numerical value of a second of said addresses, and means, associated With said comparing means and said control and base counters, operative when said sum is less than the numerical value of said second address to increase the count in the base counter by the numerical value of said one address and to reset said control counter to a value determined by the third of said addresses and operative when said sum is equal to or greater than the numerical value of said second address to reset said base counter to a predetermined count and to increase the count in said control counter by one.

4. In an automatic digital computer using instructions each containing a first address, a second address and a third address, each address being a binary number, in which there are provided a control counter for designating the next instruction and a base counter, and in which each of said addresses may be relative to one of said counters, apparatus for executing a tally instruction, said apparatus comprising: means for comparing a first quantity which is one of a group of two quantities consisting of the absolute value of the first address of said tally instruction and the sum of said absolute value and the contents of said base counter with a second quantity which is one of a group of two quantities consisting of the absolute value of the second address of said tally instruction and the sum of said absolute value and the contents of said base counter, and means, associated with said comparing means and said control and base counters, operative when said first quantity is less than said second quantity to reset said base counter to said first quantity and said control counter to one of a group of two quantities consisting of the absolute value of the third address of said tally instruction and the sum of said absolute value and the contents of said control counter and operative when said first quantity is not less than said second quantity to increase the count in said control counter by one. 5. In an automatic digital computer using instructions each containing a first address, a second address and a third address, each address being a binary number, in which there are provided a control counter for designating the next instruction and a base counter and in which each of said addresses may be relative to one of said counters, apparatus for executing a tally instruction, said apparatus comprising: means for comparing a first quantity which is one of a group of two quantities consisting of the absolute value of the first address of said tallyinstruction and the sum of said absolute value and the contents of said base counter with a second quantity which is one of a group of two quantities consisting of the absolute value of the second address of said tally instruction and the sum of said absolute value and the contents of said base counter, and means, associated with said comparing means and said control and base counters, opera- .tive when said first quantity is less than said second quantity to reset said. base counter to said first quantity and said control. counter to one of a group of two quantities consisting of the absolute value of the third address of said tally instruction and the sum of said absolute value and the contents. of said control counter and operative when said first quantity is not less than said second quantity to reset said base counter to one of a group of two quantities 17 consisting of said first quantity and zero and to increase the count in said control counter by one.

6. In an automobile digital computer employing instructions providing at least three addresses relative to each computer directive and a base counter to which said addresses may be relative: apparatus for executing a tally instruction, said apparatus comprising means for adding the numerical value of one of said addresses to the contents oy said base counter, means for comparing the resulting sum with the numerical value of a second of said addresses, means associated with said comparing means and said base counter and operative when said sum is less than the numerical value of said second address to increase the count in the base counter by the numerical value of said one address and to seek the next instruction at the place indicated by said third address, and means associated with said comparing means and operative when said sum is equal to or greater than the numerical value of said second address to refer the computer to an instruction other than the instruction at the place indicated by said third address.

7. In an automatic digital computer employing instructions providing at least three addresses relative to each computer directive and having a control counter for designating the next instruction and a base counter, and in which each of said addresses may be relative to either of said counters: apparatus for executing a tally instruction, said apparatus comprising means for adding the numerical value of one of said addresses to the contents of said base counter, means for comparing the resulting sum with the numerical value of a second of said addresses, and means, associated with said comparing means and said control and base counters, operative when said sum is less than the numerical value of said second address to increase the count in the base counter by the numerical value of said one address and to reset said control counter to.a value determined by the third of said addresses and operative when said sum is equal to or greater than the numerical value of said second address to increase the count of said control counter by one.

8. In an automatic digital computer employing instructions providing three addresses relative to each computer directive, each address being a binary quantity, a control counter for designating the next instruction and a base counter and in which each of said addresses may be relative to one of said counters, apparatus for executing a tally instruction, said apparatus comprising: means for comparing a first quantity which is one of a group of two quantities consisting of the absolute value of the first address of said tally instruction and the sum of said absolute value and the contents of said base counter with a second quantity which is one of a group of two quantities consisting of the absolute value of the second address of said tally instruction and the sum of said absolute value and the contents of said base counter, and means, associated with said comparing means and said control and base counters, operative when said first quantity is less than said second quantity to reset said base counter to said first quantity and said control counter to one of a group of two quantities consisting of the absolutevalue of the third address of said tally instruction and the sum of said absolute value and the contents of said control counter and operative when said first quantity is not less than said second quantity to reset said base counter to one of a group of two quantities consisting of said first quantity and zero and to increase the count in said control counter by one.

9. In an automatic digital computer employing instructions providing at least three addresse to the control component of the computer which takes instructions from the computer memory, analyzes these instructions and issues appropriate commands causing the computer to execute the instruction and a base counter to which said addresses may be relative: apparatus for executing a tally instruction, said apparatus comprising means for adding the numerical value of one of said addresses to the contents of said base counter, means for comparing the resulting sum with the numerical value of a second of said addresses, means associated with said comparing means and said base counter and operative when said sum is less than the numerical value of said second address to increase the count in the base counter by the numerical value of said one address and to seek the next instruction at the place indicated by said third address, and means associated with said comparing means and operative when said sum is equal to or greater than the numerical value of said second address to refer the computer to an instruction other than the instruction at the place indicated by said third address.

References Cited in the file of this patent or the original patent UNITED STATES PATENTS 2,604,262 Phelps July 22, 1952 2,636,672 Hamilton Apr. 28, 1953 FOREIGN PATENTS 709,407 Great Britain May 26, 1954 OTHER REFERENCES A Functional Description of the Edvac, vol. II, University of Pennsylvania, Research Report 509, Nov. 1, 1949.

Auerbach: The Binac," Proc. IRE, January 1952, pp. 1228.