RU2707159C1 - Adaptive control device - Google Patents

Abstract

FIELD: control systems.

SUBSTANCE: adaptive control device contains switching matrices of inputs (CMin) and outputs (CMout), a decision device, a proportional unit, a functional logic controller (FLC), an integrating-differentiating unit (IDU), a signal bus. IDU contains K integrating-differentiating clusters (IDC). IDC comprises integrating units, differentiating blocks, tables of conformity.

EFFECT: enabling the control device's ability to generate solutions pre-formed based on expert knowledge.

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Description

The claimed invention relates to the field of automatic control of devices using proportional-integral-differential laws (PID-laws) of regulation, and can find application in radio systems in conditions of intense information perturbation.

A known adaptive control system according to the PID law [1], adopted as a prototype. The structural and functional diagram of the prototype device is shown in FIG. 1, where the following notation is accepted:

1 - switching matrix of inputs (KMvh);

2 - switching matrix of outputs (KMvyh);

3 - decisive device (RU);

4 - proportional block (PB);

5 ₁ ... 5 _K - integrating blocks (IB);

6 ₁ ... 6 _K - differentiating blocks (DB);

8 ₁ ... 8 _K - integrating-differentiating clusters (IDC);

9 - signal bus (SS);

10 - functional logic controller (CFL);

11 - integrating-differentiating unit (IDB);

The prototype device contains a switching matrix of inputs (KMvkh) 1, the first output of which is connected to the signal input of the proportional block (BOP) 4, the output of which is connected to the first signal input of the switching matrix of outputs (KMvy) 2, the first output of which is connected to the first signal input of the decisive devices (RU) 3. The inputs of the prototype device are the signal inputs KMvh 1.

The integrating-differentiating unit (IDB) 11 of the prototype device contains K integrating-differentiating clusters (IDC) 8 ₁ ... 8 _K , each of which contains one of K integrating blocks (IS) 5 ₁ ... 5 _K with its own normalizing coefficient (AND ₁ ... And _K ) and one of K differentiating blocks (DB) 6 ₁ ... 6 _K with its own normalizing coefficient (D ₁ ... D _K ), respectively.

Moreover, IDB 11 has K pairs of signal inputs (i.e. 2K signal inputs), which at the same time are pairs of signal inputs of the corresponding IDK 8 ₁ ... 8 _K , where the first signal input of IDK 8 is the signal input of the corresponding IS 5, and the second signal input of IDK 8 is the signal input of the corresponding DB 6. In addition, IDB 11 has K pairs of outputs (i.e. 2K outputs), which at the same time are output pairs of the corresponding IDK 8 ₁ ... 8 _K , where the first the output of IDK 8 is the output of the corresponding IB 5, and the second output of IDK 8 is the output 6 corresponding DB.

Moreover, K pairs of signal inputs IDB 11 are connected respectively to K pairs of outputs KMvkh 1, and K pairs of outputs IDB 11 are connected to the corresponding K pairs of signal inputs KMvy 2, K pairs of outputs which are connected to the corresponding K pairs of signal inputs RU 3, the output of which is the output of the prototype device.

Also, the prototype device contains a functional logic controller (CFL) 10, the first output of which is connected to the control input KMvh 1, the second output to the control input PB 4, the third output to the control inputs of each of K integrating 5 ₁ ... 5 _K and K differentiating 6 ₁ ... 6 _K blocks; the fourth output is with the control input of KMvykh 2, and the remaining outputs of KFL 10 are connected to the corresponding control inputs of RU 3, the information outputs of which are connected to the corresponding information inputs of KFL 10.

In addition, the group of outputs KMvy 2 through the signal bus (SS) 9 is connected to the group of signal inputs KMvkh 1.

The prototype device operates as follows.

When turned on, CFL 10 initializes the values of the coefficients And ₁ ... And _K and D ₁ ... D _{K of} blocks 5 and 6, sets the parameters of BP 4 and initializes the connection structure of KMvkh 1 and Kmvy 2 by supplying the corresponding control signals to the control inputs of these blocks.

Next, CFL 10 reads the initial values of all signals from the information outputs of RU 3. The received data is stored in CFL 10 for subsequent calculations.

An input adjustable signal is supplied to the first signal input KMvkh 1. At the second signal input KMvkh 1 a feedback signal is supplied, to the third signal input KMvkh 1 there is an external disturbance signal.

Blocks KMvkh 1 and Kmvykh 2 organize the connection of IDK 8 ₁ ... 8 _K into a single structure, which provides an input signal to the signal inputs of PB 4 and IDB 11.

In PB 4, a proportional conversion of the input signal is carried out in accordance with the previously established parameters; then the converted signal from the output of the PB 4 through KMvykh 2 is fed to the first signal input RU 3.

In block 11, the integral-differential conversion of the input signal is carried out, which consists in eliminating static errors and anticipating by disturbance. The converted signal from the IDB 11 outputs through КМvyvy 2 is supplied to the other signal inputs of RU 3.

NL 9 forming the interface between KMvyh KMvh 1 and 2, allows to organize serial connections DCO 8 ₁ ... 8 _K (DCO provides the output connection 8 ₁ ... 8 _K to the DCO inputs 8 ₁ ... 8 _K consistent with the need to implement structures).

The number of signal inputs and outputs of blocks 1, 2, 3, and 11 is determined by the control task and the degree of uncertainty of the parameters of the managed object.

Each IB 5 ₁ ... 5 _K and DB 6 ₁ ... 6 _K has its own normalizing coefficient, calculated in CFL 10 based on the previous signal values. Proactive control is implemented in DB 6 ₁ ... 6 _K with normalizing coefficients D ₁ ... D _K. Compensation of static errors is implemented in IB 5 ₁ ... 5 _K with normalizing coefficients AND ₁ ... AND _K. Further, from the output of RU 3, information about the signals is fed to the information inputs of CFL 10.

In CFL 10, the values of the control signals are calculated for all control loops, and the values of the resulting coefficients are determined. In this case, CFL 10, which implements control logic, uses conditional rules embedded in the software to convert an array of input signals to control ones.

The control signals from the outputs of CFL 10 are fed to KMvkh 1, KMvykh 2, RU 3, PB 4 and IDB 11, and the values of the coefficients PB 4, I ₁ ... AND _K and D ₁ ... D _{K of} block 11 can be reconfigured.

Having received control signals, KMvkh 1 and Kvyvy 2 can reconfigure structure of connections.

Having received control signals, RU 3 generates an output signal.

Since the system consists of a number of IDK 8 ₁ ... 8 _K blocks connected with each other using КМвх 1 and КМвых 2, the number and structure of relationships can vary depending on the task.

The disadvantage of the prototype device is the limited functionality in the implementation of adaptive regulation, which consists in using only the PID laws of the formation of the control action. In cases of sudden and / or strong changes in external influences, a much longer time may be required to restore stable regulation using only PID laws. In addition, there is the likelihood of an unfavorable combination of external conditions that can lead to the formation by PID controllers of mismatched control actions.

The problem to which the invention is directed, is to expand the functionality of the adaptive control device.

The technical result achieved is the ability of the adaptive control device to make alternative decisions, not based on PID laws, but pre-formed on the basis of expert knowledge [2].

To store expert data, it is proposed to use correspondence tables (lookup tables, look up table, LUT) [3] and [4], which in practice are specialized storage devices and are currently used in the field of computer technology.

To solve this problem, an adaptive control device according to the PID law, containing switching matrices of inputs (KMvkh) and outputs (Kmvy), a solving device, a proportional block, a functional logic controller (CFL), an integrating-differentiating block (IDB), including K integrating -differentiated clusters (IDCs), each of which contains an integration and differentiating unit with its own normalizing coefficients, according to the invention, a correspondence table is introduced in each IDC. The output of the decider is the output of the adaptive control device. For each IDK, the first signal input is the signal input of the corresponding integrating unit, the second signal input is the signal input of the corresponding differentiating block, and the third signal input is the signal input of the corresponding correspondence table. Groups of three signal inputs of all IDKs are 3K signal inputs of IDB, which are connected to the corresponding 3K outputs of КМвх. For each IDK, the first output is the output of the corresponding integrating unit, the second output is the output of the corresponding differentiating block, and the third output is the output of the corresponding correspondence table. Groups of three outputs of all IDK are 3K IDB outputs, which are connected to the corresponding 3K signal inputs KMvy. The signal input of the proportional block is connected to the first output of the CMV input, and the output is connected to the first signal input of the CM output. The group of outputs KMvy through the signal bus is connected to the group of signal inputs KMvkh, the remaining signal inputs of which are inputs of the device. The first KMvy output is connected to the first signal input of the resolver, 3K signal inputs of which are connected to the corresponding 3K KMvy outputs. The first output of the CFL is connected to the control input of KMvh, the second output is with the control input of the proportional block, the third output is with the control inputs of each of K integrating, K differentiating blocks and each of K correspondence tables, the fourth output is with the control input of Kmvy. The remaining outputs of the CFL are connected to the corresponding control inputs of the deciding device, the information outputs of which are connected to the corresponding information inputs of the CFL.

The structural and functional diagram of the proposed device is presented in FIG. 2, where the following notation is accepted:

1 - switching matrix of inputs (KMvh);

2 - switching matrix of outputs (KMvyh);

3 - decisive device (RU);

4 - proportional block (PB);

5 ₁ ... 5 _K - integrating blocks (IB);

6 ₁ ... 6 _K - differentiating blocks (DB);

7 ₁ ... 7 _K - correspondence tables (TS);

8 ₁ ... 8 _K - integrating-differentiating clusters (IDC);

9 - signal bus (SS);

10 - functional logic controller (CFL);

11 - integrating-differentiating unit (IDB);

The inventive device contains a switching matrix of inputs (KMvh) 1, the first output of which is connected to the signal input of the proportional block (BOP) 4, the output of which is connected to the first signal input of the switching matrix of outputs (KMvy) 2, the first output of which is connected to the first signal input of the solving device (RU) 3. The inputs of the device are the signal inputs KMvkh 1. The group of outputs KMvy 2 through the signal bus (SS) 9 is connected to the group of signal inputs KMvkh 1.

The integrating-differentiating unit (IDB) 11 of the claimed device contains K integrating-differentiating clusters (IDC) 8 ₁ ... 8 _K , each of which contains one of K integrating blocks (IS) 5 ₁ ... 5 _K with its own normalizing coefficient And ₁ ... And _K, respectively, one of K differentiating blocks (DB) 6 ₁ ... 6 _K with its own normalizing coefficient D ₁ ... D _K, respectively, and one of K correspondence tables (TS) 7 ₁ ... 7 _K.

IDB 11 has K groups of three signal inputs (i.e. 3K signal inputs), which at the same time are groups of three signal inputs of the corresponding IDK 8 ₁ ... 8 _K , where the first signal input of IDK 8 is the signal input of the corresponding IB 5, the second signal input of IDK 8 is the signal input of the corresponding DB 6, and the third signal input of IDK 8 is the signal input of the corresponding TS 7. In addition, IDB 11 has K groups of three outputs (i.e. 3K outputs), which at the same time are groups of three outputs corresponding DCO 8 8 ₁ ... _K, where the first output is the output of the DCO 8 corresponding IB 5, the second output of the DCO output corresponding to 8 is 6 dB and the third output is the output of the DCO 8 corresponding vehicle 7. Thus K groups of three signal inputs 11 are connected IDB respectively, with K groups of three outputs KMvkh 1, and K groups of three outputs IDB 11 connected to the corresponding K groups of three signal inputs KMvy 2, K groups of three outputs which are connected to the corresponding K groups of three signal inputs RU 3, the output of which is a device output wa.

The proposed device also contains a functional logic controller (CFL) 10, the first output of which is connected to the control input KMvkh 1, the second output - to the control input PB 4, the third output - with control inputs of each of K integrating 5 ₁ ... 5 _K , K differentiating 6 ₁ ... 6 _K blocks and K correspondence tables 7 ₁ ... 7 _K ; the fourth output is with the control input of KMvykh 2, and the remaining outputs of KFL 10 are connected to the corresponding control inputs of RU 3, the information outputs of which are connected to the corresponding information inputs of KFL 10.

The proposed device operates as follows.

When you turn on CFL 10 initializes the values of the coefficients of the integrating blocks 5 ₁ ... 5 _K , differentiating blocks 6 ₁ ... 6 _K (And ₁ ... And _K , D ₁ ... D _K, respectively) and TS 7 ₁ ... 7 _K , sets the parameters PB 4, КМвх 1 and КМvyvy 2 by applying to the control inputs of the listed blocks the corresponding control signals. CFL 10 reads the initial values of the signals from the information terminals RU 3.

The first, second and third signal inputs of KMvh 1 receive respectively an adjustable input signal, a feedback signal and an external disturbance signal. Further, these signals are fed to the signal inputs of the PB 4 and IDB 11.

PB 4 implements a proportional conversion of the input signal. From the output of the PB 4, the converted signal through KMvykh 2 goes to the first signal input RU 3.

In each IDK 8 of block 11, IB 5 integrally converts the input signal with the corresponding normalizing coefficient IDB 6 implements differential conversion of the input signal with the corresponding normalizing coefficient D, TS 7 generates a signal with the required data. The signals from the outputs of IDB 11 through KMvyh 2 are fed to the other signal inputs of RU 3.

From the output of RU 3, information about the signals goes to the information inputs of the CFL 10. Using the received data, the CFL 10 implements an adaptive control algorithm, the result of which is the formation in the CFL 10 of the control signals at all its outputs.

Due to the control signal, PB 4 can change its parameters, IS 5 ₁ ... 5 _K and DB 6 ₁ ... 6 _K can update the values of the coefficients And ₁ ... And _K and D ₁ ... D _K, respectively, KMvkh 1 and Kvyvy 2 can reconfigure the structure compounds. Moreover, SSH 9 allows you to organize a serial connection of IDK 8 ₁ ... 8 _K (connecting the outputs of IDK 8 ₁ ... 8 _K to the signal inputs of IDK 8 ₁ ... 8 _K ). The number and structure of the relationships of the IDK 8 ₁ ... 8 _K can vary within the existing task.

Having received control signals, RU 3 generates a signal that is fed to the output of the device.

TS 7 block IDK 8 is used in the following cases:

- PID control does not give a positive result or is counterproductive when the values of the analyzed parameters are outside acceptable limits;

- PID control has a low efficiency, which leads to an increase in the adaptation time and, as a result, the probability of violation of the steady state of the device.

In these cases, CFL 10 generates control signals supplied to the control inputs of the TS 7 ₁ ... 7 _{K of} those IDK 8 ₁ ... 8 _K blocks in which it is necessary to implement a tabular conversion of the input regulated signal. A signal with the location code of the required data from TS 7 is supplied to the signal input of each of these TS 7s. Next, TS 7 provides these data, which are received in CM2.

The functioning algorithm of CFL 10 is illustrated using FIG. 3.

In block I, the coefficients of integrating blocks 5 ₁ ... 5 _K , differentiating blocks 6 ₁ ... 6 _K (And ₁ ... And _K , D ₁ ... D _K, respectively) and TS 7 ₁ ... 7 _{K are} initialized, and parameters PB 4, KMvh are set 1 and KMvyh 2 by applying to the control inputs of the listed blocks the corresponding control signals.

In block II, the values of the input signals are read from the information terminals of RU 3.

In block III, the obtained values of the input signals are compared with the required values.

In block IV, a decision is made on the need for correction of the control action. If correction is not required, the KFL 10 functioning algorithm ends there, otherwise a transition to block 5 is performed.

In block V, a method for generating a control action is determined: based on PID laws or using data from TS 7 ₁ ... 7 _K.

If TC 7 ₁ ... 7 _{K is} required in the formation of the control action, then transition to block VI is performed. In this block, data is corrected for the vehicle 7 ₁ ... 7 _K.

In block VII, the values updated in the previous block are recorded in TS 7 ₁ ... 7 _K.

In block VIII, the TS 7 ₁ ... 7 _K is turned on and the relationships between them and the other elements of the IDB 11 are established by reconfiguring KMvkh 1 and Kvyvy 2.

If the use of PID control laws is sufficient in the formation of the control action, then the transition from block V to block IX is performed. In block IX, the normalizing coefficients of the integrating blocks And ₁ ... And _K and the differentiating blocks D ₁ ... D _K are adjusted.

In block X updated normalizing coefficients And ₁ ... And _K and D ₁ ... D _{K are} written in the corresponding IB 5 ₁ ... 5 _K and DB 6 ₁ ... 6 _K.

In block XI, the previously used TS 7 ₁ ... 7 _K is turned off and the configuration of the connections between the IDB 11 elements is updated using KMvkh 1 and Kvyvy 2.

The actions in block I are performed, as a rule, when the adaptive control device is turned on. The actions in blocks II - XI are a cycle of operations CFL 10, which is periodically performed during operation of the device.

Thus, the correspondence tables in the adaptive control device realize additional functionalities that become popular in the event of a threat of a significant decrease in the effectiveness of PID control due to sudden and / or strong changes in external influences. As a result, the scope of the proposed device is expanded.

Implementation

The proposed device can be implemented on the following elements:

- switching matrices, correspondence tables can be configured on the basis of FPGAs (programmable logic integrated circuits), for example, the company "ALTERA" [5];

- a solver, proportional, integrating and differentiating units can be implemented on specialized analog and / or digital devices designed to control the required physical parameters of the system (for example, multifunction sensors, including ADCs and / or DACs, are needed to control the frequency) [6, 7, 8, 9];

- the functional logic controller can be implemented on the basis of a microcontroller or microprocessor, for example, a domestic integrated circuit microprocessor 1892ВМ10Я [10].

Information sources

1. RF patent for the invention No. 2510956 "Adaptive control method according to PID law and a system for its implementation." / Asoskov A.N., Malysheva I.N., Plahotniuc Yu.A., Orlyansky V.N., 2014.

2. Makarenko S. I. Intelligent information systems: a training manual. - Stavropol: Siberian State University of Moscow State University named after M.A. Sholokhov, 2009 .-- 206 p.

3. Ugryumov E. P. Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and add. - SPb .: BHV-Petersburg, 2010 .-- 816 p.

4. RF patent for invention No. 2559772 "Device for the main division of modular numbers in the format of a system of residual classes." / Chervyakov N.I., Babenko M.G., Lyakhov P.A., Lavrinenko I.N., Lavrinenko A.V., 2015.

5. http://www.altera.ru - electronic components of the ALTERA company.

6. http://www.analog.com/en/products.html - radio-electronic components of the company "Analog Devices".

7. http://www.maximintegrated.com/en.html - radio-electronic components of the company "Maxim Integrated".

8. http://www.ti.com/ru-ru/homepage.html - electronic components of the company Texas Instruments.

9. http://www.murata.com - electronic components of the company Murata Manufacturing Company, Ltd.

10. http://www.multicore.ru - domestic microcircuits of the company SPC Elvis JSC (Zelenograd).

Claims (1)

An adaptive control device comprising switching matrices of inputs (KMvkh) and outputs (KMvy), a solver whose output is the output of the device; integrating-differentiating unit (IDB), including K integrating-differentiating clusters (IDC), each of which contains an integrating and differentiating unit with its own normalizing coefficients, and K pairs of signal inputs of IDB are pairs of signal inputs of the corresponding IDK, where the first signal input of IDK is the signal input of the corresponding integrating unit, and the second signal input of the IDK is the signal input of the corresponding differentiating unit; K pairs of IDB outputs are pairs of outputs of the respective IDKs, of which the first output is the output of the corresponding integrating unit, and the second output is the output of the corresponding differentiating unit; a proportional block, the signal input of which is connected to the first output of KMvkh, the remaining K pairs of outputs of which are connected to the corresponding K pairs of signal inputs of IDB, K pairs of outputs of which are connected to the corresponding K pairs of signal inputs of Kmvy, the group of outputs of which is connected to the group of signal inputs via the signal bus KMvh, the remaining signal inputs of which are the inputs of the device; the output of the proportional block is connected to the first signal input of the CMO, the first output of which is connected to the first signal input of the solver, the remaining K pairs of signal inputs of which are connected to the corresponding K pairs of outputs of the CMO; functional logic controller (CFL), the first output of which is connected to the control input of KMvh, the second output is with the control input of the proportional block, the third output is with the control inputs of each of K integrating and K differentiating blocks, the fourth output is with the control input of Kmvy, and the rest outputs - with the corresponding control inputs of the deciding device, the information outputs of which are connected to the corresponding information inputs of the CFL; characterized in that a correspondence table is introduced in each IDK, the signal input of which is the third signal input, and the output is the third output of the corresponding IDK, and the third signal inputs of each IDK are K additional signal inputs of the IDB, which are connected to the corresponding outputs of КМвх, and the third outputs of each IDK are K additional IDB outputs that are connected to the corresponding signal inputs of Kmout, K additional outputs of which are connected to the corresponding signal inputs of guide devices, moreover, the control input of each of K tables of correspondence connected to the third output CFLs.

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