RU2704499C1 - Bose-chaudhuri-hocquenghem code decoder with canonical hamming decoder - Google Patents

Abstract

FIELD: electrical communication engineering.

SUBSTANCE: invention relates to noise-immune coding and can be used to improve communication quality and reliability of storing data in memory microcircuits. Decoder of the Bose-Chaudhuri-Hocquengham code with the canonical Hamming decoder has: a permutation unit connected to a unit for calculating the error position in the canonical Hamming code and the syndrome calculating unit. Unit for calculating an error position in a canonical Hamming code, a unit for calculating an inverse element in a third degree, a first multiplier unit, a key equation solving unit and a second multiplier unit are connected in series. Second input of the second multiplier unit is connected to a unit for calculating the error position in the canonical Hamming code. Second multiplier unit is connected to the first adder unit and the first decoder. Unit for calculating the error position in the canonical Hamming code and a second decoder are connected to the first adder unit. First decoder, the second decoder and the permutation unit are connected to the second summation unit, which is connected to the reverse permutation unit.

EFFECT: high efficiency of decoding a BCH code with a code distance of 5 and 6.

3 cl, 2 dwg

Description

The invention relates to the field of error-correcting coding and can be used to improve communication quality and reliability of data storage in memory chips.

The fast Bowse-Chowdhury-Hockingham software (hereinafter referred to as BCH) is known for the encoder and decoder (URL: http://www.channelscience.com/files/NealGloverFastSoftwareBCHEndecR400r2.pdf), which includes a block for calculating the syndrome, a block for compiling the key equation, and a block direct solution to the key equation.

The disadvantage of this decoder is the increased implementation complexity caused by the need to store the logarithm table in an additional memory block.

It is known to decode double errors and detect triple errors using BCH codes (application No. US 4556977 A, published on 09/15/1983, URL: https://patents.google.com/patent/US4556977A), which includes a syndrome calculator, a coefficient generator for each bit of the codeword and zero detector.

The disadvantage of this analogue is the increased complexity of implementation, since it is necessary to calculate a certain coefficient for each bit of the code word, which is equal to the product of the upper half of the syndrome and the matrix corresponding to this bit.

Known BCH decoder (application number US 8806308 B2, publ. 08/12/2014, URL: https://www.google.com/patents/US8806308), which consists of a generator of the syndrome, a block for solving the key equation and a block for finding the error position by the locator .

The disadvantage of this analogue is the need to use the unit for calculating errors by the syndrome, which entails additional time and hardware costs.

The closest technical solution is "Direct table decoder that fixes two errors in the BCH code and uses a couple of syndromes" (application number US 4030067 A, publ. 12/29/1975, URL: https://patents.google.com/patent/US4030067A) .

The direct table decoder consists of the first multiplication unit, the inputs of which are connected to the bus from the syndrome calculation unit, the input of which is connected to the first bus, and the inverse element calculation unit to the third degree, the input of which is connected to the S1 bus, and the output of the first multiplication unit through the bus with the zero bit inverter is connected to the input of the key equation solution block, the output of which is connected to the input of the second multiplication block, the bus S1 is connected to the second input, and its output is connected to the first decoder and the first block by sums the second input of which the bus S1 is connected, and the output is connected to the input of the second decoder, the outputs of the decoders and the first bus are connected to the second summing unit, the bus S1 and bus S3 are connected to the inputs of the flag block.

The direct table decoder works as follows: the input word is fed to the syndrome calculation unit, at the output of which the first and second components of the syndrome are formed. The first component of the syndrome is fed to the inverse element calculation unit in the third degree. The first multiplication block multiplies the result of the inverse element calculation unit in the third degree with the second component of the syndrome and feeds the result through the bus with a zero bit inverter to the key equation solution block. The output of which is fed to the input of the second multiplication block, to the second input of which the first component of the syndrome is fed. At the output of the second multiplication block, the first error locator appears, which arrives at the first decoder. The first decoder on the table converts the first locator into the vector of the first error and feeds it to the second summing block. Also, the output of the second multiplication block is fed to the first summing block, at the output of which a second locator is formed, which is fed to the second decoder. The output of the second decoder is fed to the second summing unit, which produces the sum of the input word with two error vectors and provides the corrected code word to the output bus.

The disadvantage of the prototype is the increased complexity of the implementation, due to the fact that due to the structure of the block of the transmitter of the syndrome, to find the position of the error, you must use the table in the first decoder and second decoder, and you also need to store the table to solve the key equation.

The objective of the invention is to develop a decoder error-correcting code that would allow to correct single and double errors, as well as detect triple errors and at the same time would have minimal hardware complexity at high speed.

The technical result is to reduce the hardware complexity of the decoder of an arbitrary BCH code with a code distance of 5 and 6.

The technical result is achieved in that in the decoder, comprising: a first multiplication unit, the inputs of which are connected to the bus from the unit for calculating the syndrome, the input of which is connected to the first bus, and the unit for calculating the inverse element in the third degree, the input of which is connected to the bus S1, and the output the first block of multiplication through the bus with the inverter of the zero bit is connected to the input of the block solving the key equation, the output of which is connected to the input of the second block of multiplication, the second input of which is connected to the bus S1, and its output is connected to the first decryption the switch and the first summing unit, to the second input of which the S1 bus is connected, and the output is connected to the input of the second decoder, the decoder outputs and the first bus are connected to the second summing unit, the S1 bus and S3 bus are connected to the flags block inputs, an additional permutation unit is installed, connected to the input bus and the first bus, a reverse permutation block connected to the output of the second summing block and the output bus, the error calculation block in the canonical Hamming code, the input of which is connected to the first bus, and the output to the S1 bus, block parity checks, the input of which is connected to the first bus, and the output to the flag block, the first and second decoders being made on high-speed hardware demultiplexers, the permutation unit and the reverse permutation unit are interleaved, the key equation calculation unit is executed on the hardware trace calculation circuit in the field Galois, and the flag block is made on a hardware circuit that detects single, double, triple errors.

The technical result is achieved by introducing additional blocks and links, namely, a permutation block installed between the input bus and the first bus, an error position calculation unit in the canonical Hamming code installed between the first bus and the S1 bus, the parity check block, to the input of which is connected the output of the permutation block, and the output of which is connected to the flag block and the reverse permutation block, connected between the output of the second summing block and the output bus, which allow us to give a causal effect bond between the introduction of new blocks (links) and the technical result. The changes made reduce the complexity requirements for the hardware implementation of the BCH code decoder and increase the speed of its operation, as they make it possible to simplify and speed up the first and second decoders.

The invention is illustrated by drawings, where in FIG. 1 is a diagram of a decoder, FIG. 2 is a diagram of a block for calculating an error position in a canonical Hamming code and the following notation is introduced:

n is the codeword length

r is the number of test characters

1 - permutation block

2 - Unit for calculating the error position in the canonical Hamming code

3 - Syndrome calculation unit

4 - Parity block

5 - Block calculating the inverse element in the third degree

6 - The first block of multiplication

7 - Flag block

8 - Block solving the key equation

9 - The second block of multiplication

10 - The first block summation

11 - First decoder

12 - Second decoder

13 - The second block summation

14 - Block reverse permutation

The Bowse-Chowdhury-Hockingham code decoder with the canonical Hamming decoder contains: permutation unit 1, the input bus is connected to the input, and the output is connected to the input of the error position calculation unit in the canonical Hamming code 2, the input of the syndrome 3 calculation unit, the input of the parity check block 4. The output of the unit for calculating the error position in the canonical Hamming code 2 is connected to the input of the unit for calculating the inverse element in the third degree 5, the output of which is connected to the first multiplication unit 6, the output of which is through the bus with the inverter zero the second bit is connected to the input of the flag block 7, the input of which is also connected to the output of the error calculation block in the canonical Hamming code 2, the syndrome 3 calculation block and the parity check block 4. The output of the first multiplication block 6 is connected via the inverter bus to the input of the key decision block equation 8, the output of which is connected to the second block of multiplication 9, the second input of which is connected to the output of the block for calculating the error position in the canonical Hamming code 2. The output of the second block of multiplication 9 is connected to the second input of the first block 10 and the first decoder 11. To the second input of the first summing unit 10 is connected the output of the error position calculating unit in the canonical Hamming code 2. The output of the first summing unit 10 is connected to the input of the second decoder 12. The outputs of the first decoder 11, the second decoder 12 and the permutation unit 1 connected to the inputs of the second summing unit 13, the output of which is connected to the reverse permutation unit 14, the output of which is connected to the output bus.

The permutation unit 1 is made, for example, on conductors, the connection of which between the input and output of the unit is made in such a way as to bring the systematic form of the input code word to a lexicographic form.

The unit for calculating the error position in the canonical Hamming 2 code is executed, for example, on an encoder built on hardware elements of addition modulo two [1, 2, 3].

The unit for calculating syndrome 3 is, for example, performed on addition elements modulo 2 [4].

The parity check block 4 is performed, for example, on several exclusive-OR combiners.

The inverse element calculation unit in the third degree 5 is made, for example, on a pre-calculated table.

The first block of multiplication 6 is made, for example, on the elements "And" and addition modulo 2 [5].

The block of flags 7 is made, for example, on a hardware circuit of the components "OR", "AND", "NOT".

The block for solving key equation 8 is made, for example, on a hardware circuit using the result of calculating the trace of elements in the Galois field. [6].

The second block of multiplication 9 is made, for example, on the elements "And" and the elements of addition modulo 2 [5].

The first summing unit 10 is made, for example, on addition elements modulo two with two inputs.

The first decoder 11 and the second decoder 12 are made on high-speed hardware demultiplexers [7].

The first summing unit 13 is made, for example, on addition elements modulo two with three inputs.

The permutation unit 14 is made, for example, on conductors, the connection of which between the input and the output of the unit is made in such a way as to permute the symbols of the code word so that the first part of the syndrome corresponds to the canonical Hamming code decoder.

The Bowes-Chowdhury-Hockingham code decoder with the canonical Hamming decoder works as follows: the input word is fed to the permutation unit 1, which permutes the bits of the input code word so that it matches the lexicographic form of the code. The output bits of permutation block 1 go to the input of the block for calculating the error position in the canonical Hamming 2 code, which calculates the first component of the Bowes-Chowdhury-Hawkingham code syndrome, which corresponds to the position of the error bit in case one error occurs. Also, the output bits of permutation block 1 are input to the syndrome 3 calculation block, the result of which is the second component of the syndrome. The first component of the syndrome is fed to the inverse element calculation unit in the third degree 5, the result of which is fed to the first multiplication block 6. Also, the second component of the syndrome is fed to the first multiplication block 6, as a result of which the ratio of the second component of the syndrome to the first component is obtained at the output of the first multiplication block 6 component of the syndrome in the third degree. Next, the unit is added to the result of the first multiplication block 6 using a bus with a zero-bit inverter, the result goes to the block for solving key equation 8, at the output of which one root of the equation appears. The root of the key equation is multiplied with the first component of the syndrome using the second multiplication block 9, resulting in the output of the second multiplication block 9 is a vector whose binary representation is the serial number of the first error bit. To calculate the sequence number of the second error bit, the result of the second multiplication block 9 is added to the first component of the syndrome using the first summing unit 10. The sequence number of the first error bit is fed to the input of the first decoder 11, and the sequence number of the second error bit is fed to the input of the second decoder 12. Output The first decoder 11 is a vector with one at the position of the first erroneous bit and all other zeros. The output of the second decoder 12 is a vector with one at the position of the second erroneous bit and all other zeros. The output values of the decoders are fed to the inputs of the second summing block 13, which also receives the bits received from the output of the permutation block 1. At the output of the second summing block 13, the corrected code word of the code has a lexicographically ordered upper half of the check matrix. To bring the code word received from the second summing block 13 to the source code, this word is fed to the input of the reverse permutation block 14, the result of which is the corrected code word of the original systematic code. In parallel with this, the state of the flags is set, indicating how far the received word is from the code words. This is done using the flag block 7, to the input of which two components of the syndrome are fed, a vector at the output of the bus with a zero-bit inverter and the output of the parity check block 4, to the input of which bits from the output of permutation block 1 are fed.

Based on the foregoing, we can conclude that the present invention allows decoders to be implemented for a whole class of BCH codes correcting double and detecting triple errors, and when decoding, the logarithm operation and the table necessary for this are not used, but two fast hardware demultiplexers are sufficient, which significantly saves hardware and increases the speed of the encoding system.

Used Books:

1. Mc-Williams F., Sloane N. Theory of error correction codes Per. from English - M.: Communication, 1979. - 744 p. (section 1.7, p. 33-34)

2. Arshinov M.N., Sadovsky L.E. 'Codes and mathematics (stories about coding)' \\ 'Quantum' library. Issue 30 - Moscow: Science, 1983 - p. 144 (p. 45-47)

3. R.W. Hamming, Error detecting and error correcting codes - The Bell system technical journal - Volume 29, Number 2, April 1950 (pages 147-160)

4. Titz U., Schenk K. Semiconductor circuitry. 12th ed. Volume I: Per. with him. - M.: DMK Press, 2008 .-- 832 p.: Ill. ISBN 5-94074-148-7 (section 8.6 p. 734)

5. Rahman P.A. Galois binary field arithmetic based on fast multiplication and inversion of field elements and its hardware implementation // International Journal of Applied and Fundamental Research. - 2015. - No. 12-3. - S. 403-408;

6. E. Berlekamp Algebraic Theory of Coding, Ed. WORLD, 1971. - 477 p. (chapter 11, p. 252)

7. Titz U., Schenk K. Semiconductor circuitry. 12th ed. Volume I: Per. with him. - M.: DMK Press, 2008 .-- 832 p.: Ill. ISBN 5-94074-148-7 (section 8.2.2 p. 727)

Claims (3)

1. Bowse-Chowdhury-Hawkingham code decoder with a canonical Hamming decoder, comprising a first multiplication unit, the inputs of which are connected to the bus from the syndrome calculation unit, the input of which is connected to the first bus, and the inverse element calculation unit in the third degree, whose input is connected to the bus S1, and the output of the first multiplication block via a bus with a zero-bit inverter is connected to the input of the key equation solving block, the output of which is connected to the input of the second multiplication block, to the second input of which the S1 bus is connected, and its output is sub is connected to the first decoder and the first summing unit, on the second input of which the S1 bus is connected, and the output is connected to the input of the second decoder, the decoder outputs and the first bus are connected to the second summing unit, the S1 bus and S3 bus are connected to the inputs of the flag block, characterized in that that additionally, a permutation unit connected to the input bus and the first bus, a reverse permutation unit connected to the output of the second summing unit and the output bus, an error calculation unit in the canonical Hamming code, the input of which is The key to the first bus, and an output - to bus S1, the parity check block, whose input is connected to the first bus, and the output - to the block flags. 2. The Bowes-Chowdhury-Hockingham code decoder with the canonical Hamming decoder according to claim 1, characterized in that the first and second decoders are made, for example, on high-speed hardware demultiplexers. 3. The Bowes-Chowdhury-Hockingham code decoder with the canonical Hamming decoder according to claim 1, characterized in that the permutation unit and the reverse permutation unit are interleaved conductors.

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