RU2703331C2 - Overcurrent protection device - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to electronic engineering and can be used in switched power supplies with protection against overcurrent. Device for protection against overcurrent includes resistive current sensor, bus of negative and positive potential of input and output voltages, control and commuting p-MOS transistors, a feedback resistor, four resistors and an additionally introduced low-potential connection line of the capacitive load component.

EFFECT: technical result consists in expansion of functional capabilities due to shorter time of protection operation at overload by current, protection of load from output voltage at its values higher than permissible, and increase in efficiency.

1 cl, 4 dwg

Description

The present invention relates to electronic means and can be used to transfer voltage from a power source to a load unit with protection against overcurrent, as well as to protect against overloading both the power source and the voltage switch itself. In addition, the device provides the ability to protect the load from unacceptably low or high voltage by completely removing it from the load.

The use of this device is possible if the capacitive component of the load, or part of it (the filter capacitor in the load) is not previously connected, at least with a low-potential output of the active component of the load.

Known compensation voltage stabilizer [Power sources of electronic equipment. Handbook edited by G.S. Naivelt. Moscow “Radio and Communications” 1986, p. 189, fig. 5.19] with overcurrent protection, comprising an electronic switch made on a transistor, a limiting resistor, and a second transistor controlling the electronic switch.

The disadvantage of this device is the inability to completely disconnect the load from the voltage source during unauthorized lowering of the input voltage, which can lead to unacceptable modes of operation of the load unit. For example, if the load block is an electronic device, then the elements of this device will be under reduced unacceptable voltage.

A number of devices are known - voltage switches [description of the invention to the patent of the Russian Federation No. 2210183 H03K 17/08, description of the invention to the patent of the Russian Federation No. 2240647 H03K 17/08, description of the invention to the patent of the Russian Federation No. 2208292 H03K 17/08, description of the invention to the patent of the Russian Federation No. 23355843 H03K 17/08], built on the basis of series-connected electronic key and shunt; to increase the voltage drop by several times, using the comparators and logic elements, the electronic key is controlled (turned off).

The disadvantage of such devices is insensitivity to random significant short-term drops in the input voltage, at which the voltage at the load is not removed, but reaches unacceptably low values.

As a prototype of the claimed device for construction and functional purpose, you can point to the "Overcurrent protection device" [description of the invention to the patent of the Russian Federation No. 2542950 H03K 17/08].

The prototype device contains a serially connected bus of a positive potential of the input voltage, a resistive current sensor, an electronic key with a control circuit for turning it on / off, connected to the output of the electronic key through an aperiodic link, a bus of a positive potential of the output voltage, as well as a bus of negative input and output voltage. The buses of the positive and negative potentials of the input voltage are the input of the device, the buses of the positive and negative potentials of the output voltage are the output of the devices.

The disadvantages of the known device is the long response time of the overcurrent protection, which leads to significant pulsed energy releases on the electronic key, the lack of protection of the load from a pulsed increase in the input voltage, as well as the complexity of constructing the device. In addition, the inclusion of a resistive current sensor in the circuit of the switched current, leads to the allocation of additional power on it.

The technical result of the invention is the expansion of functionality by reducing the response time of the protection during overcurrent, protecting the load from the output voltage when its values are higher than acceptable, simplifying the device and increasing its efficiency.

The technical result is achieved by the fact that in an overcurrent protection device comprising a resistive current sensor, a capacitor of the time-supply circuit, busbars of negative and positive potential of the input and output voltages, control and switching p-MOS transistors, the output of the last of which is connected to the first the output of the feedback resistor and the bus of the positive potential of the output voltage, while the bus of the negative potential of the input voltage is connected to the bus of the negative potential of the output voltage a resistive current sensor is connected between the bus of the negative potential of the output voltage and the additionally introduced bus connecting the low-potential output of the capacitive component of the load, to which the second output of the feedback resistor and the gate of the control p-MOS transistor connected through the second resistor are connected to their the drain and gate of the switching p-MOS transistor connected through a third resistor to the bus of the negative potential of the output voltage, while the source of control The current r-MOS transistor is connected through the fourth resistor to the bus of the positive potential of the input voltage, the source of the switching r-MOS transistor and, through the capacitor of the timing circuit, with its gate.

The operation of the inventive device is illustrated in FIG. 1-4. In FIG. 1 shows an overcurrent protection device.

In FIG. Figures 2-4 show the results of modeling (oscillograms) of processes.

In FIG. 1 shows:

1 - bus positive potential input voltage (hereinafter, in the description - "bus 1"),

2 - bus negative potential input voltage (hereinafter, in the description - "bus 2"),

3 - switching p-MOS transistor (hereinafter referred to as transistor 3),

4 - control r-MOS transistor, (hereinafter referred to as transistor 4),

5 - feedback resistor,

6 ... 9 - first - fourth resistors, respectively,

10 - resistive current sensor,

11 - capacitor timing circuit (hereinafter, the capacitor 11),

12 - bus positive potential of the output voltage (hereinafter, in the description - "bus 12"),

13 - bus negative potential of the output voltage (hereinafter, in the description -),

14 - load with capacitive (capacitor 15) and active (16) components,

17 - input voltage source with a voltage switch (18),

19 - bus connection low potential output capacitive component of the load (hereinafter, in the text "bus 19").

In FIG. 2 shows the results of modeling (oscillograms) of processes that explain the general principle of the device.

In FIG. Figure 3 shows the results of modeling (oscillograms) of processes that explain the principle of operation of the device with the settings for protection against impulse drops ("dips") of the input voltage.

In FIG. Figure 4 shows the results of modeling (oscillograms) of processes that explain the principle of operation of the device with settings for protection against pulse excesses of the input voltage.

In FIG. Figure 2-4 shows: + IN - an example of the form of voltage supplied to the input of the device, 1 additional - an example of a change in load (additional current flowing through the device), 1 _n - load current flowing through a bus 12, + OUT - voltage at the output of the device , E is the energy (mJ) dissipated by the transistor 3. E _prototype is the energy (mJ) dissipated by the switching transistor in the prototype device.

The graphs shown in FIG. 2-4 are the result of mathematical modeling of the claimed device, in which explanatory inscriptions are made.

The device shown in figure 1 is as follows.

The bus 1 is connected to the source of the transistor 3 and the first terminals of the capacitor 11 of the timing circuit and the resistor 9. The drain of the transistor 3 is connected to the bus 12, and through the feedback resistor 5, with the gate of the transistor 4. The source of the transistor 4 is connected to the second output of the resistor 9. The drain transistor 4 is connected to the gate of transistor 3, through a resistor 7, with its gate and, through resistor 10, with buses 2 and 13. Bus 19 is connected through a resistive current sensor 10 with buses 2 and 13 and, through resistor 6, with the gate of transistor 4. The load 14 is connected to the buses 12 and 13. The timing circuit consists of a capacitor 11, resistors 5-8 and a resistive current sensor 10. The time constant of the timing circuit is determined by the capacitance of the capacitor 11 and the equivalent resistance of resistors 5-8 and a resistive current sensor 10.

If in the load 14 the capacitive component is not connected with the active component 16, at least with its low potential output, then the low potential output of the capacitor 15 of the capacitive component of the load is connected to the bus 19.

The operation of the overcurrent protection device is based on:

"smooth" inclusion of the transistor 3 to limit the current through it when turned on,

accelerated shutdown of the transistor 3 with a sharp increase in current through it, for example, with a short circuit in the load,

the absence of current interruption through the overcurrent protection device with acceptable “surges” of the input voltage (established during the initial adjustment of the device),

interruption of current through the overcurrent protection device with unacceptable “surges” of the input voltage (established during the initial adjustment of the device).

The overcurrent protection device operates as follows.

At some point t ₁ (Fig. 2, a) at the input of the device (bus 1), at the source of the transistor 3, the first output of the capacitor 11 and the resistor 9. an input voltage + IN appears (ends at time t ₂ ). At this moment, the voltage across the capacitor 11 is zero, as a result of which the transistor 4 is closed. The transistor 3 is either open at the level of passage of "small" currents, or is closed when the voltage at its gate is close to the opening of the transistor 3. This is achieved by choosing the ratio of the nominal values of R ₈ and R _{7 of} resistors 8 and 7. The ratio (R ₈ / R ₇ ) should be in the range from 5 to 10 in order to provide at the first moment (t ₁ ) the voltage between the gate and the source of transistor 3 close to its opening level (depending on type of transistor, this voltage can be from 2 to 4 V).

As the capacitor 11 charges, the gate voltage (relative to its source) of the transistor 3 increases, which entails its opening (if it was initially closed), an increase in the current through it and the charge of the capacitor 15. The voltage acting on the gate of the transistor 4 is formed from several components: an increase in the voltage across the capacitor 11 contributes to the opening of the transistor 4, the voltage that appears on the resistive current sensor (from the passage of current through the filter capacitor 15) and flows through the resistor 6 to the gate of the trans Zistor 4, contributes to its closure; + OUT output voltage supplied to the transistor gate through feedback resistor 5 also helps to close it.

The opening of the transistor 4 helps to limit the voltage between the gate and the source of the transistor 3 and, therefore, to limit the current through it. The closure of the transistor 4 provides a complete opening of the transistor 3.

If at time t ₃ (Fig. 2, b) there is an additional load I _DOP causing a significant excess of the output current (for example, there is a short circuit in the load), then by reducing the output voltage + OUT (due to an increase in the voltage drop across the transistor 3), due to the discharge current of the capacitor 15, a negative (relative to bus 13) voltage pulse appears on the resistive current sensor 10, which (through the resistor 6) hits the gate of the transistor 4. Transistor 4 opens, closing the transistor 3, as a result of which the output voltage was + OUT continues to decrease. Further, the voltage at the gate of the transistor 4, connected through the feedback resistor 5 to the bus 12, tends to the potential of the bus 13 through the load 14, which leads to the closure of the transistor 3 and the termination of the current through it. A 1 _n current termination process is shown in FIG. 2, c and 2, g; in FIG. 2, g shows the change in voltage at the load when the transistor 3 is turned off.

The achieved effect when using the invention is illustrated by the following.

By choosing the values of the resistive sensor, current 10 (in the range from 1 to 8 Ohms), resistor 6 (in the range from 39 to 82 kOhm), resistor 7 (in the range from 3 to 7.5 kOhm), you can configure the claimed device to: disconnect the load at voltage below a predetermined (Fig. 3) and to disconnect the load at a voltage above a predetermined (Fig. 4).

The setting for the option of disconnecting the load at a voltage lower than the specified one is based on the effect of lowering the load resistance, which was described above, in terms of the description of operation. The basis for tuning to the option of disconnecting the load at a voltage higher than the specified one is the increase in the voltage drop across the transistor 3 with an increase in the input voltage and, consequently, to a decrease in the output voltage. Further, the process of turning off the transistor occurs in the same way as described above in the part of the description of operation.

The simplification of the device is achieved by the fact that with the same switched currents as a transistor 4, you can use the transistor in small design due to the fact that the energy dissipated on it when turned off (current cutoff) is 20-50 times less than the energy dissipated on the transistor in the prototype . In FIG. 2, e shows the value of E close to 0.02 J - in the inventive device. In FIG. 2, f shows the value of E close to 0.8 J - in the device prototype.

In practice, this leads to the fact that for the claimed device, transistors in the SMD-0.2 or SMD-0.5 package can be used with an allowable dissipation energy E <(0.05-0.08) J. For the prototype device, transistors in the SMD-2 package or in case with large dimensions with a permissible dissipation energy E> 1.0 J.

The increase in efficiency is due to the fact that the resistive current sensor 10 is installed in the capacitive load circuit - the current flows through it during the time T of transients, T <2 ms.

In the prototype device, a current sensor (shunt) is installed in the load current path. The allocated power on it, for example, with its resistance of 0.5 Ohms and a current of the order of 1.5 A, is more than 1 W.

The proposed set of features in the solutions considered by the author was not found to solve the problem, and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step".

Claims (1)

An overcurrent protection device comprising a resistive current sensor, a time-series capacitor, negative and positive potential input and output voltage buses, control and switching p-MOS transistors, the output of the last of which is connected to the first output of the feedback resistor and the bus of the positive output potential voltage, wherein the bus of the negative potential of the input voltage is connected to the bus of the negative potential of the output voltage, characterized in that the resistive An IR current is connected between the bus of the negative potential of the output voltage and the additionally introduced bus for connecting the low-potential output of the capacitive component of the load, to which the second output of the feedback resistor and the gate of the control p-MOS transistor connected through the second resistor are connected through its second resistor to its drain and the switching gate p-MOS transistor connected through a third resistor to the bus of the negative potential of the output voltage, while the source of the control p-MOS transistor connected through the fourth resistor to the bus of the positive potential of the input voltage, the source of the switching p-MOS transistor and through the capacitor of the timing circuit with its gate.

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