RU2699254C1 - Reconfigurable computer system with a multilevel monitoring and control subsystem - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to computer engineering. Computer system comprises: a network Ethernet management switch, a master server, an Ethernet monitoring switch, a PCI-Express switch, a power control and control unit and a group of K computing nodes, each having a general purpose computer, a PCI-Express switch, a PCI-Express switch for computation modules, a monitoring and control unit, a cooling fan monitoring and control unit, a computing module power supply control and monitoring unit; a group of N computer modules, each having a PCI-Express switch, a group of M computing PLDs; a system PLD, a unit for controlling the mode of the PCI-Express switch and memory of the start configurations of the system PLD.EFFECT: high failure-tolerance of the computer system.1 cl, 1 dwg

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology, in particular, reconfigurable cluster-type computing systems designed to solve computationally complex, time-consuming tasks and high-speed processing of large information arrays.

BACKGROUND OF THE INVENTION

Known patent US 9037833, G06F 15/80, G06F 9/50, publ. 05/19/2015, (EP 1814029, US 20050235092), in which a computing system contains many integrated computing nodes. Each computing node consists of a general-purpose calculator, which includes general-purpose processors for performing high-performance computing, random access memory, and a switch for connecting computing nodes of a computing system with each other. General-purpose processors are interconnected in pairs via the Hyper Transport interface. Each of the general-purpose processors in the general-purpose calculator is connected through the HYPERTRANSPORT ™ / PCI bridge to the Host Channel Adapter, which, in turn, is connected to the switch. Computing nodes of a high-performance system are interconnected into a single network. To control the operation of a computing system in a cluster, one node is the controlling one; its tasks include monitoring the state of the system (detecting faulty nodes), scheduling tasks between cluster nodes, and managing user access rights. An Ethernet communications network can be used between the control node and the system computing nodes.

The disadvantage of this computing system is the low efficiency of the subsystem for monitoring and controlling the state of components.

The reason that impedes the achievement of the technical result is the high load of the control unit, with a large number of objects for monitoring and control inside the cluster of the computing system. This is due to the need for the control node to process a large flow of monitoring data on the state of controlled objects in the computing nodes and the consistent algorithm of the monitoring system.

The closest device of the same purpose to the claimed invention, in terms of features adopted for the prototype, is a reconfigurable computer system (RU No. 156778 U1, IPC G06F 15/16, announced April 10, 2015, published November 20, 2015 Bull. No. 32), comprising a control Ethernet network switch 1, a master server 2, monitoring Ethernet network switch 5, a group of K slave computing nodes 4 ₁ , ..., 4 _K , each of which contains a computer 8, a PCI-Express 11 switch, and a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which with holds a PCI-Express 19 switch, a group of M computing FPGAs 20 ₁ , ..., 20M, an interface FPGA 22, a PCI-Express 19 switch mode control unit 30, and a memory 24 FPGA configurations, with the leading server 2 connected to an Ethernet 6 network interface with a network switch Ethernet 5 monitoring and a network interface Ethernet 3 with a network switch Ethernet 1 control, which is connected via the corresponding network interfaces Ethernet 7 ₁ , ..., 7 _K with computers 8 computing nodes 4 ₁ , ..., 4 _K , in which the switch PCI-Express 11, connected by appropriate high speed serial GOVERNMENTAL interfaces PCI-Express 16 _1, ..., 16 _N with switches PCI-Express 19 in the respective reconfigurable computing devices 13 _1, ..., 13 _N, in which interface the FPGA 22 is connected to memory 24 FPGA configurations, and PCI-Express 19 switch is connected with a PCI-Express 19 switch mode control unit 30, with an interface FPGA 22 via a high-speed serial PCI-Express 17 interface and with computing FPGAs 20 ₁ , ..., 20 _M via the corresponding high-speed serial interfaces 21 ₁ , ..., 21 _M.

The disadvantage of this reconfigurable computing system is its low fault tolerance and high energy costs when solving computationally complex and time-consuming tasks.

The reason that impedes the achievement of the technical result is the long polling time during monitoring and component management, associated with the sequential polling by the leading server 2 via the network interface 6 through the Ethernet 5 monitoring switch of monitoring data from each of the computing nodes 4 ₁ , ..., 4 _K.

OBJECT OF THE INVENTION

The problem to which the invention is directed, is to create a reconfigurable computing system with an effective monitoring and control system.

The technical result of the invention is to increase fault tolerance and reduce the power consumption of a reconfigurable computing system.

SUMMARY OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that in a reconfigurable computer system with a multi-level monitoring and control subsystem containing a network switch Ethernet 1 control, a lead server 2, a network switch Ethernet 24 monitoring, a group of K computing nodes 4 ₁ , ..., 4 _K , each of which contains a general-purpose calculator 6, a PCI-Express switch 7 and a group of N computing modules 8 ₁ , ..., 8 _N , each of which contains a PCI-Express 10 switch, a group of M computing FPGAs 13 ₁ , ..., 13 _M , the system FPGA 18, the block 15 control mode switch PCI-Express 10 and the memory 17 of the starting configurations of the system FPGA 18,

moreover, the master server 2 is connected by an Ethernet 57 network interface with a monitoring Ethernet network switch 24 and an Ethernet 25 network interface with a control Ethernet network switch 1, which is connected via corresponding Ethernet 26 ₁ , ..., 26 _K network interfaces with general purpose computers 6 computing nodes 4 ₁ , ..., 4 _K ,

in which the PCI-Express 7 switch is connected by the corresponding high-speed serial PCI-Express 31, ..., 31 _N interfaces to the PCI-Express 10 switches in the corresponding computing modules 8 ₁ , ..., 8 _N ,

in which the system FPGA 18 is connected to the memory 17 of the starting configuration of the system FPGA 18 with the bus 45 for configuring the system FPGA 18, and the PCI-Express 10 switch is connected to the PCI-Express 10 switch mode control unit 15 via the PCI-Express 10 switch bus 36 FPGA 18 for high-speed serial interface PCI-Express 48 and with computing FPGAs 13 ₁ , ..., 13 m for the corresponding high-speed serial interfaces PCI-Express 33 ₁ , ..., 33 _M ,

additionally introduced a PCI-Express 3 switch and a unit 23 for monitoring and power management of computing nodes 4 ₁ , ..., 4 _K ,

each of which additionally includes a PCI-Express switch 9 computing modules, a monitoring and control unit 21, a cooling fan monitoring and control unit 22, a computing module power monitoring and control unit 20 and a group of N memories 5 ₁ , ..., 5 _N computing states modules 8 ₁ , ..., 8 _N ,

each of which additionally contains a group of M memories 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M , a group of M calculators 14 ₁ , ..., 14 _M with individual power supply, a group of M blocks 12 ₁ , ..., 12 _M control mode co-calculators 14 ₁ , ..., 14 _M , block 16 monitoring and control and block 19 configuration of computing FPGAs 13 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _M start configurations,

moreover, the master server 2 is also connected by a high-speed serial interface PCI-Express 27 with a switch PCI-Express 3 computing nodes, which is connected with the switches PCI-Express 9 computing modules of computing nodes 4 ₁ , ..., 4 _K , through the corresponding high-speed serial interfaces PCI-Express 28 ₁ , ..., 28 _K , and the monitoring Ethernet network switch 24 is connected to the power nodes of the computing nodes by the network interface 56 with the power monitoring and control unit 23 and the corresponding Ethernet interfaces 55 ₁ , ..., 55 _K monitoring hectares with blocks 21 for monitoring and control of computing nodes 4 ₁ , ..., 4 _K ,

in each of which the memory 5 ₁ , ..., 5 _N states of the computing modules 8 ₁ , ..., 8 _{N are} connected to a general-purpose calculator 6 via a common interaction bus 29, which is connected by a high-speed serial PCI-Express 30 interface to the PCI-Express 7 switch, the PCI-Express switch 9 of the computing modules is also connected to the PCI-Express 10 switches in the corresponding computing modules 8 ₁ , ..., 8 _N via the corresponding high-speed serial PCI-Express 32 ₁ , ..., 32 _N interfaces _, and the monitoring and control unit 21 is connected to block 22 control and management cooling fans with a bus 54 for monitoring and controlling cooling fans, with a power monitoring and control unit 20 with a power monitoring and control bus 53 and corresponding monitoring and control buses 52 ₁ , ..., 52 _N with state monitoring and control units with monitoring and control units 16 in the corresponding computing modules 8 ₁ , ..., 8 _N ,

in each of which the system FPGA 18 is also connected to the block 19 for configuring computing FPGAs 13 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _{M of the} starting configurations by the write control bus 49, with the monitoring and control unit 16 of the local monitoring bus 47 and state management and with the memory 17 of the starting configuration bus 46 online recording,

in addition, the computing FPGAs 13 ₁ , ..., 13 _{M are} also connected by the mode control buses 38 ₁ , ..., 38 _M with the corresponding blocks 12 ₁ , ..., 12 _M of the mode control of the calculators 14 ₁ , ..., 14 _M , individual buses 34 ₁ , ... , 34 _M records and individual buses 35 ₁ , ..., 35 _M operational reconfiguration with corresponding memories 11 ₁ , ..., 11 _M start configurations, tires 37 ₁ , ..., 37 _M local control of individual power supply and tires 39 ₁ , ..., 39 _M interactions with the corresponding calculators 14 ₁ , ..., 14 _M

in addition, the monitoring and control unit 16 in the computing modules 8 ₁ , ..., 8 _{N is} connected by the mode control bus 42 to the PCI-Express 10 switch mode control unit 15, the local individual power control buses 41 ₁ , ..., 41 _M with the corresponding FPGA computing 13 ₁ , ..., 13 _M , and is also connected by the primary recording bus 43 with the memory 17 of the starting configuration of the system FPGA 18 and the primary recording control bus 44 with the computing FPGA configuration block 19 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _M start configurations,

moreover, the configuration unit 19 in the computing modules 8 ₁ , ..., 8 _{N is} also connected by a common configuration bus 50 with computing FPGAs 13 ₁ , ..., 13 _M and a common recording bus 51 with memories 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M , and blocks 12 ₁ , ..., 12 _M control mode co-calculators are connected by buses 40 ₁ , ..., 40 _M mode with the corresponding co-calculators 14 ₁ , ..., 14 _M.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 is a functional diagram of a reconfigurable computing system with a multi-level monitoring and control subsystem.

In FIG. 1 and in the text the following abbreviations and designations are adopted:

RVS - reconfigurable computing system;

VU - computing node;

VM - computing module;

SV - co-calculator;

OS - operating system;

K is the number of computing nodes in a reconfigurable computing system;

N is the number of computing modules in the computing node;

M - the number of computing FPGAs and calculators in the computing module;

1 - network switch Ethernet control reconfigurable computing system;

2 - master server;

3 - switch PCI-Express computing nodes;

4 ₁ , ..., 4 _K - a group of K computing nodes;

5 ₁ , ..., 5 _N - a group of N memories of the state of computing modules;

6 - general-purpose calculator computing node;

7 - switch PCI-Express computing node;

8 ₁ , ..., 8 _N - a group of N computing modules;

9 - switch PCI-Express computing modules of the computing node;

10 - switch PCI-Express computing module;

11 ₁ , ..., 11 _M - a group of M memories of starting configurations of computing FPGAs 13 ₁ , ..., 13 _M computing module;

12 ₁ , ..., 12 _M - a group of M counting mode control units 14 ₁ , ..., 14 _M computing module;

13 ₁ , ..., 13 _M - a group of M computing FPGAs of a computing module with individual power supply;

14 ₁ , ..., 14 _M - a group of M calculators of a computing module with individual power supply;

15 - control unit mode switch PCI-Express 10 computing module;

16 - block monitoring and control of the computing module;

17 - memory starting configuration of the system FPGA 18 computing module;

18 - system FPGA computing module;

19 - configuration block computing FPGAs 13 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _M start configurations of the computing module;

20 - block control and power management of computing modules;

21 - block monitoring and control of the computing node;

22 is a control unit for controlling cooling fans of a computing unit;

23 - control unit and power management of computing nodes;

24 - network switch Ethernet monitoring reconfigurable computing system;

25 is an Ethernet network interface between an Ethernet control switch 1 and a master server 2;

26 ₁ , ..., 26 _K - K network interfaces between the Ethernet control switch 1 and the computing nodes 4 ₁ , ..., 4 _K ;

27 is a high-speed serial PCI-Express interface between the PCI-Express 3 switch and the master server 2;

28 ₁ , ..., 28 _K - K high-speed serial PCI-Express interfaces between the PCI-Express 3 switch and the PCI-Express 9 switches;

29 - a common interaction bus of a general-purpose calculator 6 and a group of N state memories of computing modules 8 ₁ , ..., 8 _N ;

30 — high-speed serial PCI-Express interface between a PCI-Express 7 switch and a general purpose computer 6;

31 ₁ , ..., 31 _N - N high-speed serial PCI-Express interfaces between the PCI-Express 7 switch and the PCI-Express switches 10 computing modules 8 ₁ , ..., 8 _N ;

32 ₁ , ..., 32 _N - N high-speed serial PCI-Express interfaces between the PCI-Express 9 switch and the PCI-Express switches 10 computing modules 8 ₁ , ... 8 _N ;

33 ₁ , ..., 33 _M - M high-speed serial interfaces PCI-Express computing FPGA 13 ₁ , ..., 13 _M ;

34 ₁ , ..., 34 _M - M individual memory recording buses 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ... 13 _M ;

35 ₁ , ..., 35 _M - M individual buses for operational reconfiguration of computing FPGAs 13 ₁ , ..., 13 _M ;

36 - bus mode switch PCI-Express 10;

37 ₁ , ..., 37 _M - M buses of local control for individual power supply of calculators 14 ₁ , ..., 14 _M ;

38 ₁ , ..., 38 _M - M bus control mode co-calculators 14 ₁ , ..., 14 _M ;

39 ₁ , ..., 39 _M - M buses of interaction between computing FPGAs 13 ₁ , ..., 13 _M and corresponding calculators 14 ₁ , ..., 14 _M ;

40 ₁ , ..., 40 _M - M bus mode counters 14 ₁ , ..., 14 _M ;

41 ₁ , ..., 41 _M - M buses of local control of individual power supply of computing FPGAs 13 ₁ , ..., 13 _M ;

42 - PCI-Express 10 switch mode control bus;

43 - bus primary recording memory 17 of the starting configuration of the system FPGA 18 block 16 monitoring and control of the computing module;

44 - control bus for primary recording of memories 11 ₁ , ..., 11 _M start configurations of computing FPGAs 13 ₁ , ..., 13 _{M by} block 16 for monitoring and control of the computing module;

45 - bus configuration system FPGA 18 from the memory 17 of the starting configuration;

46 - bus write memory 17 starting configuration of the system FPGA 18;

47 - bus local monitoring and control of the state of the computing module of the system FPGA 18;

48 - high-speed serial interface PCI-Express system FPGA 18;

49 - a bus for managing the storage of memories 11 ₁ , ..., 11 _M starting configurations and configuration of computing 13 ₁ , ..., 13 _M system FPGAs 18;

50 - a common bus for configuring computing FPGAs 13 ₁ , ..., 13 _M ;

51 - a common bus for recording memories of starting configurations 11 ₁ , ..., 11 _M computing FPGAs 13 ₁ , ..., 13 _M ;

52 ₁ , ..., 52 _N - N buses for monitoring and controlling the state of computing modules 8 ₁ , ..., 8 _N ;

53 - bus control and power management of computing modules 8 ₁ , ..., 8 _N ;

54 - bus for monitoring and controlling cooling fans of computing nodes 4 ₁ , ..., 4 _K ;

55 ₁ , ..., 55 _K - K network interfaces for monitoring Ethernet computing nodes 4 ₁ , ..., 4 _K ;

56 - network interface Ethernet power management computing nodes 4 ₁ , ..., 4 _K ; 57 is an Ethernet network interface between an Ethernet 24 monitoring switch and a master server 2.

DETAILED DESCRIPTION OF THE INVENTION

The leading server 2 of the reconfigurable computing system is designed to organize the loading of operating systems in general-purpose computers 6 WU 4 ₁ , ..., 4 _K , organization of task flow management for WU 4 ₁ , ..., 4 _K through the network switch Ethernet 1 control RVS, organization monitoring status component and control modes of the reconfigurable computing system through the network switch Ethernet 24 monitoring PBC, as well as to organize the interaction of computing nodes 4 ₁ . ..., 4 _{K to} each other through a PCI-Express 3 switch via high-speed serial PCI-Express 28 ₁ , ..., 28 _K and computing modules 8 ₁ , ..., 8 _{N to} each other through a PCI-Express 9 switch to high-speed serial PCI-interfaces Express 32 ₁ , ..., 32 _N during the construction of various computing structures of the PBC. In addition, the leading server 2, using the resources of the PCI-Express 3 and 9 switches, as well as the PCI-Express 10 and 7 switches, provides direct access to the state memories 5 ₁ , ..., 5 _N of the computing modules. Also, due to interaction with the control unit 23 for controlling and supplying power to the control unit via the Ethernet switch 24 for monitoring the PBC, the host server 2 controls the supply of primary power to the corresponding control units 4 ₁ , ..., 4 _K , and through the network switch Ethernet 1 for controlling the PBC control the switching on of computers general purpose 6.

Computing nodes 4 ₁ , ..., 4 _K are designed for high-speed data processing in the process of solving labor-intensive computing problems.

Each general-purpose calculator 6 VU 4 ₁ , ..., 4 _K contains a general-purpose processor, RAM, PCI-Express I / O bus, network interfaces and is designed to prepare data and process the results of calculations from VM 8 ₁ , ..., 8 _N , as well as for analysis and transmission of the state of the component from memories 5 ₁ , ..., 5 _{N of the} state of the VM 8 ₁ , ..., 8 _N using the Ethernet switch 1 via the network interfaces 26 ₁ , ..., 26 _K to the master server 2 of the PBC. Data exchange between the general-purpose calculator 6 and VM 8 ₁ , ..., 8 _{N is} carried out using the PCI-Express 7 switch via the high-speed serial PCI-Express 30 interface.

Computing FPGAs 13 ₁ , ..., 13 _M with individual power supply, interact with a general-purpose computer 6 through PCI-Express 7 and 10 switches, and on buses 39 ₁ , ..., 39 _M with corresponding CB 14 ₁ , ..., 14 _M , are designed for exchanging data and results and performing preliminary data processing with subsequent processing of the results obtained from CB 14 ₁ , ..., 14 _M when solving computationally complex problems of various types. Computing FPGAs 13 ₁ , ..., 13 _M record the corresponding memories 11 ₁ , ..., 11 _M start configurations on individual buses 34 ₁ , ..., 34 _M records, and thus perform real-time self-configuration with the necessary working configurations on the corresponding individual buses 35 ₁ , ..., 35 _M RAM reconfiguration, using only its own resources without the use of FPGA resources system 18. In addition computational FPGA 13 _1, ..., 13 _M are individually controlled power and modes of operation corresponding to NE 14 _1, ..., 14 _M at on oschi respective tires 37 _1, ..., 37 _M individual local power management NE and tire 38 _1, ..., mode control 38 _M. The starting configurations of computing FPGAs 13 ₁ , ..., 13 _M are designed to ensure interaction via the high-speed serial PCI-Express interface and to overwrite the corresponding memories 11 ₁ , ..., 11 _{M of the} starting configurations with the required working configurations.

Co-calculators 14 ₁ , ..., 14 _M with individual power supply are designed to perform the bulk of data processing in the process of solving computationally complex problems. As SV 14 ₁ , ..., 14 _M FPGAs with a large number of configurable logic blocks, custom VLSI with hardware or software logic, as well as systems on a chip that can combine universal programmable gate arrays and processor cores can be used. Co-calculators 14 ₁ , ..., 14 _M , determine the performance of the RCS, have the highest specific computing power, operate at extremely high frequencies and, as a result, are characterized by high energy consumption and heat dissipation.

The VM monitoring and control unit 16 is designed to collect data on the state of computing FPGAs 13 ₁ , ..., 13 _M , calculators 14 ₁ , ..., 14 _M and system FPGAs 18, programming thresholds for temperature protection, controlling individual power supplies of computing FPGAs 13 ₁ , ... , 13 _M via buses 41 ₁ , ..., 41 _{M of} local management of individual power supply of computing FPGAs 13 ₁ , ..., 13 _M VMs, controlling the operating mode of the PCI-Express 10 switch by interacting with the PCI-Express 10 switch mode control unit 15 via bus 42 PC switch mode control I-Express 10. Also, the VM monitoring and control unit 16 performs primary recording of the memories 11 ₁ , ..., 11 _{M of the} starting configurations of computing FPGAs 13 ₁ , ..., 13 _M via the primary recording control bus 44 through block 19 and the memory 17 of the starting configuration of the system FPGA 18 on the bus 43 of the primary memory record 17. In addition, the VM monitoring and control unit 16 on the corresponding buses 52 ₁ , ..., 52 _N interacts with the VU monitoring and control unit 21, which provides access to the monitoring and control of computing modules 8 ₁ , ... , 8 _N from the server is managed 2. Initial recording of memories 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M and memory 17 of the starting configuration of system FPGAs 18 is carried out at the stage of manufacturing and commissioning of computing modules.

System FPGA 18 computing modules designed to analyze information about the state of computing FPGA 13_one, …, 13_M and calculators 14_one, …, fourteen_Mreceived from the VM monitoring and control unit 16 via the local monitoring and state management bus 47 of the VM, generating the current state frames of the VM components and transferring these frames via the high-speed PCI-Express 48 interface via PCI-Express 10 and 7 switches to the corresponding memory 5_one, …, 5_N VM state 8_one, …, 8_N. Using block 19 configuration computing FPGA 13_one, …, 13_M and their memories 11_one, …, eleven_M start configurations and bus 49 write control system FPGA 18 configures as computing FPGA 13_one, …, 13_M, and recording memory starting configurations 11_one, …, eleven_M. In addition, the system FPGA 18 via the online recording bus 46 from the memory 17 of the starting configuration records the system FPGA 18, and through interaction on the bus 47 with the VM monitoring and control unit 16, it sets the temperature protection thresholds for the VM components. The starting configuration of the system FPGA 18 is designed to provide all of the above functions, but can change during operation, which is reflected in its memory 17 of the starting configuration by overwriting.

The WU monitoring and control unit 21 is designed to monitor and control computing units 8 ₁ , ..., 8 _N , the WU power and the WU cooling fans, due to interaction with the VM monitoring and control units 16, the WU power control and management unit 20, and the control unit 22 and control VU cooling fans on the corresponding buses 52 ₁ , ..., 52 _N for monitoring and controlling the state of VM 8 ₁ , ..., 8 _N , bus 53 for monitoring and power management of VM 8 ₁ , ..., 8 _N and bus 54 for controlling and controlling cooling fans VU4 ₁ , ..., 4k and data transmission cher Without a network switch Ethernet 24 monitoring PBC on the leading server 2 PBC. In this case, due to interaction with the control unit 20 for controlling and controlling the power supply of the VU and the unit 22 for monitoring and controlling cooling fans of the VU, the monitoring and control unit 21 of the VU controls the power supply to the VM 8 ₁ , ..., 8 _N and controls the rotation speed of the cooling fans of the VU due to interaction with the monitoring and control units 16 of the VM, the monitoring and control unit of the control unit 21 sets the thresholds for the temperature protection of the component VM 8 ₁ , ..., 8 _N , and, if necessary, can carry out the initial recording of memory 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M and memory 17 of the starting configuration of system FPGAs 18 VM 8 ₁ , ..., 8 _N.

The proposed reconfigurable computer system operates as follows.

When the power is turned on, the PBC control Ethernet network switch 1, the PBC monitoring Ethernet switch 24 and the master server 2 are turned on first. After loading the master server 2, the power is switched on to the computing nodes 4 ₁ , ..., 4 _K already according to the program from the master server 2 through the block 23 control and power management WU. Next, the leading server 2 of the PBC through the block 21 monitoring and control VU carries out alternate power-up of the computing modules 8 ₁ , ..., 8 _N.

After loading the system FPGA 18 from the memory 17 of the starting configuration of the system FPGA 18, the individual power supplies of the computing FPGA 13 ₁ , ..., 13 _M are turned on. Computing FPGAs 13 ₁ , ..., 13 _{M are} configured by start configurations from the corresponding memories 11 ₁ , ..., 11 _M start configurations. Starting configurations of computing FPGAs 13 ₁ , ..., 13 _M are used to load working configurations in the memory 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M. At the same time, block 21, through the VU monitoring and control block 16, sets the thresholds for the temperature protection of the system FPGA 18, computing FPGAs 13 ₁ , ..., 13 _M and CB 14 ₁ , ..., 14 _M.

Next, the lead server 2 enables power on general purpose computers 6 WU and loading operating systems.

After loading the OS in general-purpose computers 6 WUs, which can be performed via Ethernet or from autonomous disks, the address space is distributed between computing FPGAs 13 ₁ , ..., 13 _M. At the same time, the VU monitoring unit 21 verifies the supply voltage of the system FPGA 18, computing FPGAs 13 ₁ , ..., 13 _M and CB 14 ₁ , ..., 14 _M through the VM monitoring and control unit 16.

General purpose computers 6 WUs distribute user tasks between computing FPGAs 13 ₁ , ..., 13 _M and configure them with work programs using resources only of computing FPGAs 13 ₁ , ..., 13 _M. After that, computing FPGAs 13 ₁ , ..., 13 _{M are} prepared for solving user problems. In this case, computing FPGAs 13 ₁ , ..., 13 _M control individual power supplies of the corresponding CB 14 ₁ , ..., 14 _M and dynamically control their operating modes. Depending on the used CB 14 ₁ , ..., 14 _M and the nature of the tasks processed on them and computing FPGAs 13 ₁ , ..., 13 _M , the control of operating modes of the CB 14 ₁ , ..., 14 _M includes the configuration of the CB, control of their operating frequencies and setting the required operating modes. Computing FPGAs 13 ₁ , ..., 13 _M also record new working configurations in the memory 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M , thereby organizing operational self-configuration using only their own resources.

Computing FPGAs 13 ₁ , ..., 13 _{M have the} possibility of operational self-configuration using their own memories 11 ₁ , ..., 11 _M start configurations and individual write buses 34 ₁ , ..., 34 _M and operational reconfiguration 35 ₁ , ..., 35 _M , as well as the presence of computing FPGAs 13 ₁ , ..., 13 _M and CB 14 ₁ , ..., 14 _M individual power supply and the possibility of individual power management, allows the distribution of computing resources to solve current user problems with an accuracy of up to one computing FPGA 13 ₁ , ... 13 _M with respectively Leica Geosystems CB 14 _1, ..., 14 _M, that allows to optimize the allocation of tasks to computing nodes and modules to improve the exchange of secondary PCI Express channels and equalizing power consumption and heat rate HMW component. In this regard, if in a user’s task stream all tasks have the same priority for execution, then, first of all, tasks that in combination lead to a decrease in total consumption and an increase in the average exchange rate via PCI Express channels can be selected for execution from the task stream, that is, the best combined with each other during implementation.

In the proposed RVS, a multilevel subsystem of monitoring and control of the RVS is organized, which monitors and controls four parallel operating levels.

The first level of the subsystem of monitoring and control of the RVS is responsible for the local management of individual power supplies of CB 14 ₁ , ..., 14 _M computing FPGAs 13 ₁ , ..., 13 _M , which involves disconnecting computing FPGAs 13 ₁ , ..., 13 _{M of} individual power supplies from the corresponding CB 14 ₁ , ..., 14 _M during periods of inactivity, that is, when the resources of CB 14 ₁ , ..., 14 _M are temporarily unclaimed. Such situations can arise in cases where the resources of CB 14 ₁ , ..., 14 _{M are} not involved in the processing of computational algorithms. The result of this control of individual power supplies CB 14 ₁ , ..., 14 _M is the reduction of their power consumption when solving computationally complex problems.

The second level of the subsystem of monitoring and control of the RVS is responsible for local monitoring and state management of individual VMs 8 ₁ , ..., 8 _N. At this level, system FPGA 18 collects data on the current state of VM components involved in the process of performing calculations, namely, computing FPGAs 13 ₁ , ..., 13 _M and the corresponding CB 14 ₁ , ..., 14 _M. According to the data obtained, the system FPGA 18 manages the individual power supplies of the computing FPGAs 13 ₁ , ..., 13 _M , as well as by interacting with the computing FPGAs 13 ₁ , ..., 13 _M through the VM monitoring and control unit 16, controls individual power supplies and dynamically sets the operating modes of the CB 14 ₁ , ..., 14 _M , which primarily refers to the control of the operating frequency depending on their current temperature. To control individual power supplies CB 14 ₁ , ..., 14 _M and dynamically configure their operating modes depending on their current temperature and power modes, the resources of the system FPGA 18 are mainly used, and the computing FPGA 13 ₁ , ..., 13 _M are used for relay control signals generated by the system FPGA 18. Due to this, high efficiency of state management of VM components at the stage of solving problems is ensured.

From the collected monitoring data, the system FPGA 18 forms the state frames of the computing modules 8 ₁ , ..., 8 _M. VM status frames are small data packets containing only minimal information about the state of components of a reconfigurable computing system, based on which the probability of failures in the operation of VM components 8 ₁ , ..., 8 _N is estimated. Using the PCI-Express 7 and 10 switches, VM status frames are translated into the corresponding VM status memory 5 ₁ , ..., 8 _N , from which, through a general purpose calculator, 6 VUs and Ethernet network switch 1, the PBC control is sent to the PBC master server 2. Since the on-line monitoring data is quite small, their flow practically does not burden the communication medium used for the processing of computing tasks. In the case when general-purpose computers 6 are busy with intensive transfer of data and results of user tasks, resources of the master server 2 and PCI-Express switches 7, 10, 9 and 3 can be used to transfer status frames from memories 5 ₁ , ..., 5 _N.

The third level of the subsystem of monitoring and state control of the RVS is responsible for monitoring and state management of the VU 4 ₁ , ..., 4 _K. At this level, the main monitoring and control functions are assigned to the monitoring units 21 of the WU component. These blocks collect and process extended data about the status of VU 4 ₁ , ..., 4 _K , namely computing FPGAs 13 ₁ , ..., 13 _M , CB 14 ₁ , ..., 14 _M , system FPGAs 18, PCI-Express 9 switches, power and cooling systems VU 4 ₁ , ..., 4 _K. Extended monitoring data provides detailed information about the state of the components of the VM 8 ₁ , ..., 8 _N. According to the status data of the VM 8 ₁ , ..., 8 _N component, the VU monitoring unit 21 controls the rotation speed of the VU 4 ₁ , ..., 4 _K cooling fans using the control unit 22, which reduces the power consumption of the VU 4 ₁ , ... , 4 _K , as well as power management of the VU 4 ₁ , ..., 4 _K using the unit 23 of the control and power supply of the VU. The power supply to the corresponding VM 8 ₁ , ..., 8 _{N is} carried out alternately, due to which emissions in the power circuits of the VM 8 ₁ , ..., 8 _{N are} reduced at the time of their inclusion. Thus, due to the effective operation of the cooling system, its energy consumption is reduced, and due to the possibility of alternating switching on and emergency shutdown of the VM 8 ₁ , ..., 8 _N power supplies, the probability of failure of their components is reduced. The processed information about the status of the VU 4 ₁ , ..., 4 _K from the VU monitoring units 21 through the Ethernet network switch 26 for monitoring the status of the PBC is transmitted to the main server 2 of the PBC.

The fourth level of the subsystem for monitoring and managing the status of the RVS is responsible for monitoring and managing the state of the entire RVS. At this level, the leading server 2 carries out a centralized collection of information on the status of all components of the RCS and, based on these data, the tasks are optimally redistributed between the control units, depending on their current power consumption and temperature conditions. By analyzing the monitoring information obtained using monitoring tools of the second level, the PBC master server 2 can adjust the request period for extended monitoring data from the monitoring units 21 of the control unit to quickly monitor the current state of the control unit having the highest energy consumption and temperature of their components. Thus, high operational efficiency of the monitoring and control subsystem of the DCS is ensured, which reduces the likelihood of overheating of the VU 4 ₁ , ..., 4 _K components and their emergency power off, and also increases the fault tolerance of the RCS as a whole. In addition, the master server 2 alternately turns on the power of the VU 4 ₁ , ..., 4 _K by interacting with the power monitoring and control unit 23, thereby reducing emissions in the power circuits of the VU 4 ₁ , ..., 4 _K at the time of their switching on.

The monitoring and control subsystems of the proposed reconfigurable computing system are intended for servicing only system and computing FPGAs and CBs, since the other components of the RCS have regular monitoring tools that provide a sufficient level of fault tolerance.

MODE FOR CARRYING OUT THE INVENTION

The proposed reconfigurable computing system can be implemented on the following elements:

A Kraftway server based on the Kraftway Express 200 platform can be used as the main server 2 of PBC: Intel (R) Xeon (R) E2620V4 2.10 GHz 8 cores; RAM 64 Gb; hard drive 1 Tb.

General purpose computers 6 WUs: Intel (R) Xeon (R) processor E2620V4 2.10 GHz 8 cores; RAM 64 Gb; hard drive 1 Tb; eight computing modules 8, each containing four computing FPGAs 13 ₁ , ..., 13 _M and four custom VLSIs as CB 14 ₁ , ..., 14 _M.

Computing modules 8: system FPGA 18 and computing FPGA 13 ₁ , ..., 13 _M - on Xilinx microcircuits of type XC7A100T-FGG484; PCI-Express 9 switch - on the chip of the PEX8732 switch from PLX Technology; unit 16 for monitoring the state of the VM components — on the Maxim Integrated, Maxim Integrated, TMP461AIRUNT chips of Texas Instruments; blocks 12 control mode CB 14 ₁ , ..., 14 _M - using chips SI570; block 21 configuration of computing FPGAs and their memory starting configurations - on the chip CPLD XC2C64A company Xilinx; memory starting configurations 11, 17 computing and system FPGAs - on chips SPI-memory M25P64 from Micron Technology.

Unit 21 monitoring and control WU - on a chip company Xilinx type XC7Z007S-1CLG400C.

In the proposed reconfigurable computer system, in comparison with the prototype, the use of a multi-level subsystem for monitoring and controlling the state of the PBC significantly reduces the time of polling the state of the components and transmitting data to the leading server 2. In the prototype, the time of polling and data transfer is Tprototype = M * N * T _1O + M * N * T _1D , where T _1O and T _1D are the times of polling the state (for example, temperature and voltage) and data transfer for one computing FPGA, M is the number of computing FPGAs in the module, N is the number of computing modules in the computing node, provided that computers 8 simultaneously and independently deliver their data to the leading server 2. In the proposed reconfigurable computing system, this time is T = 2 * M * T _1O + 2 * N * M * T _1D , where the coefficient " deuce "is associated with the introduction of 8 calculators into computing modules 14. This time in the present invention is significantly less than that of the prototype, due to the independent and parallel formation by the system FPGA of 18 frames of the state of computing modules 8 ₁ , ..., 8 _N in memories 5 ₁ , ... 5 _N states in Computational x nodes 4 _1, ..., 4 _K via the switches PCI-Express 7, 10, and independent parallel transmit data framing state, general purpose computer 6 and the formation of advanced monitoring and control block monitoring data 21 TA, respectively via Ethernet switches 1 and 24 and respective connection to the leading server 2. In this regard, the service interval of each specific component is also reduced, which increases the fault tolerance of the reconfigurable computing system as a whole.

In addition, in comparison with the prototype, the proposed reconfigurable computing system with a multi-level monitoring and control subsystem has lower power consumption due to the efficient control of the rotation of the cooling fans of the computing nodes 4 ₁ , ..., 4 _K , depending on the current temperatures, the components of the computing modules 8 ₁ , ..., 8 _N and operational disconnection of individual power from unused computing FPGAs 13 ₁ , ..., 13 _M and calculators 14 ₁ , ..., 14 _M.

The above information allows us to conclude that the proposed reconfigurable computer system with a multi-level monitoring and control subsystem solves the problem and meets the claimed technical result - increasing the fault tolerance of the reconfigurable computer system and reducing the power consumption.

Claims (13)

A reconfigurable computing system with a multi-level monitoring and control subsystem, containing a control Ethernet network switch 1, a host 2, a monitoring Ethernet network switch 24, a group of K computing nodes 4 ₁ , 4 _K , each of which contains a general purpose computer 6, a PCI switch Express 7 and a group of N computing modules 8 ₁ , ..., 8 _N , each of which contains a PCI-Express 10 switch, a group of M computing FPGAs 13 _1, ..., 13 _M , a system FPGA 18, a PCI switch mode control unit 15 Express 10 and memory 17 start to nfiguratsy system FPGA 18, moreover, the master server 2 is connected by an Ethernet 57 network interface with a monitoring Ethernet network switch 24 and an Ethernet 25 network interface with a control Ethernet network switch 1, which is connected via corresponding Ethernet 26 ₁ , ..., 26 _K network interfaces with general purpose computers 6 computing nodes 4 ₁ , ..., 4 _K , in which the PCI-Express 7 switch is connected by the corresponding high-speed serial PCI-Express 31, ..., 31 _N interfaces to the PCI-Express 10 switches in the corresponding computing modules 8 ₁ , ..., 8 _N , in which the system FPGA 18 is connected to the memory 17 of the starting configuration of the system FPGA 18 with the bus 45 for configuring the system FPGA 18, and the PCI-Express 10 switch is connected to the PCI-Express 10 switch mode control unit 15 via the PCI-Express 10 switch bus 36 FPGA 18 for high-speed serial interface PCI-Express 48 and with computing FPGAs 13 ₁ , ..., 13 _M for the corresponding high-speed serial interfaces PCI-Express 33 ₁ , ..., 33 _M , additionally introduced a PCI-Express 3 switch and a unit 23 for monitoring and power management of computing nodes 4 ₁ , ..., 4 _K , each of which additionally includes a PCI-Express switch 9 computing modules, a monitoring and control unit 21, a cooling fan monitoring and control unit 22, a computing module power monitoring and control unit 20 and a group of N memories 5 ₁ , ..., 5 _N computing states modules 8 ₁ , ..., 8 _N , each of which additionally includes a group of M memories 11 ₁ , ..., 11 _M starting configurations of computing FPGAs 13 ₁ , ..., 13 _M , a group of M calculators 14 ₁ , ..., 14 _M with individual power supply, a group of M blocks 12 ₁ , ..., 12 _M control mode co-calculators 14 ₁ , ..., 14 _M , block 16 monitoring and control and block 19 configuration of computing FPGAs 13 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _M start configurations, moreover, the master server 2 is also connected by a high-speed serial interface PCI-Express 27 with a switch PCI-Express 3 computing nodes, which is connected with the switches PCI-Express 9 computing modules of computing nodes 4 ₁ , ..., 4 _K through the corresponding high-speed serial interfaces PCI-Express 28 ₁ , ..., 28 _K , and the monitoring Ethernet network switch 24 is connected by the network interface 56 of the power management of the computing nodes with the power monitoring and control unit 23 and the corresponding network interfaces Ethernet 55 ₁ , ..., 55 _K monitoring and with blocks 21 monitoring and control of computing nodes 4 ₁ , ..., 4 _K , in each of which the memory 5 ₁ , ..., 5 _N states of the computing modules 8 ₁ , ..., 8 _{N are} connected to a general-purpose calculator 6 via a common interaction bus 29, which is connected by a high-speed serial PCI-Express 30 interface to the PCI-Express 7 switch, the PCI-Express switch 9 of the computing modules is also connected to the PCI-Express 10 switches in the corresponding computing modules 8 ₁ , ..., 8 _N via the corresponding high-speed serial PCI-Express 32 ₁ , ..., 32 _N interfaces, and the monitoring and control unit 21 is connected to control unit 22 cooling fans bus 54 for monitoring and control of cooling fans, to the block 20 control and power control - bus 53 control and power control and the respective buses 52 _1, ..., 52 _N monitor and control the status of a block 16 for monitoring and control in the respective computing modules August ₁ , ..., 8 _N , in each of which the system FPGA 18 is also connected to the block 19 for configuring computing FPGAs 13 ₁ , ..., 13 _M and their memory 11 ₁ , ..., 11 _M start configurations with a write control bus 49, with a monitoring and control unit 16 - a local monitoring bus 47 and state management and with the memory 17 of the starting configuration bus 46 online recording, in addition, the computing FPGAs 131, ..., 13 _{M are} also connected by buses 38 ₁ , ..., 38 _M of the mode control with the corresponding blocks 12 ₁ , ..., 12 _M of the mode control of the calculators 14 ₁ , ..., 14 _M , individual buses 34 ₁ , ..., 34 _M recordings and individual buses 35 ₁ , ..., 35 _M operational reconfiguration with the corresponding memories 11 ₁ , ..., 11 _M start configurations, tires 37 ₁ , ..., 37 _M local control of individual power supply and tires 39 ₁ , ..., 39 _M interaction with corresponding calculators 14 ₁ , ..., 14 _M in addition, the monitoring and control unit 16 in the computing modules 8 ₁ , ..., 8 _{N is} connected by the mode control bus 42 to the PCI-Express 10 switch mode control unit 15, the local individual power control buses 41 ₁ , ..., 41 _M with corresponding computing FPGAs 13 ₁ , ..., 13 _M , and is also connected by the primary recording bus 43 with the memory 17 of the starting configuration of the system FPGA 18 and the primary recording control bus 44 with the computing FPGA configuration block 19 ₁ , ..., 13 _M and their memories 11 ₁ , ..., 11 _M starting configurations, moreover, the configuration unit 19 in the computing modules 8 ₁ , ..., 8 _{N is} also connected by a common configuration bus 50 with computing FPGAs 13 ₁ , ..., 13 _M and a common bus 51 recording with memories 11 ₁ , ..., 11 _M start configurations of computing FPGAs 13 ₁ , ..., 13 _M , and blocks 12 ₁ , ..., 12 _M control mode co-calculators are connected by tires 40 ₁ , ..., 40 _M mode with the corresponding co-calculators 14 ₁ , ..., 14 _M

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