RU2686881C1 - Three-channel digital phase-shifting device - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to pulse technology, in particular to devices for specifying a phase shift of electrical signals, and can be used in digital control systems for semiconductor converters. Digital phase-shifting device (Fig. 1) includes rectangular pulses shaper 1, first 2 and second 3 short pulse generators, logical element NOT 4, first 5 and second 6 logic element AND, summing counter 7, subtracting counter 8, numerical comparator 9, memory unit 10, generator 11 pulses of stable frequency, setting register 12, first diode 13, third 14 and fourth 15 logical elements AND, second 16 and third 17 subtracting counters, second 18 and third 19 rectangular pulse formers, third 20 and fourth 21 shapers of short pulses, second 22 and third 23 diodes, second 24 and third 25 numerical comparators, memory register 26. Device provides control of semiconductor converters, which can be supplied from single-phase and three-phase mains at practically smooth change of preset control angle and its high stability under conditions of frequency instability of supply mains.

EFFECT: broader functional capabilities owing to increasing the number of control channels.

1 cl, 2 dwg

Description

The invention relates to a pulse technique, in particular, to devices for setting the phase shift of electrical signals and can be used in digital control systems for semiconductor converters.

Known analog phase shifting device (FSU) of various types / 1 / the most advanced of which are vertical FSU type.

Their disadvantages are the need for adjustment and errors caused by the drift and instability of elements.

Known digital FSU vertical type, containing a numerical comparator, a pulse generator, a counter and a node synchronization / 2 /.

Its disadvantage is the error in setting the control angles, in conditions of voltage frequency instability during power supply from sources of limited power.

The closest in technical essence to the invention is a digital phase shifting device containing a shaper of rectangular pulses, the first shaper of short pulses, the output of which is connected to the input of recording the initial number of the detracting counter, a logical element NOT, the output of which is connected to the input of the second shaper of short pulses and to the first input The second logic element And connected by the second input with the output of the stable frequency pulse generator and the second input of the first logic element And, the summing counter, the counting input of which is connected to the output of the second logic element I, the reset input to the output of the second shaper of short pulses, and the output bits to the corresponding bits of the input of the initial number of the reading counter and the address input of the first coordinate of the memory block, to the bits of the address input the second coordinates of which are connected to the corresponding bits of the output of the master register, and the bits of the output of the memory block are connected to the corresponding bits of the second input of the numerical comparator, the output is EQUALLY o is the output of the device and which bits of the first input is associated with the corresponding bits of the output of the subtracting counter, the subtracting input of which is connected to the output of the first logical element I, the first input of which is connected to the input of the logical element NOT, the input of the first shaper of short pulses and the output of the shaper of the rectangular pulse, input which through the diode is connected to the network / 3 /.

This device provides a satisfactory error, almost smooth change of the specified angle of control and its high stability in conditions of frequency instability of the supply network. However, its area of effective operation extends only to single-phase networks.

The purpose of the invention is to expand the functionality by increasing the number of control channels.

The purpose of the invention is achieved by the fact that a three-channel digital phase-shifting device containing the first shaper of rectangular pulses, the first shaper of short pulses, the output of which is connected to the input of the record of the initial number of the first subtractive counter, the logical element NOT, the output of which is connected to the input of the second shaper of short pulses and to the first input of the second logical element And connected by the second input with the output of a stable frequency pulse generator and the second input of the first logical element mA, summing counter, the counting input of which is connected to the output of the second logic element I, the fault input - to the output of the second shaper of short pulses, and output bits - to the corresponding bits of the input of the initial number of the first counting counter, the subtracting input of which is connected to the output of the first logic element And, the first input of which is connected with the input of the logical element NOT, the input of the first shaper of short pulses and the output of the first shaper of rectangular pulses, the input of which through the first diode connected to the first phase of the network, and the output bits of the first subtractive counter are connected to the corresponding bits of the first input of the first numerical comparator, the EQUAL output of which is the first output of the device and which is connected with the corresponding bits of the output of the memory block to the bits of the input of the second coordinate of which are connected the corresponding bits of the output of the master register, equipped with the third and fourth logical elements of And, the second and third subtractive counters, the second and third form Rectangular pulse drivers, third and fourth short pulse shapers, second and third diodes, second and third numerical comparators and a memory register connected by a recording input to the output of the first short pulse shaper, the input bits to the corresponding output bits of the summing counter, and the output bits to the corresponding bits of the input address of the first coordinate of the memory block and the inputs of the original number of the second and third subtractive counters, the bits of the outputs of which are connected to the corresponding The first bits of the second and third numerical comparators, respectively, the outputs of which are the outputs of the second and third channels of the device, respectively, and the bits of the second inputs of the numerical comparators are connected to the corresponding bits of the output of the memory unit, and the second phase of the power supply is connected to the second rectangular pulse shaper, the output of which is connected directly to the first input of the third logical element I, and through the third shaper of short pulses with a recording input of the initial number of the second subtractive counter, the subtracting input of which is connected to the output of the third logical element I, connected by a second input to the input of a stable pulse generator and the second input of the fourth logical element I, the output of which is connected to the subtracting input of the third subtractive counter, the recording input of the original the numbers of which are connected to the output of the fourth shaper of short pulses connected by an input with the first input of the fourth logical element AND and the output of the third STUDIO rectangular pulses whose input is connected via a third diode to the third phase mains.

The memory register provides storage of information about the half-period of the supply voltage for the three channels. The second diode, the rectangular pulse shaper, the subtracting counter, the numerical comparator, the third short pulse shaper, and the third logical element And their connections provide the formation of a signal at the output of the second channel. The third diode, the rectangular pulse shaper, the subtracting counter, the numerical comparator, the fourth short pulse shaper, and the fourth logical element And and their connections provide the formation of a signal at the output of the third channel.

FIG. 1 shows a diagram of a three-channel digital phase shifting device; FIG. 2 - signal plots on the elements of the device.

Digital phase-shifting device (Fig. 1) includes a rectangular pulse shaper 1, the first 2 and second 3 short pulse shapers, the logical element is NOT 4, the first 5 and the second 6 logic element is And, summing counter 7, subtracting counter 8, numerical comparator 9, block memory 10, the generator 11 pulses of a stable frequency, setting the register 12, the first diode 13, the third 14 and the fourth 15 logic gates And, the second 16 and the third 17 subtracting counters, the second 18 and the third 19 shapers of rectangular pulses, the third 20 and fourth 21 formate whether there are short pulses, the second 22 and third 23 diodes, the second 24 and third 25 numerical comparators, memory register 26. The control angle code is set at the output of the master register 12. The addresses of the two-dimensional memory block 10 recorded codes K ₁₀ ^{(i, j) of the} driving voltage corresponding to the frequency ƒ _c ^{(i) of the} supply voltage and the specified angle α ^{(j) of the} control

K ₁₀₀ ^{(i, j)} = K ₇ ⁽ⁱ⁾ / K ₁₂ ^(j) ,

where K ₇ ⁽ⁱ⁾ / is the i-th address on the first coordinate, which is formed at the output of counter 7 and is equal to the code of the frequency of the supply voltage K ₇ ⁽ⁱ⁾ = ƒ ₁₁ / (2f _C ⁽ⁱ⁾ );

ƒ ₁₁ - frequency generator 11 pulses of a stable frequency;

ƒ _С ⁽ⁱ⁾ is the i-th value of the frequency of the supply voltage, which varies in the range of ƒ _Mr. -Δƒ≤f _C ⁽ⁱ ≤ƒ _Mr. + Δƒ,

ƒ _nom - nominal frequency;

Δƒ - frequency deviation ;,

i is the address number in the first coordinate i = 1, 2, 3 ... n, while ƒ _C ⁽¹⁾ corresponds to ƒ _C = ƒ _Mr. + Δƒ, and ƒ _C ⁽ⁿ⁾ corresponds to ƒ _C = ƒ _Mr. -Δƒ;

K ₁₂ ^(j) is the jth address on the second coordinate K ₁₂ ^(j) = π / α ^(j) = 180 ° / α ^(j) , which is specified by register 12;

j is the address number in the second coordinate j = 1, 2, 3 ... m, with K ₁₂ ⁽¹⁾ corresponding to α ⁽¹⁾ = 180 ° / m, and K ₁₂ ^(m) corresponding to α ^(m) = 180 °.

The device works as follows. At time t ₀ (Fig. 2) a negative half-wave of the supply voltage T of the first phase appears. The signal X1 at the output of the driver 1 disappears, and at the output of the logic element NOT 4, the signal X4 appears. On the front of the pulse X4, the driver 3 short pulses produces a pulse X3, which resets the counter 7. Simultaneously the pulse X4 from the output of the element HE 4, the duration of which is half the period T _{C of the} supply voltage u ₁ , is prepared at the first input element AND 6. From the output of the pulse generator 11 through the element And 6 to the counting input of the counter 7 begin to receive pulses X6. At its output, the code X7 of the half period T _C / 2 of the supply voltage begins to form. Its formation is completed at time t ₁ (Fig. 2), when the positive half-wave of the supply voltage u ₁ passes through the diode 13 to the input of shaper ₁ . At the same time, the X4 signal at the output of the HE 4 element disappears, preventing further X11 pulses from entering the counter 7, and a signal X1 appears at the output of the former 1. On the front of the X1 signal, the former 2 generates an X2 pulse, which writes the X7 code to the counter 8 and memory register a half-cycle of the supply voltage from the output of the meter 7. At the same time, the signal X1 from the output of the driver 1 prepares the element 5 for the first input. Through the element And 5 with the output of the generator 11 to the subtracting input of the counter 8 are pulses X5. Code X8 at the output of the counter 8 begins to decrease. This code X8 arrives at the first input of the numerical comparator 9. The second input of the numerical comparator 9 is supplied with the control voltage code X10 from the output of the memory block 10, which is selected from the cells of the memory block 10 depending on the half-period code X26 formed at the output of the counter 7, and the code X12 angle of the control set at the output of the register 12. Codes X8 and X10, entering the inputs of the comparator 9 are compared.

At time t ₂ (Fig. 2), when the codes on the input of the comparator 9 become equal, at its output appears the control signal α ₁ , which from the output of the first channel enters the output driver of the control system, which opens the corresponding valve of the valve set (in the diagram not shown).

When a positive half-wave voltage of the second phase u ₂ (time t ₃ in Fig. 2), which passes through the diode 22, the driver 18 produces a rectangular pulse X18, preparing the logical element And 14 on the first input. At the same time, on the front of the X18 signal, the driver 20 generates a short pulse X20, which into the subtractive counter 16 enters the power supply half-period code 26 from the register 26 output. The pulses X11 from the generator 11 output through the element 14 arrive at the subtracting input of the counter 16 and the code X16 at its output decreases. This code X16 is fed to the first input of the comparator 24, where it is compared with the code X10 coming from the output of the memory block 10. At time t ₄ (Fig. 2), when the codes at the inputs of the comparator 24 become equal, the control signal α appears at its output ₂ This signal α ₂ from the output of the second channel is fed to the converter control system (not shown in the diagram).

At time 15 (Fig. 2) the positive half-wave voltage of the third phase u ₃ , through the diode 23 is fed to the input of the driver 19. On the signal front from the output of the driver 19, the driver 21 generates a pulse recording in the counter 17 a half-cycle code of the supply voltage from the register output 26 At the same time, the subtractive input of counter 17, through element I 15, begins to receive pulses from the output of generator 11. The decreasing code X17 comes from the output of counter 17 to the first input of comparator 25, which is compared with the code X10 from the output of memory block 10. At the moment from codes fall X17 and X10 (time t ₆ in FIG. 2), appears on the output of the comparator ₃ outputs a signal α of the third channel, which enters into the control system.

Further, the process of the appearance of signals α ₁ , α ₂ and α ₃ at the outputs of the channels is periodically repeated as previously described. In addition, each time during the negative half-period of the supply voltage u _{1 of the} first phase, the half-cycle duration is measured, the code X7 of which is recorded in the register 26 with the beginning of the positive half-wave voltage u ₁ . If the period of the supply voltage changes, then the code X10 at the output of the memory block 10 changes accordingly, and the control angle remains unchanged and corresponds to the code at the output of the register 12.

Thus, the proposed device provides control of semiconductor converters that can be powered from a single-phase and three-phase network with an almost smooth change in the specified angle of control and its high stability in conditions of unstable frequency of the supply network. The stage Δα of the change in the specified control angle α depends on the digit capacity of m register 12 and is Δα = 180 ° / m. The error δα of the control angle α is determined by the ratio of the network frequencies сети _C and the generator генератора ₁₁ pulses 11 δα <ƒ ₁₁ / (2ƒ _C ) and the digit capacity k of counters 7, 8, 16, 17, comparators 9, 24, 25 and memory block 10, which associated with the mentioned frequencies by the ratio ƒ ₁₁ / (2ƒ _C ) <2 ^{k + 1} -1.

Information sources

1. Gorbachev G.N., Chaplygin E.E. Industrial Electronics: A Textbook for High Schools / Ed. V.A. Labuntsova. - M: Energoatomizdat, 1988, p. 275-287.

2. The same with. 284-285, fig. 8.7.

3. Description of the invention to the patent RU 2612055 C1, 2017.

Claims (1)

A three-channel digital phase-shifting device containing the first rectangular pulse shaper, the first short pulse shaper, the output of which is connected to the input of recording the initial number of the first subtractive counter, the logical element NOT, the output of which is connected to the input of the second shaper of short pulses and to the first input of the second logical element And, connected by the second input with the output of the stable frequency pulse generator and the second input of the first logic element AND, the sum counter, the counting input D of which is connected to the output of the second logic element I, the fault input to the output of the second shaper of short pulses, and the output bits to the corresponding bits of the input of the initial number of the first subtractive counter, the subtracting input of which is connected to the output of the first logic element I, the first input of which is connected to the input of the logical element NOT, the input of the first shaper of short pulses and the output of the first shaper of rectangular pulses, the input of which through the first diode is connected to the first phase of the network, and the discharge The dips of the output of the first subtractive counter are connected to the corresponding bits of the first input of the first numerical comparator, the EQUAL output of which is the first output of the device and which bits of the second input are associated with the corresponding bits of the output of the memory block, the corresponding bits of the output of the master register that are different to the bits of the address input of the second coordinate the fact that in order to expand the functionality provided with the third and fourth logical elements of And, the second and third subtractive counters, second and third rectangular pulse shapers, third and fourth short pulse shapers, second and third diodes, second and third numerical comparators and a memory register connected to the recording input to the output of the first short pulse shaper, input bits to the corresponding digits of the summing counter, and the output bits to the corresponding input bits of the address of the first coordinate of the memory block and the inputs of the initial number of the second and third subtractive counters, bits of the output which are connected to the corresponding bits of the first inputs of the second and third numerical comparators, respectively, the outputs of the EQUAL of which are the outputs of the second and third channels of the device, respectively, and the bits of the second inputs of the numerical comparators are connected to the corresponding bits of the output of the memory unit, in addition, the second phase of the mains through the second the diode is connected to the input of the second rectangular pulse shaper, the output of which is connected directly to the first input of the third logic element AND, and the third shaper short pulses - with the input record of the original number of the second subtractive counter, the subtracting input of which is connected to the output of the third logical element And connected by the second input to the input of the generator of stable pulses and the second input of the fourth logical element And the output of which is connected to the subtractive input of the third subtractive the counter, the input entry of the original number of which is connected to the output of the fourth shaper of short pulses connected by the input with the first input of the fourth logical element cient and AND output of the third rectangular pulse shaper whose input is connected via a third diode to the third phase mains.

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