RU2674934C1 - Data groups shifting device - Google Patents

Abstract

FIELD: computer engineering.SUBSTANCE: invention relates to the field of computing and can be used in signal processing processors and general-purpose processors, devices for converting information, encoding and decoding data, and cryptography devices. Device contains N groups of external input data DG1, DG2, …, DGN with bit width W1, W2, …, WN, respectively, U bits of the external inputs of the task value of the number of shifts V0, V1, …, V(U-1) by the amount of shift groups from 0 to L, where U=[logL]+1(smaller integer), (N+L) groups of external output data QG1, QG2, …, QG(N+L), U cascades of modules of elements from the 0th to (U-1), each i-th stage of which, where i=0, 1, …, (U-1), contains by (N+2-1) modules of elements combined in three sections, (U+1) internal shear tires SB0, SB1, …, SBU with digit capacity of groups K (i, j), where j=1, 2, …, (N+2-1) – the module number in the cascade, the first sections of the cascades consist of modules containing groups of 2AND gates with a second inverse input, the second sections of cascades consist of modules containing groups of 2AND gates with a second inverse input, 2AND gates and 2OR gates, and the third sections of cascades consist of modules containing groups of 2AND gates.EFFECT: technical result is the ability to shift groups of binary data of different bit widths without losing the advanced discharges and reducing hardware costs.1 cl, 1 dwg, 5 tbl

Description

The invention relates to the field of computer technology and can be used in signal processors and general purpose processors, information conversion devices, data encoding and decoding, cryptography devices.

A device Circuit for rotating, left shifting, or right shifting bits is known (US 5978822 (A) IPC G06F 5/01, G06F 7/76, claimed December 29, 1995, published November 2, 1999), which describes a device for performing logical, cyclic and arithmetic shifts of the input data left and right by a given number of bits. The device contains a matrix of shift multiplexers in only one direction — to the left, higher bits, a multiplexer for transmitting input data in the forward or “inverted” reverse order of bits, a multiplexer for transmitting bits of a code for the shift value or their inversion, the outputs of which control the matrix of multiplexers, and an output transfer multiplexer for shifting data in the direct order of the bits or in the “inverted” reverse order of the bits with a shift of one bit.

The disadvantages of this device is the low speed, since the input data, in addition to the matrix of multiplexers, additionally passes through the input data transmission multiplexer and the output multiplexer, and the loss of the most advanced extended bits during a logical shift.

A device is known Fast conversion two's complement encoded shift value for a barrel shifter (US 5948050 (A) IPC G06F 5/01, claimed 19.12.1996, published 07.09.1999), which describes a device for performing cyclic or logical shifts left or right N bit input data for a shift value in the range from 0 to N-1 bits, which is set by M bits, where M = log ₂ N. The shift device contains N bit input data, N bit output data, M bits sets the number of shifts, a bi-directional matrix shear dimension N × N, a group of M elements EXCLUSIVE LEE, decoder shift direction, decoder and multiplexer amount and shift direction.

The disadvantages of this device is the large amount of equipment and low speed, as well as the inability to perform shifts of N or more N digits and the loss of senior extended digits in a logical shift.

The closest device of the same purpose to the claimed invention in terms of features is the shear device adopted for the prototype (RU No. 2613533 C1, IPC G06F 5/01, G11C 19/00, H03M 13/00 announced on 02/08/2016, published on 03/16/2017 , Bull. No. 8), containing N bits of external input data D0, D1, ..., D (N-1), N bits of output data Y0, Y0, ..., Y (N-1), V bits of setting the value of the number of shifts K0 , K1, ..., K (V-1), a bi-directional shift matrix of dimension N × M, where M≤log ₂ N, from M cascades containing groups of elements 2I-2I-2I-3ILI and 2I-2I-2OR, modification block amount of shift s, the direction of shift control unit and forming unit zero result flag, wherein the matrix shift stages comprise three groups of elements.

The disadvantages of this device are the loss of the most advanced extended bits during a logical shift, the inability to perform group shifts of input data of a given bit depth and a large amount of equipment.

The technical result of the proposed device is the ability to shift groups of binary data of different capacities without loss of extended bits and reduce hardware costs.

The specified technical result in the implementation of the invention is achieved by the fact that the device shift data groups contains

N groups of external input data DG1, DG2, ..., DGN, with bits of groups W1, W2, ..., WN, respectively, U bits of the external inputs to specify the number of shifts V0, V1, ..., V (U-1) by the group shift from 0 to L, where U = [log ₂ L] +1 (smaller integer), (N + L) groups of external output data QG1, QG2, ..., QG (N + L), (U + 1) internal shift buses SB0 , SB1, ..., SBU, U cascades of modules of elements from 0 to (U-1), of which each i-th cascade, where i = 0, 1, ..., (U-1), contains (N + 2 ^{i + 1} -1) modules of elements combined in three sections,

moreover, the first sections of cascades consist of modules containing a group of elements 2I with a second inverse input, the second sections of cascades consist of modules containing a group of elements 2I with a second inverse input, elements 2I and 2IL elements, and the third sections of cascades consist of modules containing a group of elements 2I,

moreover, in each i-th cascade, the first sections contain 2 ⁱ modules of elements, starting from the first to 2 ⁱ modules of the i-th cascade, the second sections contain (N-1) modules of elements, starting from (2 ⁱ +1) to the (N + 2 ⁱ -1) module of the i-th cascade, and the third sections contain 2 ⁱ modules of elements, starting from the (N + 2 ⁱ ) th to (N + 2 ^{i + 1} -1) modules of the i-th cascade cascade

moreover, N groups of external input data DG1, DG2, ..., DGN are N groups of bits of the 0th internal shift bus SB0 with the bits of the groups K (0, 1), K (0, 2), ..., K (0, N), respectively , and the module outputs of the elements of each i-th cascade form the corresponding groups of cascade outputs and are the bit groups of the subsequent (i + 1) -th internal shift bus SB (i + 1) with the bit depth of the groups K (i + 1, j), where j = 1, 2, ..., (N + 2 ^{i + 1} -1) is the number of the module in the cascade, while the bits of the groups of the first U internal shift buses SB0, SB1, ..., SB (U-1), except for the last internal SBU bus connected to the inputs of the groups of modules eleme comrade respective stages with the same names 0th to (U-1) th stage,

and in each i-th cascade in the first sections of the modules in each j1-th module, where j1 = 1, 2, ..., 2 ⁱ , there is a group of K (i, j1) elements 2I with a second inverse input, the outputs of which are outputs the first lower 2 ⁱ modules, from the first to the (2 ⁱ ) -th module of the i-th cascade,

in the second sections of the modules of each i-th cascade, each j2-th module contains K (i, j2) elements 2I with a second inverse input, K (i, j2-2 ⁱ ) elements 2I, where j2 = 2 ⁱ +1, 2 ⁱ +2, ..., (2 ⁱ + N-1) and (min (К (i, j2), К (i, j2-2 ⁱ ))) elements 2 OR, in which the first and second inputs are connected to the outputs of the corresponding first elements 2I with the second inverse input and the corresponding first elements 2I of the j2nd module, with each j2nd module has (max (К (i, j2), К (i, j2-2 ⁱ ))) outputs, of which the first (min (К (i, j2), К (i, j2-2 ⁱ ))) the outputs of the j2th module are connected to the outputs of the elements 2 OR, and the outputs of the j2th module with (min (К ( i, j2), К (i, j2-2 ⁱ )) + 1) th to (max (К (i, j2), К (i, j2-2 ⁱ ))) of the second connected to the outputs of the same elements 2I with the second inverse input of the module at K (i, j2)> K (i, j2-2 ⁱ ) or connected to the outputs of the same elements 2and the module at K (i, j2) <K (i, j2-2 ⁱ ),

and in the third sections of each i-th cascade in each j3-th module, where j3 = 2 ⁱ + N, 2 ⁱ + N + 1, ..., (2 ^{i + 1} + N-1), contains a group from K (i , j3) elements 2I, the outputs of which are the outputs of the last senior 2 ⁱ modules, from the (N + 2 ⁱ ) th to the (N + 2 ^{i + 1} -1) th module of the i-th cascade,

moreover, in each i-th cascade, the first inputs of all elements 2I with a second inverse input are connected to the first inputs of the corresponding elements of the same name 2I and are also connected to the corresponding bits of the groups of the corresponding i-th internal shift bus SBi, and the second inverse inputs of all elements 2I with a second inverse the input is interconnected and also connected to the second inputs of all elements 2I and connected to the corresponding Vi-th discharge of the external inputs of the value of the number of shifts,

the outputs of (N + L) groups of the last highest (U + 1) -th internal shift bus SBU are (N + L) groups of external output data QG1, QG2, ..., QG (N + L) with the capacity of groups K (U, 1 ), K (U, 2), ..., K (U, (N + L)), respectively.

In FIG. 1 shows a diagram of the proposed device for shifting data groups with the number of groups N = 5 with the group widths W1 = 2, W2 = 2, W3 = 3, W4 = 2, W5 = 1 and the shift value L = 7.

In FIG. 1 and the following notation is introduced in the text:

DG1, DG2, ..., DGN - N groups of external input data, with bits W1, W2, ..., WN, respectively,

L is the magnitude of the shift groups

V0, V1, ..., V (U-1) - U bits of the external inputs of setting the value of the number of shifts, where U = [log ₂ L] +1 (smaller integer),

QG1, QG2, ..., QG (N + L) - (N + L) groups of external output data,

K (U, 1), K (U, 2), ..., K (U, (N + L)) - the width of the groups of external output data,

SB0, SB1, ..., SBU - (U + 1) internal shift buses,

i is the cascade number, where i = 0, 1, ..., (U-1),

j1 - the module number in the first section of each i-th stage, where j1 = 1, 2, ..., 2 ^i,

j2 is the module number in the second sections of each i-th cascade, where j2 = 2 ⁱ +1, 2 ⁱ +2, ..., (2 ⁱ + N-1),

j3 is the module number in the third sections of each i-th cascade, where j3 = 2 ⁱ + N, 2 ⁱ + N + 1, ..., (2 ^{i + 1} + N-1),

j is the module number in the cascade, where j = 1, 2, ..., (N + 2 ^{i + 1} -1),

K (i, j) is the bit depth of the groups of the j-th module in the i-th cascade,

1j - j-th module of elements in the cascade,

2 - element 2I with a second inverse input,

3 - element 2I,

4 - element 2 OR.

The device has N groups of external input data DG1, DG2, ..., DGN, with a capacity of groups W1, W2, ..., WN, respectively, U bits of the external inputs to specify the number of shifts V0, V1, ..., V (U-1) by the amount of shift groups from 0 to L, where U = [log ₂ L] +1 (smaller integer), (N + L) groups of external output data QG1, QG2, ..., QG (N + L), (U + 1) internal buses shift SB0, SB1, ..., SBU, U cascades of modules of elements from 0 to (U-1), of which each i-th cascade, where i = 0, 1, ..., (U-1), contains by ( N + 2 ^{i + 1} -1) modules of elements combined in three sections.

The first sections of cascades consist of modules containing a group of elements 2I with a second inverse input, the second sections of cascades consist of modules containing a group of elements 2I with a second inverse input, elements 2I and 2IL elements, and the third sections of cascades consist of modules containing a group of elements 2I.

In each i-th cascade, where i = 0, 1, ..., (U-1), the first sections contain 2 ⁱ modules of elements, starting from the first to 2 ⁱ modules of the i-th cascade, the second sections contain (N- 1) modules of elements, starting from (2 ⁱ +1) th to (N + 2 ⁱ -1) modules of the i-th cascade, and the third sections contain 2 ⁱ modules of elements, starting from (N + 2 ⁱ ) -th to (N + 2 ^{i + 1} -1) the module of the i-th cascade.

N groups of external input data DG1, DG2, ..., DGN are N groups of bits of the 0-th internal shift bus SB0 with the bits of the groups K (0, 1), K (0, 2), ..., K (0, N), respectively. The outputs of the modules of the elements of each i-th cascade form the corresponding groups of outputs of the cascades and are groups of bits of the subsequent (i + 1) -th internal shift bus SB (i + 1) with the bit depth of the groups K (i + 1, j), where j = 1 , 2, ..., (N + 2 ^{i + 1} -1) - the number of the module in the cascade. The discharges of the groups of the first U internal shift buses SB0, SB1, ..., SB (U-1), in addition to the last internal SBU bus, are connected to the inputs of groups of modules of elements of the corresponding cascades of the same name from the 0th to the (U-1) th cascade.

Each i-th cascade in the first sections of the modules in each j1-th module, where j1 = 1, 2, ... 2 ⁱ , contains a group of K (i, j1) elements 2I with a second inverse input, the outputs of which are the outputs of the first junior 2 ⁱ modules, from the first to the (2 ⁱ ) -th module of the i-th cascade.

In the second sections of the modules of each i-th cascade, each j2-th module contains K (i, j2) elements 2I with a second inverse input, K (i, j2-2 ⁱ ) elements 2I, where j2 = 2 ⁱ +1, 2 ⁱ +2, ..., (2 ⁱ + N-1) and (min (К (i, j2), ..., К (i, j2-2 ⁱ ))) 2 OR elements in which the first and second inputs are connected to the outputs the corresponding first elements 2I with a second inverse input and the corresponding first elements 2I of the j2nd module. Moreover, each j2nd module has (max (К (i, j2), К (i, j2-2 ⁱ ))) outputs, of which the first (min (К (i, j2), К (i, j2- 2 ⁱ ))) the outputs of the j2nd module are connected to the outputs of the 2 OR elements, and the outputs of the j2th module from (min (К (i, j2), К (i, j2-2i)) + 1) -st to ( max (K (i, j2), K (i, j2-2 ⁱ ))) of the second connected to the outputs of the elements of the same name 2I with the second inverse input of the module at K (i, j2)> K (i, j2-2 ⁱ ) or connected to the outputs of the elements of the same module 2I at K (i, j2) <K (i, j2-2 ⁱ ).

In the third sections of each i-th cascade in each j3-th module, where j3 = 2 ⁱ + N, 2 ⁱ + N + 1, ..., (2 ^{i + 1} + N-1), contains a group from K (i, j3) elements 2I, the outputs of which are the outputs of the last senior 2 ⁱ modules, from the (N + 2 ⁱ ) th to the (N + 2 ^{i + 1} -1) th module of the i-th cascade.

In addition, in each ith cascade, the first inputs of all elements 2I with a second inverse input are connected to the first inputs of the corresponding elements of the same name 2I and are also connected to the corresponding bits of the groups of the corresponding i-th internal shift bus SBi, and the second inverse inputs of all elements 2I to the second the inverse input are interconnected, and also connected to the second inputs of all elements 2I and connected to the corresponding Vi-th discharge of the external inputs to set the number of shifts.

The outputs of the (N + L) groups of the last highest (U + 1) -th internal shift bus SBU are (N + L) groups of external output data QG1, QG2, ..., QG (N + L) with the capacity of the groups K (U, 1 ), K (U, 2), ..., K (U, (N + L)), respectively.

The principle of operation of the device is as follows.

The device is designed for group left shifts towards the older groups of N groups of external input data DG1, DG2, ..., DGN, with a given bit depth of the groups W1, W2, ..., WN, respectively, by the amount of shift of the groups from 0 to L. The input data groups are integer unsigned numbers. In the input, the DG1 group is the youngest group, and the DGN group is the senior group. The shift of data groups is carried out in U cascades of modules containing a group of elements 2I with a second inverse input, elements 2I and elements 2OR, where U = [log ₂ L] + l (a smaller integer). The magnitude of the shift of the groups L is set by U bits of the external inputs to set the number of shifts V0, V1, ..., V (U-1).

In each i-th cascade, the first inputs of all elements 2I with a second inverse input and the first inputs of all elements 2I receive data of the corresponding bits of groups from the internal bus SBi, and the second inputs of all elements 2I with a second inverse input and the second inputs of all elements 2I receive the value from the corresponding Vi-th digit of the task of the value of the number of shifts. But since the elements 2I are located in cascade modules with a left shift (towards the older groups) relative to the elements 2I with an inverse input to 2 ⁱ modules, the data from the internal buses to the outputs of the elements 2I with an inverse input are transmitted without a shift at Vi = 0, and to the outputs of the elements 2I with a shift of 2 'groups at Vi = 1.

With a shift, the bits of the input data by groups are shifted to the left towards the older groups by the amount of shift L without loss of the extended bits of the groups. In this case, the digits L of the lower groups are filled with zeros. Table 1 shows an example of a shift of eight groups of input data DG1, DG2, ..., DG8 by the amount of shift in the range from 0 to 7 groups. Table 2 shows an example of shifting input data groups by cascades. In each ith cascade, where i = 0, 1, ..., (U-1), data groups are transferred without a shift or with a shift of 2 ⁱ groups to the left. The inputs of the 0th stage receive input data groups. Further, from the outputs of the previous i-th stage, data groups are transferred to the internal bus SB (i + 1) and then to the inputs of the subsequent (i + 1) -th stage.

In table 2, three sections of data groups are highlighted in cascades:

- in the first sections, lower cascade groups, the cascade outputs at zero value of the input of the shift job Vi = 0 transmit the value of the input groups of the cascade from the internal SBi bus without a shift, and at a single value of Vi = 1, zero bits are formed, which is implemented on elements 2I with an inverse input (inhibit input) connected to the input of the shift job Vi,

- in the second sections, middle groups of cascades, data is transmitted to the outputs without a shift (Vi = 0) or with a shift of 2 ⁱ groups (Vi = 1) to the left, which is implemented on elements 2I with an inverse input and elements 2I, the outputs of which are connected by digits with the inputs of the corresponding elements 2OR,

- in the third sections, the senior cascade groups, data is transmitted to the outputs from the internal SBi bus with a shift of 2 ⁱ groups (Vi = 1) to the left or zero bit values (Vi = 0) are generated, which is implemented on elements 2I.

If all groups of input data DG1, DG2, ..., DGN have the same bit depth of the groups W1 = W2 = ... = WN = w, then in all modules of elements of all stages the number of input bits of the groups and the number of outputs of the module are equal to w. For example, in table 3, for the five groups of input data DG1, DG2, ..., DG5 and the bit depth of all groups w = 3 with the group shift value from 0 to L = 7, an example of calculating the required number of 2I elements with an inverse input (indicated by nonI) is given , elements 2I (AND) and elements 2OR (OR) in stages and modules, and also the bit depths of the groups K (i, j) of the internal shift buses SB0, SBI, SB2, SB3 are marked. The total number of elements in three stages is 150 elements.

Table 4 shows the calculations of the number of elements in cascades and modules for five groups of input data DG1, DG2, ..., DG5 and bit depths of the groups W1 = 2, W2 = 2, W3 = 3, W4 = 2, W5 = 1 with the group shift from 0 to L = 7, with a shift of groups from 0 to L = 7. In this case, in the modules of the first sections, the number of output bits is equal to the number of input bits in the group and the values of the outputs are transmitted from the outputs of elements 2I with an inverse input, the number of which is equal to the input bit depth of the module. In the modules of the second sections, when the number of bits of groups without a shift and groups with a shift is equal, the number of output bits is also equal to the number of input bits in groups. In each module of the second sections, when the bit depth of the input groups without a shift exceeds the bit depth of the groups with a shift, the highest bits of the module outputs are connected to the outputs of 2I elements with an inverse input, and when the bit depth of the input groups with a shift exceeds the bit depth of groups without a shift, the higher bits of the module outputs are connected to the outputs elements 2I. In the modules of the third sections, the number of output bits is equal to the number of input bits in the group and the values of the outputs are transmitted from the outputs of 2I elements, the number of which is equal to the input bit depth of the module.

The values of the external (N + L) groups of output data QG1, QG2, ..., QG (N + L) are taken from the last highest (U + 1) -th internal shift bus SBU, and the bit capacity of the output groups corresponds to the bit width of the modules of the elements of the last (U- 1) of the cascade, which are the bits of the internal bus groups SBU - K (U, 1), K (U, 2), ..., K (U, (N + L)), respectively.

The proposed device operates as follows.

N input groups of external input data DG1, DG2, ..., DGN with a given bit depth W1, W2, ..., WN, respectively, U bits of the external inputs of setting the number of shifts V0, V1, ..., V (U-1), specifying the amount of shift from 0 to L groups.

Next, N groups of external input data DG1, DG2, ..., DGN go to the internal shift bus SB0 and then to the 0th cascade of element modules. For example, Table 4 shows the number of elements and the bit depth of the cascade modules for five N = 5 input data groups DG1, DG2, ..., DG5 with a given bit depth of the groups W1 = 2, W2 = 2, W3 = 3, W4 = 2, W5 = 1 with a shift of groups from 0 to L = 7. The 0th stage contains 10 2I elements with an inverse input and 10 2I elements, which corresponds to the input bit depth of all groups. In the first module 1 ₁ (j = 1) of the 0th stage, the input group DG1 has a capacity of two K (0, 1) = 2, so the first module contains two 2I elements with an inverse input, the outputs of which are transmitted to the outputs of the cascade and the internal bus SB1 and have a capacity of K (1, 1) = 2. In the second module, 1 ₂ (j = 2) of the 0th cascade of data bits without a shift K (0, 2) = 2 and with a shift K (0, 1) = 2 are equal to each other, therefore the second module 1 _{2 of the} 0 cascade contains two elements 2I with an inverse input, two elements 2I and two elements 2OR, and also the bit capacity of the outputs of the cascade transmitted to the internal bus SB1 is equal to two K (1, 2) = 2. In the third module 1 ₃ (j = 3) of the 0th stage, the width of the data group without a shift is three K (0, 3) = 3, and the width of the data group with a shift is two K (0, 2) = 2, so the third module 1 ₃ contains three elements 2I with an inverse input, two elements 2I and two elements 2OR - equal to the minimum value of bit capacity (min (K (0, 3), K (0, 2))) = 2. The output bit depth of the third module 1 _{3 of the} 0 cascade transmitted to the internal bus SB1 is three K (1, 3) = 3 - the maximum value of the bit depth of the input groups of the module (max (K (0, 3), K (0, 2))) = 3. In this case, the outputs from the outputs of the two elements of the 2 OR, are transmitted to the outputs of the two least significant bits of the third module 1 ₃ (j = 3), and the value from the output of the third element 2I with an inverse input is transmitted to the third output. In the fourth module 1 ₄ (j = 4) of the 0th stage, the width of the data group without a shift is two K (0, 4) = 2, and the width of the data group with a shift is three K (0, 3) = 3, so the fourth module 1 ₄ contains two elements 2I with an inverse input, three elements 2I and two elements 2OR - equal to the minimum value of bit capacity (min (K (0, 4), K (0, 3))) = 2. The output bit depth of the fourth module 1 _{4 of the} 0 stage transmitted to the internal bus SB1 is three K (1, 4) = 3 - the maximum bit value of the input groups of the module (max (K (0, 4), K (0, 3))) = 3. At the same time, the values from the outputs of the two elements of 2 OR are transferred to the outputs of the two least significant bits of the fourth module 1 ₄ (j = 4), and the value from the output of the third element 2I is transmitted to the third output. The fifth module 1 ₅ (j = 5) of the 0 stage contains one 2I element with an inverse input, two 2I elements and one 2 OR element - it is equal to the minimum bit value (min (К (0, 5), К (0, 4) )) = 1. The output bit depth of the fifth module 1 _{5 of the} 0th cascade transmitted to the internal bus SB1 is two K (1, 5) = 2 - the maximum bit value of the input groups of the module (max (K (0, 5), K (0, 4))) = 2. The sixth module 1 ₆ (j = 6) of the 0th stage contains only one element 2I, the output of which is transmitted to the output of the module and to the internal bus SB1 K (1, 6) = 1. Thus, in the 0-th cascade contains 27 elements, including ten elements 2I with an inverse input, ten elements 2I and seven elements 2OR, and the capacity of the outputs of six groups (modules) is 13 bits.

Further, in the first stage, a shift by 2 ¹ groups or transfer of input groups from the 0th stage without a shift can be performed depending on the value of the discharge V1 of the external inputs of the number of shifts. The first stage contains 33 elements (see table 4), and the capacity of the outputs of eight groups (modules) is 19 bits. Similarly, further in the second stage there are 45 elements (see table 4), and the bit width of the outputs of twelve groups (modules) is 31 bits, which are transmitted to the outputs of the twelve external output groups QG1, QG2, ..., QG12) with the corresponding bits K (3, 1), K (3, 2), ..., K (3, 12).

Thus, in the device, it is possible to perform shifts of N groups of input data of different lengths by a shift in the range from 0 to L groups.

In the proposed device for the shift of five N = 5 groups of input data DG1, DG2, ..., DG5 with a given capacity of the groups W1 = 2, W2 = 2, W3 = 3, W4 = 2, W5 = 1 with the value of the shift of groups from 0 to L = 7 requires 105 elements (see table 4). When implementing a device for shifting data of five groups and setting the bit depth of groups equal to the maximum number of bits in the groups, w = W3 = 3 for all groups, 150 elements are needed (see calculations in table 3) and the total bit depth of the output groups is 36. Thus, in the proposed device for the implementation of the shift of five N = 5 groups of input data DG1, DG2, ..., DG5 with a given capacity of the groups W1 = 2, W2 = 2, W3 = 3, W4 = 2, W5 = 1, 30% less hardware is needed . Similarly, Table 5 shows the distribution of elements and the bit depth of the groups according to cascades and element modules for five N = 5 input data groups DG1, DG2, DG5 with a given bit depth of the groups W1 = 3, W2 = 3, W3 = 3, W4 = 2, W5 = 1 with a shift of groups from 0 to L = 7. The total number of elements 114, and the total bit depth of the output groups 32, i.e. in the proposed device, 24% less hardware is needed. Therefore, in the proposed device requires less hardware to shift data groups.

The above information allows us to conclude that the proposed device for shifting data groups has a regularity of nodes and connections, and corresponds to the claimed technical result - the expansion of functionality, in terms of the possibility of shifting groups of binary data of different capacities without losing extended bits, and reducing hardware costs.

Claims (1)

The device for shifting data groups contains N groups of external input data DG1, DG2, ..., DGN with the bits of groups W1, W2, ..., WN, respectively, U bits of the external inputs of setting the number of shifts V0, V1, ..., V (U-1) by the shift of groups from 0 to L, where U = [log ₂ L] +1 (smaller integer), (N + L) groups of external output data QG1, QG2, ..., QG (N + L), (U + 1) internal shift buses SB0, SB1, ..., SBU, U of cascades of element modules from 0 to (U-1), of which each i-th cascade, where i = 0, 1, ..., (U-1), contains for (N + 2 ^{i + 1} -1) of the elements of modules grouped into three sections, the first section consists of a cascade of modules, containing groups of elements 2I with a second inverse input, the second sections of cascades consist of modules containing groups of elements 2I with a second inverse input, elements 2I and elements 2OR, and the third sections of cascades consist of modules containing groups of elements 2I, and in each i-th In the cascade, the first sections contain 2 ⁱ modules of elements, starting from the first to 2 ⁱ modules of the i-th cascade, the second sections contain (N-1) modules of elements, starting from the (2 ⁱ +1) th to (N + 2 ⁱ -1) module i-th stage, and third sections contain elements 2 ⁱ modules, starting with (N + 2 ⁱ⁾ th d (N + 2 ^{i + 1} -1) module i-th stage, the N groups of the external input data DG1, DG2, ..., DGN groups are N bits of 0-th inner SB0 shift bus with the bit groups K (0, 1), K (0, 2), ..., K (0, N), respectively, and the module outputs of the elements of each i-th cascade form the corresponding groups of cascade outputs and are the group of bits of the subsequent (i + 1) -th internal shift bus SB (i + 1) with the bit depth of the groups K (i + 1, j), where j = 1, 2, ..., (N + 2 ^{i + 1} -1) is the number of the module in the cascade, while the bits of the groups of the first U internal shift buses SB0, SB1, ..., SB (U-1), besides the last internal SBU bus, are connected to by moves of groups of modules of elements of the corresponding cascades of the same name from the 0th to the (U-1) -th cascade, and in each i-th cascade in the first sections of the modules in each j1-th module, where j1 = 1, 2, ..., 2 ⁱ , contains a group of K (i, j1) elements 2I with a second inverse input, the outputs of which are the outputs of the first lower 2 ⁱ modules, from the first to the (2 ⁱ ) th module of the i-th cascade, in the second sections of the modules of each i-th the cascade in each j2nd module contains K (i, j2) elements 2I with a second inverse input, K (i, j2-2 ⁱ ) elements 2I, where j2 = 2 ⁱ +1, 2 ⁱ +2, ..., (2 ⁱ + N-1) and (min (K (i, j2 ), K (i, j2-2 i))) 2 or elements have to the first and second inputs are connected to the outputs of the corresponding first elements 2I with the second inverse input and the corresponding first elements 2I of the j2nd module, each j2nd module has (max (K (i, j2), K (i, j2- 2 ⁱ ))) outputs, of which the first (min (K (i, j2), K (i, j2-2 ⁱ ))) outputs of the j2th module are connected to the outputs of the 2 OR elements, and the outputs of the j2th module with (min (K (i, j2), K (i, j2-2 ⁱ )) + 1) th to (max (K (i, j2), K (i, j2-2 ⁱ ))) th connected with the outputs of the elements of the same name 2I with the second inverse input of the module at K (i, j2)> K (i, j2-2 ⁱ ) or connected with the outputs of the same elements 2I of the module with K (i, j2) <K (i, j2-2 ⁱ ), and in the third sections of each i-th cascade in each j3-th module, where j3 = 2 ⁱ + N, 2 ⁱ + N + 1, ..., (2 ^{i + 1} + N-1), contains a group of K (i, j3) elements 2I, the outputs of which are the outputs of the last senior 2 ⁱ modules, from the (N + 2 ⁱ ) th to the (N + 2 ^{i + 1} -1) th module of the i-th cascade, and in each i-th cascade, the first inputs of all elements 2I with a second inverse input are connected to the first inputs of the corresponding elements of the same name 2I and are also connected to the corresponding bits of the groups of the corresponding i-th internal shift bus SBi, and the second inverse inputs of all elements 2I with the second inverse are connected to each other and connected to the second inputs of all 2I elements and connected to the corresponding Vi-th bit of the external inputs of setting the value of the number of shifts, outputs (N + L) of the groups of the last senior (U + 1) -th internal shift bus SBU are (N + L) groups of external output data QG1, QG2, ..., QG (N + L) with the capacity of the groups K (U, 1), K (U, 2), K (U, (N + L)), respectively .

Images