RU2669720C1 - Electronic device for aircraft chair - Google Patents

Abstract

FIELD: manufacturing technology.SUBSTANCE: electronic device of the catapult chair contains the processor, RAM, ROM, switch, clock, timer, switch, four pressure sensors, a group of optocouplers, MEC controller, controller, four optocouplers, three power-reset circuits, four generators, two gate shutters, two AND elements, an OR element, a key connected in a specific way.EFFECT: quality and reliability of bailouts are improved.14 cl, 25 dwg

Description

The invention relates to aviation and is intended for use in an ejection seat of the type K36L-3,5Ya (hereinafter referred to as KK) and performs the functions of an electronic parachute device (EUKK).

The invention is known to US 4505444 A [1], an aircraft landing system, which includes means for ejecting the main parachute at the end of the delay after the chair is ejected and a mode switching mechanism capable of deploying the parachute at a shorter predetermined time after the ejection, if the ejection occurs on low speed and low altitude. The mode selection mechanism includes a piston sliding along the hole to control the firing pin to close the relay contacts and, thus, provides earlier opening of the parachute.

Aircraft landing system having an ejection seat for accommodating the pilot and the main parachute for lowering the pilot to the ground, means for ejecting said main parachute at the end of the delay after initiating the ejection of the ejection seat and pilot, and this means includes a parachute with a throttle functionally associated with the specified seat and means for a temporary delay for a predetermined time after the mentioned initiation of the ejection; and also mode selection means for determining at least one predetermined condition and for permitting the main parachute to be ejected prior to the expiration of the delay, provided that a predetermined condition is determined, the mode selection mechanism means including means for determining a deceleration of the ejection seat position and pilot, using a parachute and means for braking the switching mechanism, leading to the disclosure of the main parachute after a specified time before the expiration of the delay.

The invention is known US 4,527,758 A [2], an electronic system for selecting the sequence of the correct mode and the correct sequence of ejection. The system measures altitude, speed, true speed and compares them with the given reference signals. The system also includes logic and time delay circuits. Logic circuits are organized to select one of four time delays depending on the state of various parameters relative to the reference signals. The aim of this invention is to optimize the deployment sequence of the parachute, choosing the moment of ejection, choosing the right time sequence to initiate deployment of the parachute, using the true speed of the aircraft, as well as the height and speed in choosing the right synchronization sequence to start deploying the parachute, creating an ejection system suitable for installation on aircraft, creating a parachute ejection system suitable for use with existing sensors. The above functions are implemented in the present invention using electronic circuits for comparing the input signals of flight speed, airspeed and true speed with the given values. This circuit, in turn, transmits a signal or signals to a plurality of electronic logic circuits. These logic circuits also receive turn-on signals when the moment the parachute is released. Logic circuits select the appropriate time delay when the correct combination of input and enable signals is received. Time delay is performed using electronic time delay circuits, each of which has a different pulse width. In addition, electronic circuits are provided to block additional input signals from the sensor after selecting a time delay. An “open parachute” signal is generated when a trailing edge of a time delay pulse is detected.

Significant disadvantages of each of these devices is the low reliability and insufficient quality of ejection.

Closest to the technical essence of the invention (prototype) is a microprocessor device performing bailouts [3], containing a processor, RAM, ROM, switch (Time Zero Switch), clock (clock), timer, switch (Power switch), the first, second and the third pressure sensors, multiplexer and ADC, parachute discharge squib, autonomous power supply and filter, the first and second outputs of which are connected to the first and second inputs of the switch, the output of which is connected to the input of the parachute discharge squib, and the switch outputs, The aces and the timer are connected to the first, second and third inputs of the processor, the first, second, third and fourth outputs of which are connected to the inputs of the clock, the timer of the switch and the switch, and the group of processor outputs is connected to the group of RAM inputs, the group of outputs of which is connected to the group of processor inputs , the second group of inputs of which is connected to the group of outputs of the ROM, and the fifth and sixth outputs of the processor are connected to a power source and to the control input of the multiplexer, the first, second and third inputs of which are connected to odes first, second and third sensors, a multiplexer output coupled to the input of the ADC, the output of which is coupled to a fifth input of the processor, wherein the power supply output is connected to the input of the filter.

The described device as the closest to the alleged taken as a prototype.

The disadvantage of this device is the low reliability and insufficient quality of the bailout.

The objective of the invention is to improve the quality of the bailout and increase reliability through the use of the channel-model structure, which implements the function of the ejection of the parachute with the coincidence of the calculation results of the channel and model in the range. In case of mismatch of calculations in the range, the device provides for a duplicated scheme of a hot reserve for generating a parachute ejection signal according to the maximum permissible parameters.

The essence of the claimed invention, the possibility of its implementation and industrial use are illustrated by the drawings shown in FIG. 1 ... FIG. 25 where

• in FIG. 1 shows the architecture of an electronic device for an ejection seat for an airplane;

• in FIG. 2 is a structural diagram of an electronic device of an ejection seat for an airplane;

• in FIG. 3 shows the functional diagram of the Monitoring device (Controller);

• in FIG. 4 is a functional diagram of an ejection signal generation unit;

• in FIG. 5 is a functional diagram of the SPI_SLAVE node;

• in FIG. 6 is a functional diagram of an SPI-STATE node;

• in FIG. 7 is a functional diagram of a control unit;

• in FIG. 8 is a functional diagram of a CMND signal conditioning unit;

• in FIG. 9 is a functional diagram of a signal conditioning unit MASK;

• in FIG. 10 is a functional diagram of a parameter selection node;

• in FIG. 11 is a functional diagram of the counter node dt1 ... dt6, dtc;

• in FIG. 12 is a functional diagram of a ZBV assembly;

• in FIG. 13 is a functional diagram of a delay driver FZ1;

• in FIG. 14 is a functional diagram of a delay driver FZ2;

• in FIG. 15 is a functional diagram of a delay driver FZ3;

• in FIG. 16 presents table 1, the input digital information;

• in FIG. 17 presents table 2-1 and table 2-2, digital output;

• in FIG. 18 presents table 3, the formation of the mass range;

• in FIG. 19 shows table 4, the calculation of the delay T1 according to the automation algorithms in accordance with priority .;

• in FIG. 20 shows the distribution of information in an SPI exchange package;

• in FIG. 21 shows the distribution of information in an SPI exchange frame;

• in FIG. 22 shows the structure of the information in the frame coming from the controller to the MK of the normal operating mode;

• in FIG. 23 shows the structure of information in the frame coming from the MC to the controller of the normal operating mode;

• in FIG. 24 shows the algorithm of operation of dT counters;

• in FIG. 25 presents a continuation of the algorithm for the operation of dT counters.

The indicated advantages of the inventive electronic device for the ejection seat for an airplane over the prototype are achieved due to the fact that the electronic device of the ejection seat for an airplane contains a processor (CPU) 1, RAM 2, ROM (ROM) 3, switch 4 (Time Zero Switch) , clock 5 (clock), timer 6, switch 7 (Power switch), first 8, second 9 and third 10 pressure sensors (PS1-PS3), and the outputs of switch 4, clock 5 and timer 6 are connected to the first, second and third the inputs of the processor 1, the first, second and third outputs of which are connected to the inputs of hours 5, measure 6 and switch 7, and the group of inputs and outputs of the processor 1 is connected to the group of inputs and outputs of the RAM 2, the group of inputs of which is connected to the group of outputs of the processor 1, the group of inputs of which is connected to the group of outputs of the ROM 3, the controller MCO 11, controller 12 are additionally introduced (Monitoring device), group of optocouplers 13, fourth 14 pressure sensors (PS4), first 15, second 16, third 17 and fourth 18 optocouplers, first 19, second 20 and third 21 power supply reset circuits, first 22, second 23, third 24 and fourth 25 generators, first 26 and second 27 nodes ZBV (shutter timed go), the first 28 and second 29 elements AND, element OR 30, key 31, the output of which is the output 32 of the AECC, the first 33 group of inputs of which is connected to the group of optocouplers 13, the group of outputs 34 of which is connected to the first groups of inputs of the controller 12, the first 26 and the second 27 nodes ZBV (time-lag shutter), the outputs of which are connected to the first and second inputs of the OR element 30, the output of which is connected to the input of the key 31, and the second 35 group of inputs of the ECMC is connected to the first group of inputs of the controller MCO 11 and the second group of inputs of the controller 12 first 36 output connected to the first inputs of the first 28 and second 29 AND elements, the outputs of which are connected to the third and fourth inputs of the OR element 30, and the first input of the first node ZBV (shutter bar) 26 is connected to the output 37 of the first generator 22, the output 38 of the second generator 23 is connected to the first input of the second node ZBV (latch shutter) 27, the second input of which is connected to the output 39 of the second power reset circuit 20, the outputs 40, 41 of the first 19 and third 21 power reset circuits are connected to the second input of the first node ZBV (latch shutter) 26 and with the fourth the input of the processor 1 and the first input of the controller 12, respectively, the bus SPI 42 of which is connected to the bus SPI of the processor 1, the first group of outputs of which is connected to the group of inputs of the RAM 2, and the first input 43 of the EECC is connected to the first, second and fifth inputs of the controller MCO 11, controller 12 and processor 1, and the third input of the first node ZBV (time-lag shutter) 26 is connected to the output 44 of the first optocoupler 15, the input of which is connected to the output of the first pressure sensor 8, the output of the second pressure sensor 9 is connected to the input of the second optocoupler 16, the output of which 45connected to the third inputs of the controller 12 and the second node ZBV (valve shutter) 27 and the sixth input of the processor 1, and the fourth input of the first node ZBV (valve shutter) 26 is connected to the output 46 of the third optocoupler 17, the input of which is connected to the output of the third pressure sensor 10 moreover, the output of the fourth pressure sensor 14 is connected to the input of the fourth optocoupler 18, the output of which 47 is connected to the fourth input of the second node ZBV (time-latch shutter) 27, with the fourth input of the controller 12 and with the seventh input of the processor 1, the processor bus 48 is connected with the controller MCO 11, and the fifth input of the controller 12 is connected to the output 49 of the third generator 24, the output of the switch 7 is connected to the second inputs of the first 28 and second 29 And elements, and the output 50 of the fourth generator 25 is connected to the eighth input of the processor 1.

The controller (Monitoring device) 12 contains an MCO monitor 51, a processor (CPU) 52, ROM 53, an arithmetic logic unit (ALU) 54, a constant node (UCONST) 55, a parameter selection node 56, an ejection signal generation section 57, an SPI bus 42 which is connected to the controller's SPI bus 12, output 32 (parachute ejection signal) of which is connected to the first output of the ejection signal generation unit 57, the first 58 group of outputs of which are connected to the first group of inputs ALU 54, the first, second, third, fourth, fifth, sixth output groups of which are connected to the first, second, tr the fifth, fourth, fifth and sixth groups of inputs of the processor 52, the information group of inputs of which is connected to the group of outputs of the ROM 53, the group of inputs of which is connected to the address group of outputs of the processor 52, the first, second, third groups of outputs of which are connected to the second, third and fourth groups ALU 54, the seventh, eighth, ninth, tenth, eleventh, twelfth groups of outputs are connected to the seventh, eighth, ninth, tenth, eleventh, twelfth groups of inputs of the processor 52, fourth 59, fifth 60 and sixth 61 groups the outputs of which are connected to the first, second and third groups of inputs of the parameter selection node 56, the first 62, second 63 and third 64 groups of outputs of which are connected to the fifth, sixth and seventh groups of inputs ALU 54, the thirteenth 65 group of outputs of which is connected to the first group of inputs of the node the formation of the ejection signal 57, the second 66 group of outputs of which is connected to the eighth group of inputs ALU 54, the ninth group of the inputs of which is connected to the second group of inputs of the site of the formation of the ejection signal 57 and the seventh 67 group of outputs processor 52, the thirteenth group of inputs of which is connected to the third 68 group of outputs of the ejection signal generating unit 57, the fourth 69 group of outputs of which is connected to the fourth group of inputs of the parameter selection unit 56, the fourth 70 group of outputs of which is connected to the third group of inputs of the ejection signal generating unit 57, the fifth 71 group of outputs of which is connected to the fifth group of inputs of the node for selecting parameters 56, the sixth group of inputs of which is connected to the fourth group of inputs of the node for generating a signal ultimately 57 and with the output 72 of the MCO 51 monitor, the group of inputs of which is connected to the second 35 group of inputs of the controller 12, the second 43 input of which is connected to the input of the MCO 51 monitor, clock 49 and reset 41 inputs of which are connected to the clock and reset inputs of the processor 52, ALU 54, the ejection signal generation section 57, the parameter selection section 56 and the controller 12, the first 34 group of inputs of which is connected to the fifth group of inputs of the ejection signal generation section 57, the second 73 output of which is connected to the input of the processor 52, fourteen the fifth group of inputs is connected to the seventh group of inputs of the parameter selection node 56, to the sixth group of inputs of the ejection signal generation section 57 and to the output 74 of the constant node (UCONST) 55, and the eighth 75 and ninth 76 groups of outputs of the processor 52 are connected to the seventh and eighth groups the input node of the formation of the ejection signal 57, the first and second inputs of which are the third 45 and fourth 47 inputs of the controller 12.

The ejection signal generation unit 57 comprises an SPI_SLAVE 77 node, an SPI_STATE node 78, a CMND node 79, a MASK node 80, an I element 81, a control unit 82 and a combinational circuit 83, the output group 84 of which is connected to the first input group of the SPI_SLAVE 77 node, the output group 85 which is connected to the first group of inputs of the CMND 79 node, the output group of which is the second 66 group of outputs of the ejection signal generating section 57, the SPI bus 42 of which is connected to the SPI bus of the SPI_SLAVE 77 node, the output 86 of which is connected to the first inputs of the SPI_STATE 78 and CMND 79 nodes, output 190 of which is connected n with the first input of AND element 81, the output of which is the first output 32 of the ejection signal generation unit 57, the second output 73 of which is connected to the first output of the control unit 82, the second output of which 87 is connected to the second inputs of the SPI_STATE 78 and CMND 79 nodes, the second group of inputs which is connected to the fifth group of inputs of the combinational circuit 83, with the first group of outputs 88 of the SPI_STATE 78 node, the second 89 group of outputs of which is connected to the first group of inputs of the control unit 82 and the third input of CMND 79, the third and fourth groups of inputs of which are united with the seventh 75 and eighth 76 groups of inputs of the ejection signal generating unit 57, the first 58 group of outputs of which is connected to the second group of outputs of the control unit 82, the third and fourth groups of outputs which are connected to the fifth 71 and fourth 69 groups of outputs of the ejection signal generating unit 57, the first 65 group of inputs of which is connected to the first group of inputs of the combinational circuit 83, with the fifth and first groups of inputs of the nodes CMND 79 and MASK 80, the group of outputs 90 of which is connected to the second and first groups of inputs of the unit line 82 and SPI_STATE 78, the second group of inputs of which is connected to the third and sixth groups of inputs of the control nodes 82 and CMND 79 and is the second 67 group of inputs of the ejection signal generation unit 57, respectively, the fifth 34 group of inputs of which is connected to the second group of inputs of the MASK 80 and with the fourth group of inputs of the control unit 82, the fifth 91 group of outputs of which is connected to the second group of inputs of the combinational circuit 83, the third group of inputs of which is the fourth 72 group of inputs of the catapultro signal generating unit 57 and is connected to the third input of the SPI_STATE 78 node and the fifth group of inputs of the control unit 82, the first group of outputs of which is the third 68 group of outputs of the ejection signal generation unit 57, the third 70 group of inputs of which is connected to the seventh group of inputs of the control unit 82, the sixth 74 group the inputs of the ejection signal generating section 57 is connected to the fourth group of inputs of the combinational circuit 83, with the third groups of inputs of the MASK 80 and SPI_STATE 78 nodes, with the second group of inputs of the SPI_SLAVE 77 node, with the seventh group of inputs of the CMND 79 node and a third group of inputs of the control unit 82, the first input of which is connected to the first output 92 of the MASK 80 node, the second 130 output of which is connected to the second input of the AND element 81, the clock 49 and the reset 41 inputs of the ejection signal generating section 57 connected to the clock and reset inputs of the node SPI_SLAVE 77, SPI_STATE 78, control 82, CMND 79 and MASK 80, the first and second inputs of which are the first 45 and second 47 inputs of the ejection signal generation unit 57.

The SPI_SLAVE 77 node contains the first register 93, the second register 94, the third register 95 and the fourth register 96, the first trigger 97, the second trigger 98, the third trigger 99, the fourth trigger 100, the fifth trigger 101 and the sixth trigger 102, the adder 103, the first multiplexer 104 the second multiplexer 105, the third group of multiplexers 106, the fourth multiplexer 107, the fifth group of multiplexers 108 and the sixth group of multiplexers 109, the first element And 110, the second element And 111, the third element And 112, the fourth element And 113, the fifth element And 114, the sixth element And 115, the seventh element And 116 and the eighth element AND, 117 element OR 118 and element 3-OR 119, the output of which is connected to the information input of the sixth trigger 102, the output of which is the fourth signal of the SPI bus 42, the first, second and third signals of which are connected to the information input of the first trigger 97, with the first the input of the first multiplexer 104, with the first input of the second multiplexer 105, respectively, the output of which is connected to the information input of the fourth trigger 100, the output of which is the fifteenth bit of the first group of inputs of the sixth group of multiplexers 109, and from zero the 14th to the 14th bits of which are connected to the group of outputs of the fourth register 96 and are the group of outputs 85 of the SPI_SLAVE 77 node, the output of which 86 is connected to the output of the fifth trigger 101, whose inverse enable input is connected to the inverse enable input of the fourth register 96 and the output of the sixth element And 115, the first inverse input of which is connected to the input of the adder 103 and the output of the second element And 111, the direct input of which is connected to the output of the second trigger 98, with the inverse input of the third element And 112 and the first input of the fourth mult Iplexer 107, the output of which is connected to the information input of the third trigger 99, the output of which is connected to the inverse input of the second element And 111 and the direct input of the third element And 112, the output of which is connected to the first inverse input of the first element And 110, the output of which is connected to the inverse enable input the sixth trigger 102 and the first input of the OR element 118, the output of which is connected to the inverse enable input of the second register 94, the group of outputs of which is connected to the group of inputs of the third group of multiplexers 106, and the fifteenth the charge is connected to the first input of the AND-OR element 119, the second input of which is connected to the output of the fifth element AND 114, the first inverse of which is connected to the inverse input of the fourth element AND 113, with the third input of the element 3-OR 119, controlling the inputs of the first 104, second 105, fourth 107, fifth 108 and sixth 109 groups of multiplexers, with a second inverse input of the sixth element And 115, with an inverse input of the seventh element And 116, with a permitting input of the first register 93, with a second input of the element OR 118, with the second inverse input of the first element And 110 and the output of the first trigger 97, the clock input of which is connected to the clock inputs of the second 98, third 99, fourth 100, fifth 101 and sixth 102 triggers, with the clock inputs of the first 93, second 94, third 95 and fourth 96 registers and with the clock input 49 nodes SPI_SLAVE 77, the reset input 41 of which is connected to the inverse, installation inputs of the first 97, second 98, third 99, fourth 100 and sixth 102 triggers and with inverse reset inputs of the first 93, second 94, third 95 and fourth 96 registers and fifth trigger 101, whose information input is with it is single with the output of the seventh element 116, the first, second, third and fourth inputs of which are connected to the inverse group of inputs of the eighth element And 117, to the group of inputs of the adder 103 and to the group of outputs of the third register 95, the information group of inputs of which is connected to the group of outputs of the fifth group of multiplexers 108, the first group of inputs of which is connected to the group of outputs of the adder 103, the second group of inputs of the fifth group of multiplexers 108 is connected to the group of inputs of the sixth group of multiplexers 109 (constant 0) and with the group of inputs CONST 74 I (constant 1) is connected to the second inputs of the first 104, second 105 and fourth 107 multiplexers and to the fourth input of the 3-OR 119 element, the fifth input of which is connected to the output of the fourth AND element 113, the direct input of which is connected to the second inverse input of the fifth AND element 114, with the output of the eighth element And 117 and the control input of the third group of multiplexers 106, the second group of inputs of which is connected to the group of outputs of the first register 93, and the fifteenth digit of which is connected to the sixth input of the element 3-OR 119, and the group of outputs of the second group of multiplexers 106 is connected to the information group of inputs of the second register 94, the output of the first multiplexer 104 is connected to the information input of the second trigger 98, the group of outputs of the sixth group of multiplexers 109 is connected to the information group of inputs of the fourth register 96, the first group of inputs 84 of the SPI_SLAVE 77 node is connected to the information group of inputs of the first register 93.

Node SPI_STATE 78 contains the first trigger 120, the second trigger 121, the adder 122, the register 123, the group of elements 3-OR 124, the first element OR 125, the second element OR 126, the third element OR 127, the fourth element OR 128, the first element AND 129, the second element And 130, the third element And 131, the fourth element And 132, the fifth element And 133, the sixth element And 134, the seventh element And 135, the eighth element And 136, the ninth element And 137 and the tenth element And 138, the output of which is connected to the first the input of the fourth element OR 128, the output of which is connected to the inverse input of the first element And 129 and is in the second signal of the second group of outputs 89 of the SPI_STATE 78 node, the first signal of which is connected to the information input of the second trigger 121 and the output of the fifth AND 133 element, the direct input of which is connected to the output of the first OR 125 element, the first input of which is connected to the first inverse input of the fourth And element 132 , with the first input of the second OR element 126 and is the first signal of the fourth group of inputs 72 of the SPI_STATE 78 node, the first group of outputs 88 of which are connected to the group of inputs of the adder 122 and the group of outputs of the register 123, the information group of inputs to The second input is connected to the second inverse input of the fourth element AND 132 and the output of the second element AND 130, which is connected to the group of outputs of the group of elements 3-OR 124, the first allowing input of which is connected to the inverse input of the seventh element AND 135 and the output of the second element OR 126. the direct and inverse inputs of which are the second and third signals of the first group of inputs 90 of the SPI_STATE 78 node, the first signal of which is connected to the second input of the first OR 125 element, and the second group of inputs 67 of the SPI_STATE 78 node is connected in the following way: the left discharge is connected to the direct input of the ninth element And 137, the first discharge is connected to the first inverse input of the tenth element And 138, the second discharge is connected to the first and second inverse inputs of the ninth 137 and the tenth element And 138, the third discharge is connected to the second inverse and direct inputs of the ninth 137 and the tenth 138 AND elements, respectively, the output of the ninth AND element 137 is connected to the second input of the fourth OR element 128, and the first input 86 of the SPI_STATE 78 node is connected to the information input of the first trigger 120 and the inverse input of the third ele Enta AND 131, the output of which is connected to the direct input of the seventh element And 135, the third inverse input of the fourth element And 132 and the first input of the sixth element And 134, the output of which is connected to the second enable input of the group of elements 3-OR 124, the first (000) and second (111) the information groups of which are the third group of inputs 74 of the SPI_STATE 78 node, the second input of which 87 is connected to the inverse input of the fifth 133 and the direct input of the first 129 elements And, accordingly, the output of which is connected to the inverse enable input of the second trigger 121, the output of which connected to the second input of the sixth element And 134 and the inverse input of the eighth element And 136, the output of which is connected to the enable input of the adder 122 and the first input of the third element OR 127, the output of which is connected to the third enable input of the group of elements 3-OR 124, the third information group the inputs of which are connected to the group of outputs of the adder 122, the clock 49 and the reset 41 inputs of the SPI_STATE 78 node are connected to the clock and reset inputs of the first 120 and second 121 triggers and register 123, the output of the first trigger 120 is connected to direct input third AND house 131, wherein the fourth element output of AND 132 is connected to a second input of the third OR gate 127, the output of the seventh AND gate 135 is connected to the direct input of the eighth AND gate 136.

The control node 82 contains a node for comparing stabilization parameters KK 139, register 140, first trigger 141, second trigger 142, third trigger 143, fourth trigger 144, fifth trigger 145, sixth trigger 146, seventh trigger 147, eighth trigger 148, ninth trigger 149, adder 150, combinational circuit 151, first element And 152, second element And 153, third element And 154, fourth element And 155, fifth element And 156, sixth element And 157, seventh element And 158, eighth element And 159, ninth element And 160, tenth element AND 161, first element OR 162, second element OR 163, third element tent OR 164, fourth element OR 165, fifth element OR 166, sixth element OR 167, the output of which is connected to the information input of the ninth trigger 149, the output of which is connected to the first input of the second element OR 163 and is the first signal of the fifth group of outputs 91 of the control unit 82 , the second and third signals of which are connected to the outputs of the eighth 148 and sixth 146 triggers, the information input of the sixth trigger 146 is connected to the inverse input of the ninth element And 160 and the output of the second trigger 142, the information input of which is connected to the output of the first OR element 162, the inverse inputs of which are the first and second signals of the fifth group of inputs 34 of the control unit 82, the third, fourth, fifth and sixth signals of which are connected to the inverse inputs of the second element And 153 and the sixth element OR 167, and the output of the second element And 153 is connected with the information input of the first trigger 141, the output of which is connected to the direct input of the ninth element And 160, the output of which is connected to the information input of the eighth trigger 148, the enable input of which is connected to the enable input of the ninth trigger 14 9, with an inverse enable input of the sixth flip-flop 146 and is the first input 92 of the control unit 82, the first group of outputs 68 of which is connected to the group of outputs of the register 140, the information group of inputs of which is connected to the group of outputs of the combinational circuit 151, the group of inputs of which is the fourth group of inputs 72 control unit 82, the second signal of which is connected to the information input of the third trigger 143, and the first signal is connected to the first inputs of the fifth 166 and third 164 OR elements and the third AND element 154, the output of which is connected n with an enabling input of the third trigger 143, the output of which is connected to the second input of the second OR element 163, the output of which is the first signal of the second group of outputs 58, the second signal of which is connected to the second inputs of the third 164 and fifth 166 OR elements, with the first inverse input of the first element And 152, with the inverse input of the fifth element And 156, with the first input of the combinational circuit 151, with the second group of inputs 90 of the control unit 82 and is the first signal of the fourth group of outputs 69 of the control unit 82, the third signal of the second group outputs 58 of the control unit 82 is connected to the output of the fifth trigger 145, the information input of which is connected to the direct input of the eighth element And 159, with inverse inputs of the sixth 157, seventh 158 and tenth 161 And elements, with the second inverse input of the first element And 152, with the first input the adder 150, with the output of the seventh trigger 147, is the second signal of the fourth group of outputs 69 and the second output 87 of the control unit 82, the third group of outputs 71 of which are connected to the second group of inputs of the combinational circuit 151 and the group of outputs of the parameter comparison node stabilization ditch KK 139, the first group of inputs of which is connected to the third group of inputs of the combinational circuit 151 and is the fifth group of inputs 74 of the control unit 82, the first group of inputs 89 of which is connected to the first inputs of the fourth OR element 165 and the fifth AND element 156, the output of which is connected to the second input of the fourth element OR 165, the output of which is connected to the second input of the adder 150, the output of which is connected to the information input of the seventh trigger 147, the inverse output of which is connected to the second input of the fifth element And 156, there is a second group of inputs 67 of the control unit 82 is connected to the first and second inverse inputs and the direct input of the fourth element And 155, the output of which is connected to the inverse input of the eighth element And 159, the output of which is connected to the inverse enable input of the fifth trigger 145, the clock and reset inputs of which connected to the clock and reset inputs of the first 141, second 142, third 143, fourth 144, sixth 146, seventh 147, eighth 148, ninth 149 triggers, register 140 and are clock 49 and reset 41 inputs of the control unit 82, the sixth group and the inputs 70 of which are connected to the second group of inputs of the node for comparing stabilization parameters KK 139, the output of the first element And 152 connected to the second input of the third element And 154, the output of the third element OR 164 connected to the second inverse input of the seventh element And 158 and the direct input of the sixth element And 157, the output of which is connected to the information input of the fourth trigger 144, whose inverse enable input is connected to the output of the seventh element And 158, and the output is the first output 73 of the control unit 82, and the output of the fifth element LI 166 is connected to the direct input of the tenth AND gate 161, whose output is connected with a resolution register entry 140.

The signal conditioning unit CMND 79 contains a trigger 168, a first register 169, a second register 170, a first adder 171, a second adder 172, a first comparator 173, a second comparator 174, a third comparator 175, a first group of multiplexers 176, a second group of multiplexers 177, element 3I- OR 178, the first element And 179, the second element And 180, the third element And 181, the fourth element And 182, the fifth element And 183, the sixth element And 184, the seventh element And 185, the eighth element And 186, the first element OR 187, the second element OR 188, the third element OR 189, the output of which is connected with inverse resolution the input of the second register 170, the group of outputs of which is the first group of outputs of the group of outputs 66 of the signal conditioning unit CMND 79, the second group of outputs of which is connected to the group of outputs of the first register 169, the information inputs of which are connected to the group of outputs of the first group of multiplexers 176, the first group of inputs of which connected to the first groups of inputs of the second 174 and third 175 comparators, with the first group of inputs of the second group of multiplexers 177 and is the seventh group of inputs 74 of the signal conditioning unit CMND 79, the first the output 190 of which is connected to the first input of the 3I-OR element 178 and the output of the first trigger 168, the information input of which is connected to the output of the 3I-OR 178 element, the second input of which is connected to the "power", the third input of which is connected to the "case", the first and the second enable inputs of which are connected to the outputs of the first 187 and second 188 OR elements, the first input of the second OR element 188 is connected to the output of the sixth element AND 184, the inverse input of which is connected to the output of the second comparator 174 and the first input of the fourth element And 182, the output of which connected to the first input of the first element OR 187, the second input of which is connected to the output of the fifth element And 183, the first input of which is connected to the direct input of the seventh element And 185 and the output of the third element And 181, the first input of which is connected to the third inverse enable input of the element 3I- OR 178, the direct input of the second element And 180 and is the first input 86 of the signal conditioning unit CMND 79, the first group of inputs 85 of which is connected to the direct group of inputs of the first adder 171, with the first group of inputs of the first comparator 173 and with inverse uppa of the inputs of the second adder 172, the group of outputs of which is connected to the second group of inputs of the third comparator 175, the output of which is connected to the second input of the fifth element And 183 and the inverse input of the seventh element And 185, the output of which is connected to the second input of the second element OR 188, the second group the inputs 88 of the signal conditioning unit CMND 79 is connected to the first, second and third inverse inputs of the first element And 179, the output of which is connected to the enable input of the trigger 168, the clock and reset inputs of which are connected to the clock and the fault inputs of the first 169 and second 170 registers and are clock 49 and fault 41 inputs of the signal conditioning unit CMND 79, the third group of inputs 75 of which is connected to the second group of inputs of the first group of multiplexers 176, the enable input of which is connected to the enable input of the second group of multiplexers 177 and is the first signal of the sixth group of inputs 67 of the signal conditioning unit CMND 79, the fourth group of inputs 76 of which is connected to the second group of inputs of the second group of multiplexers 177, the group of outputs of which is connected to info by the input inputs of the second register 170, the fifth group of inputs 65 of the signal conditioning unit CMND 79 is connected to the direct and inverse groups of inputs of the second 172 and first 171 adders, respectively, and to the second group of inputs of the first comparator 173, the output of which is connected to the second input of the third element And 181 and the inverse input of the second element And 180, the output of which is connected to the direct input of the sixth element And 184 and the second input of the fourth element And 182, the second input 87 of the signal conditioning unit CMND 79 is connected to the inverse input of the third element OR 1 89 and a direct input of the eighth element AND 186, the output of which is connected to the direct input of the third element OR 189 and with an inverse enable input of the first register 169, the third input 89 of the signal conditioning unit CMND 79 is connected to the inverse input of the eighth element And 186, and the group of outputs of the first adder 171 is connected to the second group of inputs of the second comparator 174, and the enabling inputs of the first 171 and second 172 adders are connected to the "power".

The signal conditioning unit MASK 80 contains a first trigger 191, a second trigger 192, a third trigger 193, a fourth trigger 194, a fifth trigger 195, a sixth trigger 196, a seventh trigger 197, an eighth trigger 198, a ninth trigger 199, a first register 200, a second register 201, first adder 202, second adder 203, first comparison circuit 204, second comparison circuit 205, first element OR 206, second element OR 207, third element OR 208, fourth element OR 209, first element AND 210, second element AND 211, third element And 212, the fourth element And 213, the output of which is connected to a permit the input of the ninth trigger 199, the output 214 of which is the second output of the signal conditioning unit MASK 80, the group of outputs 90 of which consists of three signals: the first signal is connected to the output of the fifth trigger 195, the second signal is connected to the information and enable inputs of the fifth 195 and eighth 198 triggers and the output of the second trigger 192, the third signal is connected to the first inputs of the first 210 and fourth 213 And elements, with a direct input of the second element And 211 and the output of the eighth trigger 198, the information input of which is connected to the information input w first trigger 196 and the output of the seventh trigger 197, the enable input of which is connected to the output of the fourth trigger 194 and is the first output 92 of the signal conditioning unit MASK 80, the first group of inputs 65 of which is connected to the first group of inputs of the second comparison circuit 205, the output of which is connected to the second input the fourth element And 213 and the inverse input of the first element And 210, the output of which is connected to the enable input of the first adder 202, the group of outputs of which is connected to the information group of inputs of the first register 200, the group of outputs which is connected to the second group of inputs of the second comparison circuit 205 and the group of inputs of the first adder 202, the second group of inputs 34 of the signal conditioning unit MASK 80 connected to the inverse inputs of the second 207, third 208 and fourth 209 OR elements, the outputs of which are connected to the information inputs of the second 192 , the third 193 and the fourth 194 triggers, respectively, whose clock and reset inputs are connected to the clock and reset inputs of the first 191, fifth 195, sixth 196, seventh 197, eighth 198 and ninth 199 triggers, with clock and sat the axial inputs of the first 200 and second 201 registers and are clock 49 and reset 41 inputs of the signal conditioning unit MASK 80, the third group of inputs 74 of which are connected to the first group of inputs of the first comparison circuit 204, the output of which is connected to the inverse input of the second element And 211 and the first input the third element And 212, the output of which is connected to the second input of the first element And 210 and the third input of the fourth element And 213, the first 45 and second 47 inputs of the signal conditioning unit MASK 80 connected to the first inverse and second inverse inputs the first element OR 206, the output of which is connected to the information input of the first trigger 191, the output of which is connected to the information input of the ninth 199 trigger, the output of the third trigger 193 is connected to the enable input of the sixth trigger 196, the output of which is connected to the second input of the third element And 212, and the group the outputs of the second register 201 is connected to the second group of inputs of the first comparison circuit 204 and the group of inputs of the second adder 203, the group of outputs of which is connected to the information group of inputs of the second register 201, and allowing the first input with the output of the second element And 211, the information input of the seventh trigger 197 is connected to the "power".

The parameter selection node 56 comprises a counter node 215, a first register 216, a second register 217, a third register 218, a fourth register 219, a fifth register 220, a sixth register 221, a seventh register 222, an eighth register 223, a ninth register 224, a first combiner circuit 225, the second combinational circuit 226, the third combinational circuit 227, the fourth combinational circuit 228, the fifth combinational circuit 229, the sixth combinational circuit 30, the seventh combinational circuit 231, the adder 232, the group of multiplexers 233, the first element And 234, the second element And 235, the second element And 235, the third element And 236 even the wound element AND 237, the fifth element AND 238, the OR element 239, the output of which is connected to the inverse input of the adder 232, the group of outputs of which is connected to the first group of inputs of the group of multiplexers 233, the group of outputs of which is connected to the information group of the fifth register 220, the group of outputs of which is connected with the group of inputs of the fifth element And 238 and with the group of inputs of the adder 232, the third group of outputs 64 of the node parameter selection 56 is connected to the first group of outputs of the node counters 215, the second group of outputs of which is the fourth group of outputs 70 of the parameter selection node 56, the first group of outputs 62 is connected to the group of outputs of the first register 216, the first and second groups of inputs of which are connected to the first 59 and second 60 groups of inputs of the parameter selection node 56, the second group of outputs 63 of which consists of groups of outputs from the third 218, fourth 219, seventh 222 and ninth registers 224, the third group of inputs 61 of the parameter selection node 56 is connected to the group of inputs of the first combinational circuit 225, the first, second and third outputs of which are connected to the first, second and third inputs of the first register 216, the first signal of the fourth group of inputs 69 of the parameter selection node 56 is connected to the first inputs of the second 226, third 227, fifth 229 and seventh 231 combinational circuits, with inverse inputs of the fourth 228 and sixth 230 combinational circuits and the first input of the counter node 215, the second input of which is connected to second inputs of the second 226, third 227, fifth 229 and seventh 231 combinational circuits, with direct and second inverse inputs of the fourth combinational circuit 228, with direct input of the sixth combinational circuit 230, with inverse inputs of the first 234, third 236 and four of a solid 237 AND element, with the first input of the OR element 239 and is the second signal of the fourth group of inputs 69 of the parameter selection node 56, the fifth group of inputs 73 of which is connected to the first groups of inputs of the third 227 and seventh 231 combinational circuits, the group of outputs and the output of the seventh combinational circuit 231 connected to the group of inputs and the input of the ninth register 224, the sixth group of inputs 72 of the parameter selection node 56 is connected to the first groups of inputs of the second 226, fourth 228, fifth 229 and sixth 230 by combinational circuits and the second register 217, sixth Istrom 221 and eighth register 223, with second groups of inputs of the third 227 and seventh 231 combinational circuits, with the first group of inputs of the counter node 215, a group of signals F1_V and signals F1_Vd, F1_Rec of the sixth group of inputs are connected to the information input of the third register 218, the first and second inputs the second 235 element And and the direct input of the third element And 236, respectively, the seventh group of inputs 74 of the parameter selection node 56 is connected to the second groups of inputs of the group of multiplexers 233 and the counter node 215, the clock and reset inputs of which are connected to Actual and fault inputs of the first 216, second 217, third 218, fourth 219, fifth 220, sixth 221, seventh 222, eighth 223, ninth 224 registers and are clock 49 and fault 41 inputs of the parameter selection node 56, the first, second and third the outputs of the second combinational circuit 226 are connected to the first, second and third inputs of the second register 217, the first group of outputs of which is connected to the third group of inputs of the third combinational circuit 227, the second and third groups of inputs of which are connected to the second and third groups of outputs of the second histra 217, the group of outputs and the output of the third combinational circuit 227 being connected to the group of inputs and the input of the fourth register 219, the output of the second element And 235 connected to the direct inputs of the fourth 237 and the first 234 elements And, the output of which is connected to the enabling input of the third register 218, the output the third element And 236 is connected to the second input of the OR element 239, the inverse of which is connected to the output of the fifth element And 238, the first, second and third outputs of the fourth combination circuit 228 are connected to the first, second and third inputs of the sixth p histra 221, the first, second and third groups of outputs of which are connected to the second, third and fourth groups of inputs of the fifth combination circuit 229, the group of outputs and the output of which are connected to the group of inputs and input of the seventh register 222, the first, second and third outputs of the sixth combination circuit 230 connected to the first, second and third inputs of the eighth register 223, the first, second and third groups of outputs of which are connected to the third, fourth and fifth groups of inputs of the seventh combination circuit 231, and the output of the fourth element And 237 is connected the control input of the group of multiplexers 233.

The counter assembly 215 comprises a first combinational circuit 240, a second combinational circuit 241, a first adder 242, a second adder 243, a third adder 244, a fourth adder 245, a fifth adder 246, a sixth adder 247, a seventh adder 248, a first group of multiplexers 249, a second group of multiplexers 250, the third group of multiplexers 251, the fourth group of multiplexers 252, the fifth group of multiplexers 253, the sixth group of multiplexers 254, the first register 255, the second register 256, the third register 257, the fourth register 258, the fifth register 259, the sixth register 260, gray the seventh register 261, the trigger 262 and the element And 263, the output of which is connected to the information input of the trigger 262, the output of which is the first signal of the first group of outputs 64 of the counter node 215, the first and second groups of outputs of which are connected to the group of inputs of the element And 263, with a group of inputs of the seventh adder 248, with the group of outputs of the seventh register 261 and the information group of inputs of the seventh register 261, with the group of outputs of the second combination circuit 241, respectively, the output of which is connected to the enable input of the seventh register 261 and with an inverse input ohm of the seventh adder 248, the output of which is connected to the input of the second combinational circuit 241, the first group of inputs of which is connected to the group of inputs of the first combinational circuit 240 and is the first group of inputs 72 of the counter node 215, the second group of outputs of which is connected to the second, third, fourth, fifth , the sixth and seventh groups of inputs of the second combinational circuit 241, with groups of inputs of the first 242, second 243, third 244, fourth 245, fifth 246 and sixth 247 adders and with groups of outputs of the first 255, second 256, third 257, fourth 258, fifth 259th and sixth 260 registers, the information inputs of which are connected to the output groups of the first 249, second 250, third 251, fourth 252, fifth 253 and sixth 254 multiplex groups, the first input groups of which are interconnected and are the second group of inputs 74 of the counter node 215 , the first and second inputs of which are connected to the first and second inputs of the first combinational circuit 240, the first, second, third, fourth, fifth and sixth outputs of which are connected to the inverse inputs of the first 242, second 243, third 244, fourth 245, fifth 246 and sixth 247 s ummators whose output groups are connected to the second input groups of the first 249, second 250, third 251, fourth 252, fifth 253 and sixth 254 multiplexer groups, the control inputs of which are connected to the seventh, eighth, ninth, tenth, eleventh and twelfth outputs of the first combinational circuit 240, respectively, with the clock 49 and the reset 41 inputs of the counter node 215 connected to the clock and inverse reset inputs of the first 255, second 256, third 257, fourth 258, fifth 259, sixth 260, seventh 261 registers and trigger 262.

The ZBV (bar-time shutter) node 26 (27) contains the first counter 264, the second counter 265, the third counter 266, the first trigger 267, the second trigger 268, the third trigger 269, the fourth trigger 270, the fifth trigger 271, the sixth trigger 272, the seventh trigger 273 , eighth trigger 274, ninth trigger 275, tenth trigger 276, first delay shaper FZ1 277, second delay shaper FZ1 278, first delay shaper FZ2 279, second delay shaper FZ2 280, third delay shaper FZ2 281, fourth delay shaper FZ2 282, fourth shaper delays FZ3 283, first eleme t OR 284, second element OR 285, third element OR 286, fourth element OR 287, fifth element OR 288, sixth element OR 289, seventh element OR 290, first element AND 291, second element AND 292, third element And 293, fourth element And 294, fifth element And 295, sixth element And 296, the output of which is the output 297 of the ZBV 26 node, the first 34 group of inputs of which are connected to the direct input of the first element OR 285 (the first signal SM), with the direct input of the second element OR 285 ( second signal DX), with the eighth input of the second delay driver FZ1 278 (third signal SH_S), with direct the course of the first element And 291, with the first input of the second element And 292, with the eighth inputs of the third 281 and fourth 282 formers delay FZ2 (fourth signal B_M), with inverse and second input of the first 291 and second 292 elements And (fifth signal M_M), output the first element And 291 is connected to the eighth inputs of the first 277 and second 280 delay drivers FZ1 and FZ2, the output of the second element And 292 is connected to the eighth inputs of the first delay driver FZ2 279 and the delay driver FZ3 283, the input groups of which are connected to the input groups of the first 277 and second 2 78 delay shapers FZ1, second 280, third 281 and fourth 282 delay shapers FZ2 and a group of outputs of the third counter 266, the clock input of which is connected to the first inputs of the first 277 and second 278 delay shapers FZ1, the first 279, second 280, third 281 and fourth 282 delay shapers FZ2 and delay shaper FZ3 283, with the clock input of the second counter 265 and the output of the first counter 264, the clock input of which is connected to the inverse clock input of the eighth trigger 274 and is the first input 49 of the ZBV 26 node, the first input is sixth And element 296 is connected to the reset input of the third counter 266 and the output of the tenth flip-flop 276, whose inverse clock input is connected to the output of the seventh OR element 290, whose direct input is connected to the output of the ninth flip-flop 275, the information input of which is connected to the “power”, with the enabling input the third counter 266, with information inputs of the seventh 273 and tenth 276 triggers, the inverse dump input of which is connected to the inverse reset inputs of the seventh 273, eighth 274 and ninth 275 triggers, with inverse inputs of the first 284 and a second 285 OR element, with a reset input of the first counter 264 and is the second input 41 of the ZBV 26 node, the third input of which 44 is connected to the first inverse input of the fourth AND element 294, the output of which is connected to the first input of the sixth OR element 289, the output of which is connected with the second input of the sixth element And 296, and the fourth input 46 of the node ZBV 26 is connected to the inverse input of the fifth element And 295 and with the second inverse input of the fourth element And 294, the direct input of which is connected to the output of the fourth element OR 287, the first, second and third input whose odes are connected to the outputs of the first delay shaper FZ1 277, the first 279 and third 281 delay shapers FZ2, respectively, the second 280 and fourth 282 delay shapers FZ2 and the delay shaper FZ3 283 are connected to the inputs of the fifth element OR 288, the output of which is connected to the direct input of the fifth element And 295, the output of which is connected to the second input of the sixth OR element 289, the third input of which is connected to the output of the second delay driver FZ1 278, the second output of the first counter 264 connected to the clock inputs of the first 267 , second 268, third 269, fourth 270, fifth 271 and sixth 272 triggers, the installation inputs of which are connected to the outputs of the first 284 and second 285 OR elements, moreover, the information inputs of the first 267 and second 268 triggers are connected to the “case”, the outputs of which are connected to information inputs of the third 269 and fourth 270 triggers, the outputs of which are connected to the information inputs of the fifth 271 and sixth 272 triggers, the outputs of which are connected to the inverse clock input of the seventh trigger 273 and the inverse input of the seventh element OR 290, respectively Namely, the output of the eighth trigger 274 is connected to the clock input of the ninth trigger 275 and the inverse enable input of the second counter 265, the output of the seventh trigger 273 is connected to the inverse reset input of the second counter 265, the group of outputs of which is connected to the group of inputs of the third element OR 286 and the first input of the third element And 293, the second input of which is connected to the output of the third OR element 286, and the output is connected to the information input of the eighth trigger 274.

The delay driver FZ1 277 contains a first trigger 298, a second trigger 299, a first OR-NOT 300 element, a second OR-NOT 301 element, a first AND element 302, a second AND element 303, the output of which is connected to the information input of the first trigger 298, the output of which is connected with a clock input of the second trigger 299, the output of which is the output 304 of the delay driver FZ1 277, the group of inputs 305 of which is connected to the groups of inputs of the first 300 and second 301 elements OR NOT and the first element AND 302, the outputs of which are the inputs of the second element And 303, and first entry Code 306 of the delay driver FZ1 277 is connected to the clock input of the first trigger 298, the reset input of which is the eighth input 307 of the delay driver FZ1 277 and connected to the reset input of the second trigger 299, the information input of which is connected to the "power".

The delay driver FZ2 279 contains a first trigger 308, a second trigger 309, an OR-NOT 310 element, a first And 311 element, a second And 312 element and a third And 313 element, the output of which is connected to the information input of the first trigger 308, the output of which is connected to the clock input the second trigger 309, the output of which is the output 304 of the delay driver FZ2 279, the group of inputs 305 of which is connected to the groups of inputs of the first 311 and second 312 of the AND elements and OR-NOT 310, the outputs of which are the inputs of the third AND element 313, the first input 306 of the driver I delay FZ2 279 is connected to the clock input of the first trigger 308, the reset input of which is the eighth input 307 of the delay generator FZ2 279 and connected to the reset input of the second trigger 309, the information input of which is connected to the "power".

The delay driver FZ3 283 comprises a first trigger 314, a second trigger 315, an OR-NOT element 316, a first AND element 317, a second AND element 318 and a third AND element 319, the output of which is connected to the information input of the first trigger 314, the output of which is connected to the clock input the second trigger 315, the output of which is the output 304 of the delay driver FZ3 283, the group of inputs 305 of which is connected to the groups of inputs of the first 317 and second 318 of the AND elements and the OR-NOT 316 elements, the outputs of which are the inputs of the third AND element 319, the first input 306 of the driver I delay FZ3 283 is connected to the clock input of the first trigger 314, the reset input of which is the eighth input 307 of the delay driver FZ3 283 and connected to the reset input of the second trigger 315, the information input of which is connected to the "power".

The electronic device of the ejection seat for an airplane (AUCC) works as follows.

The principle of operation of the UAVC is to obtain information from aircraft systems about the parameters of the aircraft’s flight at the time of bailout, such as: speed, speed head and flight altitude, state of the landing gear and the generation of a time delay for launching a parachute depending on the installed mass of the pilot in accordance with the architecture presented on FIG. 1, consisting of a normal mode calculator operating as a terminal device (OS) via the trunk serial interface of the GOST R 52070-2003 electronic module system (hereinafter - MKIO) that accurately calculates the time of the main parachute ejection using the Sh-I, Sh- algorithms II, W-III, W-IV, W-V, W-VI and issuing command 3.1; the controller of the normal operating mode, operating as a bus monitor (MS) (Monitoring device) according to the MKIO, which calculates the time of release of the main parachute of the spacecraft according to the algorithms Sh-I, Sh-II, Sh-III, Sh-IV, Sh-V, Sh- VI and issuing command 3.2; two identical calculators of autonomous mode of operation, carrying out a simplified calculation of the ejection time of the main parachute according to the autonomous algorithm, and issuing commands 1.1, 1.2, 2.1 and 2.2. After calculating the discharge time of the main parachute of the spacecraft, the calculator and controller of the normal operating mode exchange the calculation results and only when they coincide (with some accuracy) issue commands 3.1 and 3.2, respectively.

Fast algorithm

где Ах=15,1 [м/с²] - принятое максимально возможное ускорение движения самолета при V<Vоп, последнее принятое достоверное значения было такое, что V<Vоп, то T₁=0,4 с. В остальных случаях в данном алгоритме время T₁ определено быть не может.In the presence of the integral characteristic “CHASSIS IS RELEASED”, the time T ₁ = 0.4 s. If in the absence of an integral sign “CHASSIS IS RELEASED” before the appearance of the integral sign “MISSILE MECHANISM (SM)” in the time range

where Ax = 15.1 [m / s ² ] is the accepted maximum possible acceleration of the aircraft at V <Vop, the last accepted reliable value was such that V <Vop, then T ₁ = 0.4 s. In other cases, in this algorithm, the time T ₁ cannot be determined.

Algorithm Sh-I

Step 1: calculate the density of the atmosphere ρ [kg / m ³ ] according to the formula:

Step 2: the logical coefficients are calculated by the formulas:

Step 3: the coefficient K ₁ [km ² / kPa] is calculated by the formula:

Step 4: the predicted speed V * [km / h] is calculated by the formula:

V *: = V + ΔV, where ΔV: = 43.5 km / h.

Step 5: the predicted pressure head q * [kPa] is calculated by the formula:

Step 6: the coefficient K ₂ [km ² / kPa] is calculated by the formula:

Step 7: the delay t ₁ [s] is calculated by the formula:

Step 8: the delay t ₂ [s] is calculated by the formula:

Step 9: the parameter T ₂ [s] is calculated by the formula:

Step 10: the parameter T ₁₁ [s] is calculated by the formula:

Step 11: the parameter T ₁₂ [s] is calculated by the formula:

Step 12: the time T ₁ [s] is calculated by the formula:

Algorithm Sh-II

Step 1: the atmospheric density ρ _Nabs [kg / m ³ ] is calculated by the formula:

ρ _Nabs : = 1.090-0.088⋅H _abs + 0.0004⋅H _abs ² .

Step 2: the velocity head q [kPa] is calculated by the formula:

Step 3: calculate the time T ₁ according to the algorithm Ш-I.

Algorithm Sh-III

Step 1: the atmospheric density ρ _Nabs [kg / m ³ ] is calculated by the formula:

ρ _Nabs : = 1,090-0,088⋅Н _abs + 0,0004⋅Н _abs ² .

Step 2: the true airplane speed V [km / h] is calculated using the formula:

Step 3: calculate the time T ₁ according to the algorithm Ш-I.

Algorithm Ш-IV

Step 1: the velocity head q [kPa] is calculated by the formula:

Step 2: calculate the time T ₁ according to the algorithm Ш-I.

Sh-V Algorithm

Step 1: calculate the true speed of the aircraft V [km / h] using the formula:

Step 2: calculate the time T ₁ according to the algorithm Ш-I.

Algorithm W-VI

Step 1: the height value N [km] is calculated by the formula:

Step 2: the time T ₁ [s] is calculated using the following formula:

The block diagram of the EAAC is shown in FIG. 2.

The AECC consists of three independent nodes: the computational mode node (processor 1, RAM 2, ROM 3, controller 12), the autonomous mode of the bead A (ZBV 26), the autonomous mode of the bead B (ZBV 27).

The main regime EAUK includes:

- MKIO primary and backup channel based on the transmitters 5559IN74T transmitters of the Manchester code in accordance with GOST R 52070-2003;

- a calculator based on a microcontroller (MK) 1986BE1T;

- a controller based on a reprogrammable microcircuit (FPGA) A3RE1500-1PQG208I;

The MK and the controller receive the ICIE data from the aircraft systems, calculate in accordance with the Sh-I, Sh-II, Sh-III, Sh-IV, Sh-V, Sh-VI algorithms in the main mode and exchange data via the SPI bus ".

If the interval calculated by the MK programmatically does not coincide with that obtained in the controller (FPGA), taking into account the permissible deviation, by no more than 0.0064 s, the parachute ejection signal is blocked.

Thus, the implementation of the channel function (MK) - Model (FPGA) is implemented.

Also, the parachute ejection signal is blocked at the first power-up for a period of (10 ± 5) ms.

The EAUK constantly receives analog information on board A and on board B:

- signals “landing gear released A” and “landing gear released B”, determining the fact of the aircraft on the ground;

- signals "small mass A" and "small mass B", which determine the mass of the pilot as small;

- signals “large mass A” and “large mass B”, which determine the mass of the pilot as large;

- signals “accident A” and “accident B”, which determine the beginning of the procedure for emergency exit of the aircraft by the pilot;

- signals “firing mechanism (SM) A” and “firing mechanism B”, determining the fact of the operation of the squib;

- signals "stroke sensor (DX2) A" and "stroke sensor B", determining the fact of the beginning of the movement of spacecraft;

- signals "telemetry + 27V A" and "telemetry + 27V V", determining the fact of the presence of the main power supply;

- signals “ejection fact (FC) A” and “ejection fact B”, determining the fact of the operation of the ejection mechanism;

- signals “barorel 6 km A” and “barorel 6 km B”, determining the fact that the spacecraft is below a height of 6 km;

- signals “barorel 2 km A” and “barorel 2 km B”, determining the fact that the spacecraft is below a height of 2 km.

The analogue configuration information is constantly being supplied to the AAAA: the “address” signal, which determines the least significant bit of the op-amp and bus-link own address.

The analog information received in the ECMC in the form of signals of the “dry contact” / “open” type is converted to the values logical unit “1” / logical zero “0”, respectively, and is used further in the mathematics of the algorithm.

According to the results of its work according to the present algorithm, the AAAE gives an analog signal “input of the main parachute” of the “dry contact” / “open” type, which defines the beginning of the procedure for entering the main parachute of the spacecraft.

The OS and the MS have their own address 4 or 5, depending on the “address” signal, and they are regularly asked to receive digital information from the aircraft in format 1 and subaddress 8. The OS and the MS receive this information, the structure of data words (SD) which is presented in table 1 of FIG. 16. According to the results of receiving information, the OS in accordance with the ICIE issues a response word (OS) with the results of the reception.

The OS and the MS regularly receive a request to transmit digital information to the aircraft board in format 2 and subaddress 12. The OS and the MS receive the request, the OS issues the OS with the result of the request and gives information, the SD structure of which is presented in Table 2, and the MS controls it.

The integral attribute “CHASSIS IS RELEASED” of the computer and the controller of the normal operation mode is determined by the logical “OR” 167 of the signs “CHASSIS IS RELEASED” (Tg 149) and the latches “chassis released A” and “chassis released B”.

The latches “chassis released A” and “chassis released B” of the calculator and the controller of normal operation in the absence of the integral sign “ALARM” repeat the values of the analog signals “chassis released A” and “chassis released B”, respectively, and in the presence of the integral sign “ALARM” "(OR 209, Tg197) their meanings do not change.

The latches “chassis released A” and “chassis released B” of the autonomous operating mode nodes are remembered when they are turned on based on the values of the analog signals “chassis released A” and “chassis released B”, respectively.

The mass ranges “LOW MASS”, “MEDIUM MASS”, “LARGE MASS”, are determined in accordance with table. 3 formation of the mass range.

“LOW MASS” and “MEDIUM MASS” are formed on the elements And 291 and And 292 of FIG. 12 respectively.

The latches “LOW MASS A” and “LOW MASS B”, “LARGE MASS A” and “LARGE MASS A” of the computer and the controller of the normal operating mode in the absence of the integral sign “ALARM” repeat the values of the analog signals “LOW MASS A” and “LOW MASS MASS B ”and“ BIG MASS A ”and“ BIG MASS B ”, respectively, and in the presence of the integral sign“ EMERGENCY ”, their values do not change.

The latches “LOW MASS A” and “LOW MASS B”, “LARGE MASS A” and “LARGE MASS A” of the autonomous operating mode nodes are remembered when they are turned on based on the values of the analog signals “LOW MASS A” and “LOW MASS A”, “LARGE MASS A” and “LARGE MASS B” are “small mass A” and “small mass B”, respectively.

Depending on the mass values “LOW MASS” and “LARGE MASS”, the following values of the parachute insertion speed Vop presented in table 3 in FIG. eighteen.

The integral attribute “STROKE SENSOR 2 (DX2)” (OR 208 of Fig. 9) of the normal operation computer initiates the procedure of storing the following information parameters in non-volatile memory ROM 3:

- the true speed of the aircraft V;

- velocity head q;

- the value of the absolute barometric height of the Nabs;

- a sign of reliability of the parameter V - Vd;

- a sign of reliability of the parameter q - qd;

- a sign of reliability of the parameter Nabs - N;

- the algorithm of the automation of the normal operating mode (name);

- own calculated value of the parameter T1;

- the calculated value of the parameter T1 of the controller of the normal operation mode;

- telemetry signal "chassis released A";

- telemetry signal "small mass A";

- telemetry of the signal "large mass A";

- telemetry of the signal "accident A";

- telemetry signal "firing mechanism (SM) A";

- telemetry of the signal "stroke sensor (DX2) A";

- telemetry of the signal "telemetry + 27V A";

- telemetry signal "fact of bailout (FC) A";

- telemetry of the “6 km A barorele” signal;

- telemetry signal "barorel 2 km A";

- telemetry signal "chassis released In";

- telemetry of the signal "low mass B";

- telemetry signal "large mass B";

- telemetry of the signal "accident B";

- telemetry signal "firing mechanism (SM) B";

- telemetry signal "stroke sensor (DX) B";

- telemetry signal "telemetry + 27V";

- telemetry signal "fact of bailout (FC) B";

- telemetry of the signal “barorel 6 km V”;

- telemetry signal "barorel 2 km V";

- telemetry signal "address".

When receiving information on the MKIO with DMKIO = "1" (a sign of reliable exchange), the microcontroller (1-7, 11, 25) and the controller (12) of the normal operating mode calculate the time delay T1 in accordance with the fast algorithm. If the fast algorithm cannot calculate the delay T1, then the calculation is carried out in accordance with the algorithms shown in table 4 in FIG. 19 depending on the parameters Vd, qd, Nd. The MK of the normal operation mode initiates the exchange of information with the controller of the normal operation mode via the SPI interface no later than 5 ms after receiving information on the MCIP with DMKIO = "1". Moreover, the time ΔТ1 (0 s <= ΔТ1 <= 0.8 s) means the time interval from the moment of receipt of the selected parameters according to the ICIE to the calculation.

When transmitting information via the ICIP, the controller checks the accuracy of the information transmitted MK normal operation.

In cases where the exchange via the SPI interface has not occurred or the time delay T1 differs by more than 0.0064 from the MC and / or the controller of the normal operating mode blocks the issuance of commands 3.1 and / or 3.2, respectively, depending on which one has detected specified violation. In the event that the controller of the normal operation mode found that the information transmitted by the ICIE does not match his expectations, he will block the issuance of command 3.2.

If at the moment of receiving the integral attribute “MASTERING MECHANISM (SM)” (OR 207, Tg 192) in the previous time interval of 0.8 s there are information messages, then the MC and the controller of the normal operation mode of the time delay T1 are carried out in accordance with the fast algorithm. If the MC by the fast algorithm cannot calculate the delay T1, then the calculation is carried out according to the algorithms in accordance with the priority indicated in table 4 of FIG. 19. At the same time, the time ΔТ1 (0 s <= ΔТ1 <= 0.8 s) means the time interval from the moment of obtaining reliable information parameters selected in accordance with the priority to the receipt of the integral attribute "SHOOTING MECHANISM (SM)". If there are no information messages in the previous time interval of 0.8 s, then the issuance of commands 3.1 and / or 3.2 is blocked. The MK of the normal operation mode initiates the exchange of information with the controller of the normal operation mode via the SPI interface no later than 5 ms after receiving information on the MCIP with DMKIO = "1".

The ZBV nodes (26, 27) of the autonomous mode of operation, in the presence of the integral attribute “MOTION MECHANISM (SM),” calculate the time delay using the autonomous algorithm.

The MK of the normal operation mode is the main one (Master), and the controller of the normal operation mode is the Slave unit in the SPI interface, which is represented at the physical level by a 4-wire interface containing the following signals:

- SCLK - signal of the clock frequency issued by the Master unit;

- CS - Slave block selection signal (active “0”);

- MOSI - a signal containing data coming from the Master unit;

- MISO - a signal containing data coming from the Slave block.

A timing diagram showing the distribution of binary bits of information in an SPI 42 exchange is shown in FIG. twenty.

One parcel of exchange transmits 16 binary bits to both blocks.

The interaction of the Master and Slave blocks at the channel level is the sending of frames on the SPI interface 42, separated by a synchronizing pause among themselves (Fig. 21).

The frame consists of X packages, where X can be in the range from 1 to 8. When the Master initiates more than one package, the information in them cyclically repeats (with updating).

The frame will automatically begin with parcel No. 1 when the integral sign “SHOOTING MECHANISM (SM)" occurs, as well as after receiving reliable data with the correct checksum according to format 1 of the interface GOST R 52070-2003 for MK and the controller for normal operation.

The structure of the information in the frame coming from the controller 12 to the MC of the normal operation mode is presented in table 5 of FIG. 22.

The information structure in the frame coming from the MC to the controller 12 of the normal operating mode is presented in table 6 of FIG. 23.

The functional diagram of the controller 12 is shown in FIG. 3.

The controller consists of a processor 52, ALU 54, ROM53, a constant assembly 55, an MCO monitor 51, a parameter selection unit 56, an ejection signal generation unit 57.

The processor 52, ALU 54 and ROM53 ensure the execution of a fast algorithm and algorithms for the automation of normal operation.

The MKIO 51 node provides MC data exchange between the AAA and the aircraft system.

Parameter selection node 56 is intended for selecting and storing parameters from the MCO protocol, for determining the maximum safe bailout time in a fast algorithm.

The site of the formation of the ejection signal 57 is designed to generate the necessary and sufficient sign of ejection.

A functional diagram of the ejection signal generation section 57 is shown in FIG. four.

The ejection signal generation unit 57 consists of SPI_SLAVE 77, SPI_STATE 78, CMND 79, MASK 80, a control unit 82, and a combinational circuit 83.

The SPI_SLAVE 77 node is intended for data exchange between the processor 1 and the controller 12 via the SPI bus 42, a timing diagram of the exchange is shown in FIG. twenty.

The SPI_STATE 78 node is designed to transmit a frame on the SPI 42 bus (Fig. 21).

Node CMND 79 is designed to form a reliable condition for bailouts.

The MASK 80 node is designed to form a bailout permit.

The control unit 82 provides control of the nodes of the ejection signal generating unit 57 and generating the START signal (73).

The combinational circuit 83 provides data generation for the SPI_SLAVE 77 node.

The combinational circuit 83 has the following formula:

» - логическое И, «+» - логическое ИЛИ.where "

"- logical AND," + "- logical OR.

A functional diagram of the parameter selection unit 56 is shown in FIG. 9.

Parameter selection node 56 consists of arithmetic register and flag register nodes 216, speed register V 217, register of the last value of found speed Vc 219, speed register from MCO Vlc 218, register of pressure head Q 221, register of pressure head from MCO Qc 222, height register H 223 and height register from MCO Hc 224 first combinational circuit 225, second combinational circuit 226, third combinational circuit 227, fourth combinational circuit 228, fifth combinational circuit 229, sixth combinational circuit 230, seventh combinational circuit 231, nodes counters dt1..dt6, dtc, limit value counter Δt (register 220, adder 232 and multiplexer 233).

The first combination circuit 225 of the parameter selection node 56 provides the formation of enable signals E1, E2, E3 for receiving data into the register of arithmetic operations and flags.

The first combinational circuit 225 has the following formula:

E3 = E1 + E2.

The second combination circuit 226 of the parameter selection node 56 provides the formation of enabling signals EV1, EV2, EV3 for receiving data in the speed registers 217 depending on the reliability parameters presented in table 4 (register V1 → (the speed Vd and the pressure head qd are reliable), the register V2 → (reliable speed Vd and height Nd), register V3 → (reliable speed Vd)).

The second combinational circuit 226 has the following formula:

The third combination circuit 227 of the parameter selection node 56 provides the formation of the enable signal EVc for receiving data and the data DVc (14..0) in the register Vc, in which the last value of the found speed is stored.

The third combinational circuit 227 has the following formula:

The fourth combinational circuit 228 of the parameter selection node 56 provides the formation of enabling signals Eq1, Eq3, Eq5 for receiving data into the pressure head registers 221 depending on the reliability parameters presented in table 4 (register q1 → (speed Vd and speed head qd are reliable), register q3 → (the height Nd and the pressure head qd are reliable), the register q5 → (the speed head qd is reliable)).

The fourth combinational circuit 228 has the following formula:

The fifth combination circuit 229 of the parameter selection node 56 provides the formation of the enable signal Eqc for receiving data and the Dqc data in the Qc register, in which the last value of the velocity head is stored.

The fifth combinational circuit 229 has the following formula:

The sixth combinational circuit 230 of the parameter selection node 56 provides the formation of enable signals EH2, EH3, EH6 for receiving data in height registers 223 depending on the reliability parameters presented in table 4 (register H2 → (speed Vd and height Nd are reliable), register H3 → (reliable height Nd and pressure head qd), register Н6 → (reliable height Nd)).

The sixth combinational circuit 230 has the following formula:

The seventh combination circuit 231 of the parameter selection node 56 provides the formation of the enable signal EHc for receiving data and the DHc data in the register Hc, in which the last height value is stored.

The seventh combinational circuit 231 has the following formula:

A functional diagram of the counter assembly 215 is shown in FIG. eleven.

The counter node 215 consists of six dt counters (adders 242-247, multiplexers 249-254, registers 255-260), a DTC counter (register 261, adder 248), the first combinational circuit 240, the second combinational circuit 241, the And 263 element and trigger 262.

Counters dt determine the time period of reliable information parameters. The operation algorithm of the dT counters is shown in FIG. 24, 25.

The DTC counter, the And 263 element and the trigger 262 determine the time interval from the moment of receipt of reliable information parameters selected in accordance with the priority, to the receipt of the integral sign "MOTION FUNCTION (SM)". If there are no information messages in the previous time interval of 0.8 s, then the issuance of commands 3.1 and / or 3.2 is blocked.

The first combinational circuit 240 provides the generation of control signals for dt counters. The first combinational circuit 240 has the following formula:

The second combinational circuit 241 provides the formation of an enable signal for receiving Edtc data and Ddtc data in the DTC register 261, which together with the And element and trigger 262 determine the time when you need to go to the calculation of T1.

The second combinational circuit 241 has the following formula:

The functional diagram of the ZBV nodes (bar-time gate) 26, 27 is shown in FIG. 12.

Node ZBV (bar-time shutter) 26, (27) of the autonomous mode of operation in the presence of the sign “SHOOTING MECHANISM (SM)” performs a simplified calculation of the time of the main parachute ejection according to the autonomous algorithm and issues commands 1.1, 1.2, 2.1 and 2.2.

The ZBV (bar-time shutter) node 26, (27) contains the first counter 264, the second counter 265, the third counter 266, the first trigger 267, the second trigger 268, the third trigger 269, the fourth trigger 270, the fifth trigger 271, the sixth trigger 272, the seventh trigger 273, eighth flip-flop 274, ninth flip-flop 275, tenth flip-flop 276, first delay shaper FZ1 277, second delay shaper FZ1 278, first delay shaper FZ2 279, second delay shaper FZ2 280, third delay shaper FZ2 281, fourth delay shaper FZ2 282, delay former FZ3 283, first element nt OR 284, second OR element 285, third OR element 286, fourth OR element 287, fifth OR element 288, sixth OR element 289, seventh OR element 290, first AND element 291, second AND element 292, third AND element 293, fourth element And 294, the fifth element And 295, the sixth element And 296.

The sign "EMERGENCY" is formed as a logical OR of the signals "accident A" and "accident B". According to this signal, power is supplied to the aircraft’s ESCA for the autonomous operating mode ZBV nodes.

The latches “chassis released A” and “chassis released B” are received at ZBV 26 and 27, respectively. The latches “chassis released A” and “chassis released B” of the ZBV units of stand-alone operation are remembered when they are turned on based on the values of the analog signals “chassis released A” and “chassis released B”, respectively.

Signals with a duration of at least 4 ms “travel sensor 2 (DX2) A” and “travel sensor 2 (DX2) B”, arriving at nodes ZBV 26 and 27, respectively, serve as the beginning of the report: time T ₂₆ of the main parachute ejection depending on the BR2 and BR6 (from 2 to 6 km) before issuing commands 1.1 and 2.1; time T _{22 of the} release of the main parachute, depending on the state of the barrele BR2 and BR6 (up to 2 km) before issuing commands 1.2 and 2.2.

The latches “small mass A” and “small mass B” of the nodes ZBV 26, 27 of the stand-alone operation mode are remembered when they are turned on based on the values of the analog signals “small mass A” and “small mass B”, respectively.

The latches “large mass A” and “large mass B” of the nodes ZBV 26, 27 of the stand-alone operation mode are remembered when they are turned on based on the values of the analog signals “large mass A” and “large mass B”, respectively.

The nodes ZBV 26 and 27 autonomous mode of operation in the presence of the sign "MOTIONING MECHANISM (CM)" calculate the time delay using an autonomous algorithm.

Until the CM signal arrives, counter 265 is locked. When the SM signal arrives (OR element 284, flip-flops 267, 269, 271, 273) and the RES 41 is not reset, the counter 265 starts counting, after 160 ms the trigger 274, 275 are set to “1”, allowing the DX stroke sensor to pass through the signal ( OR element 285, flip-flops 268, 270, 272) to flip-flop 276, which on the trailing edge removes the reset from the delay counter for generating a parachute ejection signal.

Depending on the mass of the pilot (VM large, MM small and SM medium) and the “CHASSIS RELEASED (SH-S)” signal, various parachute release delays are formed on the elements FZ1, FZ2 and FZ3 (1.3 s, 1.5 s , 2.1 s, 2.3 s, 2.5 s, 3.6 s, 0.4 s).

In the presence of signals barrel BR2 44 and BR6 46 on the elements OR 287, 288, 289 and the elements And 294, 295, 296, the signal of the ejection of the parachute REL 297 will be generated.

Standalone algorithm

Step 1: If “CHASSIS IS RELEASED”, the time T ₂₂ = 0.4 s, otherwise it is calculated by the formula:

Step 2: If there is a sign “CHASSIS IS RELEASED”, the time T ₂₆ = 0.4 s, otherwise it is calculated by the formula:

The process of ejection of an upgraded ejection seat (KK) K-36L-3,5YaM (with a controller, with two barorels) is the following sequence of actions:

- before the flight, the parameter “pilot mass” (small, medium or large) is entered into the spacecraft;

- in flight, the plane supplies power to the spacecraft automatics, informs it of the “true airplane speed”, “speed head”, “absolute barometric altitude”, “landing gear compression fact”, “spacecraft number” (first or second) and “signs of reliability” of these data. In response, the KK automation returns “accepted values” and “estimated time delay for entering the main parachute”, which are received, including in the “black box” of the aircraft;

- the pilot, reporting on his actions, tears the handles, pulls the handrails. The “accident” command, the destruction of the flashlight, the automation is activated, the “ejection fact” command is generated. The fixing system is initiated: the pulling of the belts begins, the fixing and raising of the legs, the side arms of the arms lower and lower.

The integral sign “EMERGENCY” is formed as a logical “OR” 209 of the signals “ACD_A alarm” and “ACD_B alarm”, setting trigger 194 to “1” (Fig. 9). According to this signal, power is supplied to the EECC for calculators of stand-alone operation mode. The processor 1 on the bus 48 (Fig. 9) transmits the sign of the fact "catapult" in KMKO 11, and then through the second group of inputs 35 to the central computer.

After 0.2 seconds, the fixation ends, a command is issued for the bailout "firing mechanism" (SM).

The integral sign of “SHOOTING MECHANISM” is defined as the logical “OR” 207 (Fig. 9) of the signals “SM_A” and “CM_B” and trigger 192, which allows the passage of the “EMERGENCY” signal from triggers 197, 198, which is necessary to obtain permission for bailout. In the calculator and the controller of the normal operating mode, this feature forcibly blocks the reception of information from the ICMO before resetting the power on.

After 0.35-0.4 seconds, the firing mechanism moves the spacecraft along the guides, the command "stroke sensor 2" is generated. The introduction of stabilizer rods begins.

The integral characteristic of DX2 is defined as a logical “OR” 208 of the signals “travel sensor 2” DX2_A and “travel sensor 2” DX2_B and trigger 193 (Fig. 9), allowing the passage of the alarm signal from triggers 196, 197, which is necessary for obtaining permission on bailout. After 170 ms (second register 201, adder 203, comparison circuit 204) after receiving the integral attribute “SHOOTING MECHANISM (SM)”, the permission signal for the passage of the external signal “STROKE 2” “DX2” is generated on element I 212, according to which counter 1 (element And 210, adder 202, the first register 200) begins to count the time of ejection of the parachute.

After 0.45 seconds, the spacecraft leaves the cockpit, jet engines and roll correction mechanisms are turned on.

After 0.8-4.0 seconds: the spacecraft stabilizes according to the flight vector, and at high altitudes there is a decrease to a certain height, determined by the “barorel” commands.

The integral attribute “BARORELA 6 km” is formed as a logical “OR” of 206 signals “barrele 6 km A” BR6_A and “barorele 6 km B” BR6_B and trigger 191 and unlocks the generation of the bailout permit.

After that, the command “to enter the main parachute” with an error of ± 0.02 s is issued, leading to the shooting of the heading, separation from the spacecraft and the introduction of the parachute.

Sources of information taken into account during the examination:

1. Patent No. US 4505444, B64D 25/10, 1983

2. Patent No. US 4527758, B64D 17/58, 1983.

3. Patent No. US 4792903, B64D 25/10, 1985

4. Chip A3P250 - 1VQG100I f. MICROSEMI. Order card UShKR.430103.528 D16 (JSC Research Institute Submicron).

5. Chip A3RE1500 - 1PQG208I f. MICROSEMI. Order card UShKR.430103.527 D16 (JSC Research Institute Submicron).

Claims (14)

1. The electronic device of the ejection seat (KK) for the aircraft (EUKK), containing a processor, RAM, ROM, switch (Time Zero Switch), clock (clock), timer, switch (Power switch), the first, second and third pressure sensors, moreover, the outputs of the switch, clock and timer are connected to the first, second and third inputs of the processor, the first, second and third outputs of which are connected to the inputs of the clock, timer and switch, and the group of inputs / outputs of the processor is connected to the group of inputs and outputs of RAM, the group of inputs of which connected to a group of processor outputs, the input group of which is connected to the group of ROM outputs, characterized in that it additionally includes an MCO controller, a controller (Monitoring device), a group of optocouplers, a fourth pressure sensor, first, second, third and fourth optocouplers, the first, second and third reset circuits power supply, the first, second, third and fourth generators, the first and second nodes ZBV (time-lag shutter), the first and second elements AND, the OR element, the key, the output of which is the output of the EECC, the first group of inputs of which are connected to the group of optocouplers, the group of outputs of which soy dinene with the first groups of inputs of the controller, the first and second nodes ZBV (time-lag shutter), the outputs of which are connected to the first and second inputs of the OR element, the output of which is connected to the input of the key, and the second group of inputs of the DCMC is connected to the first group of inputs of the controller MCO and the second group inputs of the controller, the first output of which is connected to the first inputs of the first and second AND elements, the outputs of which are connected to the third and fourth inputs of the OR element, and the first input of the first node ZBV (time-lag shutter) is connected to the output the house of the first generator, the first input of which is connected to the output of the first generator, the output of the second generator is connected to the first input of the second node ZBV (time-lag shutter), the second input of which is connected to the output of the second power reset circuit, the outputs of the first and third power reset circuits are connected to the second input of the first latch gate and the third processor input, the first input of the controller, respectively, whose SPI bus is connected to the processor SPI bus, the first group of outputs of which is connected to the group of RAM inputs, p By the way, the first input of the DCMC is connected to the first, second and fourth inputs of the MCO controller, controller and processor, and the third input of the first ZBV node (time-lag shutter) with the output of the first optocoupler, the input of which is connected to the output of the first pressure sensor, the output of the second pressure sensor is connected to the input of the second optocoupler, the output of which is connected to the third inputs of the controller and the second node ZBV (bar-time shutter) and to the fifth input of the processor, and the fourth input of the first node ZBV (bar-time shutter) is connected to the output of the third op a throne, the input of which is connected to the output of the third pressure sensor, and the output of the fourth pressure sensor is connected to the input of the fourth optocoupler, the output of which is connected to the fourth input of the second ZBV node (time-lag shutter), with the fourth input of the controller and with the sixth input of the processor, the processor bus is connected to MCO controller, and the fifth input of the controller is connected to the output of the third generator, the output of the switch is connected to the second inputs of the first and second elements AND, and the output of the fourth generator is connected to the seventh input th processor. 2. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the controller (Monitoring device) comprises an MCO monitor, a processor (CPU), ROM, an arithmetic logic unit (ALU), a constant node, a parameter selection node, a formation node ejection signal, whose SPI bus is connected to the controller's SPI bus, the output (parachute ejection signal) of which is connected to the first output of the ejection signal generating unit, the first group of outputs of which is connected to the first group of ALU inputs, the first, second, third, fourth, fifth, a group of outputs of which are connected to the first, second, third, fourth, fifth, sixth groups of inputs of the processor, the information group of inputs of which is connected to the group of outputs of the ROM, the group of inputs of which is connected to the address group of outputs of the processor, the first, second, third groups of outputs of which are connected with the second, third, fourth groups of inputs ALU, the seventh, eighth, ninth, tenth, eleventh, twelfth groups of outputs are connected to the seventh, eighth, ninth, tenth, eleventh, twelfth groups of inputs in the processor, the fourth, fifth and sixth groups of outputs of which are connected to the first, second and third groups of inputs of the parameter selection node, the first, second and third groups of outputs of which are connected to the fifth, sixth and seventh groups of inputs ALU, the thirteenth group of outputs of which is connected to the first the group of inputs of the ejection signal generation unit, the second group of outputs of which is connected to the eighth group of ALU inputs, the ninth group of inputs which is connected to the second group of inputs of the ejection signal generation and with the seventh group of processor outputs, the thirteenth group of inputs of which is connected to the third group of outputs of the ejection signal generating unit, the fourth group of outputs of which is connected to the fourth group of inputs of the parameter selection unit, the fourth group of outputs which is connected to the third group of inputs of the ejection signal generation, fifth group of outputs which is connected to the fifth group of inputs of the parameter selection node, the sixth group of inputs of which is connected to the fourth group of inputs of the formation node ejection needle and with the output of the MCO monitor, the input group of which is connected to the second group of inputs of the controller, the second input of which is connected to the input of the MCO monitor, the clock and reset inputs of which are connected to the clock and reset inputs of the processor, ALU, ejection signal generation unit, parameter selection node and a controller, the first group of inputs of which is connected to the fifth group of inputs of the ejection signal generation unit, the second output of which is connected to the processor input, the fourteenth group of inputs in which it is connected to the seventh group of inputs of the parameter selection node, to the sixth group of inputs of the ejection signal generation unit and to the output of the constant node, the eighth and ninth groups of processor outputs are connected by the seventh and eighth groups of inputs of the ejection signal generation node, the eighth and ninth groups of processor outputs connected to the seventh and eighth groups of inputs of the ejection signal generation unit, the first and second inputs of which are the third and fourth inputs of the controller. 3. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the ejection signal generating unit comprises an SPI_SLAVE unit, an SPI_STATE unit, a CMND unit, a MASK unit, an I element, a control unit and a combination circuit, the output group of which is connected to the first group the inputs of the SPI_SLAVE node, the output group of which is connected to the first group of inputs of the CMND node, the output group of which is the second group of outputs of the ejection signal generation unit, whose SPI bus is connected to the SPI bus of the SPI_SLAVE node, the output of which is connected to the first inputs of the SPI_STATE and CMND nodes, the first output of which is connected to the first input of the And element, the output of which is the first output of the ejection signal generating unit, the second output of which is connected to the first output of the control unit, the second output of which is connected to the second inputs of the SPI_STATE and CMND nodes, the second the group of inputs of which is connected to the first group of outputs of the SPI_STATE node, the second group of outputs of which is connected to the first group of inputs of the control node and the third input of the CMND node, the third and fourth groups of inputs of which are connected with the eighth and seventh groups of inputs of the ejection signal generating unit, the first group of outputs of which is connected to the second group of outputs of the control unit, the third and fourth groups of outputs which are connected to the fifth and fourth groups of outputs of the ejection signal generating unit, the first group of inputs of which is connected to the first group inputs of the combinational circuit, with the fifth and first groups of inputs of the nodes CMND and MASK, the group of outputs of which is connected to the first group of inputs of the node SPI_STATE, the second group of inputs of which is inena with the second and sixth groups of inputs of the control nodes and CMND and is the second group of inputs of the ejection signal generating unit, respectively, the fifth group of inputs of which is connected to the second group of inputs of the MASK node and the third group of inputs of the control node, the fifth group of outputs of which is connected to the second group of inputs a combinational circuit, the third group of inputs of which is the fourth group of inputs of the ejection signal generation unit and is connected to the third input of the SPI_STATE node and the fourth group of inputs of the node board, the sixth group of outputs of which is the third group of outputs of the ejection signal generating unit, the third group of inputs is connected to the sixth group of inputs of the control unit, the sixth group of inputs of the ejection signal generating unit is connected to the fourth group of inputs of the combinational circuit, with the third groups of inputs of the MASK and SPI_STATE nodes , with the second group of inputs of the SPI_SLAVE node, with the seventh group of inputs of the CMND node and with the fifth group of inputs of the control node, the first input of which is connected to the first output of the MASK node, th output is connected to the second input of the AND, and a clock input node and effluent formation ejection signal connected to the clock and reset input node SPI_SLAVE, node SPI_STATE, management node, and the node MASK CMND node. 4. The electronic device of the ejection seat for an aircraft according to claim 1, characterized in that the SPI_SLAVE node contains a first register, a second register, a third register and a fourth register, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger and a sixth trigger, the adder, the first multiplexer, the second multiplexer, the third group of multiplexers, the fourth multiplexer, the fifth group of multiplexers and the sixth group of multiplexers, the first element And, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, seventh element And and eighth element And, element OR and element 3-OR, the output of which is connected to the information input of the sixth trigger, the output of which is the fourth signal of the SPI bus, the first, second and third signals of which are connected to the information input of the first trigger, with the first input of the first multiplexer, with the first input of the second multiplexer, respectively, the output of which is connected to the information input of the fourth trigger, the output of which is the fifteenth bit of the first group of inputs of the sixth group of multipl which is zero to fourteenth digits of which are connected to the group of outputs of the fourth register and are the group of outputs of the SPI_SLAVE node, whose output is connected to the output of the fifth trigger, whose inverse enable input is connected to the inverse enable input of the fourth register and the output of the sixth element And, whose first inverse input is connected to the input of the adder and the output of the second element And, the direct input of which is connected to the output of the second trigger and the first input of the fourth multiplexer, the output of which is connected to information the ion input of the third trigger, the output of which is connected to the inverse input of the second element And and the direct input of the third element And, the output of which is connected to the inverse input of the first element And, the output of which is connected to the inverse enable input of the sixth trigger and the first input of the OR element, the output of which is connected to an inverse enable input of the second register, the group of outputs of which is connected to the group of inputs of the third multiplexer, and the fifteenth bit is connected to the first input of the 3-OR element, the second input of which is connected to the output of the fifth element And, the first inverse input of which is connected to the inverse input of the fourth element And, with the third input of the 3I-OR element, controlling the inputs of the first, second, fourth, fifth and sixth multiplexers, with the second inverse input of the sixth element And, with the inverse input of the seventh AND element, with a permitting input of the first register, with the second input of the OR element, with the second inverse input of the first AND element and the output of the first trigger, the clock input of which is connected to the clock inputs of the second, third, fourth, fifth of the sixth and sixth triggers, with the clock inputs of the first, second, third and fourth registers and with the clock input of the SPI_SLAVE node, the reset input of which is connected to the inverse, installation inputs of the first, second, third, fourth and sixth triggers and with the reset inputs of the first, second, the third and fourth registers and the fifth trigger, the information input of which is connected to the output of the seventh element And, the first, second, third and fourth inputs of which are connected to the group of inputs of the eighth element And, with the group of inputs of the adder and the group of outputs of the third register, the information group of inputs of which is connected to the group of outputs of the fifth group of multiplexers, the first group of inputs of which is connected to the group of outputs of the adder, the second group of inputs of the fifth group of multiplexers is connected to the group of inputs of the sixth group of multiplexers (constant 0) and the group of inputs CONST, which (constant 1) is connected to the second inputs of the first, second and fourth multiplexers and to the fourth input of the 3-OR element, the fifth input of which is connected to the output of the fourth AND element, pr my input is connected to the inverse input of the fifth element And, with the output of the eighth element And and the control input of the third group of multiplexers, the second group of inputs of which is connected to the group of outputs of the first register, and the fifteenth digit is connected to the sixth input of the element 3-OR, and the group of outputs of the third the group of multiplexers is connected to the information group of inputs of the second register, the output of the first multiplexer is connected to the information input of the second trigger, the group of outputs of the sixth group of multiplexers is connected to formation group of inputs of the fourth register. 5. The electronic device of the ejection seat for an aircraft according to claim 1, characterized in that the SPI_STATE node contains a first trigger, a second trigger, an adder, a register, a 3-OR element group, a first OR element, a second OR element, a third OR element, a fourth element OR, the first element AND, the second element AND, the third element AND, the fourth element AND, the fifth element AND, the sixth element AND, the seventh element And, the eighth element And, the ninth element And and the tenth element And, the output of which is connected to the first input of the fourth element OR whose output is connected to inverse the input of the first AND element is the second signal of the second group of outputs of the SPI_STATE node, the first signal of which is connected to the information input of the second trigger and the output of the fifth AND element, whose direct input is connected to the output of the first OR element, the first input of which is connected to the first inverse input of the fourth element And, with the first input of the second OR element, it is the first signal of the fourth group of inputs of the SPI_STATE node, the first group of outputs of which is connected to the group of inputs of the adder and the group of outputs of the register, I am the group of inputs of which is connected to the group of outputs of the group of 3I-OR elements, the first allowing input of which is connected to the inverse input of the seventh AND element and the output of the second OR element, the second input of which is connected to the second inverse input of the fourth AND element and the output of the second AND element, direct and whose inverse inputs are the second and third signals of the first group of inputs of the SPI_STATE node, the first signal of which is connected to the second input of the first OR element, the second group of inputs of the SPI_STATE node: zero discharge connected to the line the input of the ninth element And, the first discharge is connected to the first inverse input of the tenth element And, the second discharge is connected to the first and second inverse inputs of the ninth and tenth elements And, the third discharge is connected to the second inverse and direct inputs of the ninth and tenth elements And, accordingly, the output of the ninth element And connected to the second input of the fourth OR element, and the first input of the SPI_STATE node is connected to the information input of the first trigger and the inverse input of the third AND element, the output of which is connected to the direct input of the seventh of the And element, the third inverse input of the fourth And element and the first input of the sixth And element, the output of which is connected to the second enable input of the group of 3-OR elements, the first (000) and second (111) information groups of which are the third group of inputs of the SPI_STATE node, the second the input of which is connected to the inverse input of the fifth and the direct input of the first AND element, respectively, the output of which is connected to the inverse enable input of the second trigger, the output of which is connected to the second input of the sixth element AND and the inverse input of the eighth AND element, the output of which is connected to the enable input of the adder and the first input of the third OR element, whose output is connected to the third enable input of the 3I-OR element group, whose third information group of inputs is connected to the adder output group, and the clock and reset inputs of the SPI_STATE node are connected to clock and reset inputs of the first and second triggers and register, the output of the first trigger is connected to the direct input of the third element And, and the output of the fourth element And is connected to the second input of the third element and OR, the output of the seventh element AND is connected to the direct input of the eighth element I. 6. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the control unit comprises a QC stabilization parameter comparison unit, a register, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, and an eighth trigger, ninth trigger, adder, combinational circuit, first element And, second element And, third element And, fourth element And, fifth element And, sixth element And, seventh element And, eighth element And, ninth element And, tenth element And, first element IL And, the second OR element, the third OR element, the fourth OR element, the fifth OR element, the sixth OR element, the output of which is connected to the information input of the ninth trigger, the output of which is connected to the first input of the second AND element and is the first signal of the fifth group of outputs of the control unit, the second and third signals of which are connected to the outputs of the eighth and sixth triggers, the information input of the sixth trigger is connected to the inverse input of the ninth element And the output of the second trigger, the information input of which is connected to the output of the of the OR element, whose inverse inputs are the first and second signals of the fifth group of inputs of the control node, the third, fourth, fifth and sixth signals of which are connected to the inverse inputs of the second AND element and the sixth OR element, the output of the second AND element is connected to the information input of the first trigger, the output of which is connected to the direct input of the ninth element AND, the output of which is connected to the information input of the eighth trigger, the enable input of which is connected to the enable input of the ninth trigger, with inverse enable m input of the sixth trigger and is the first input of the control unit, the first group of outputs of which is connected to the group of outputs of the register, the information group of inputs of which is connected to the group of outputs of the combinational circuit, the group of inputs of which is the fourth group of inputs of the control unit, the second signal of which is connected to the information input of the third trigger, and the fifth signal is connected to the first inputs of the fifth and third elements OR and the third element AND, the output of which is connected to the enable input of the third trigger, the output is connected to the second input of the second OR element, the output of which is the first signal of the second group of outputs, the second signal of which is connected to the second inputs of the third and fifth OR elements, with the first inverse input of the first AND element, with the inverse input of the fourth AND element, with the first combination input circuit and is the first signal of the fourth group of outputs of the control unit, and the third signal of the second group of outputs of the control unit is connected to the output of the fifth trigger, the information input of which is connected to direct input the ode of the eighth element And, with the inverse inputs of the sixth, seventh and tenth elements And, with the second inverse input of the first element And, with the first input of the adder, with the output of the seventh trigger, is the second signal of the fourth group of outputs and the second output of the control unit, the third group of outputs of which connected to the second group of inputs of the combinational circuit and the group of outputs of the node for comparing the stabilization parameters of the QC, the first group of inputs of which is the third group of the control node, the first group of inputs of which is connected to the input inputs of the fourth OR element and the fourth AND element, the output of which is connected to the second input of the fourth OR element, the output of which is connected to the second input of the adder, the output of which is connected to the information input of the seventh trigger, the inverse output of which is connected to the second input of the fourth AND element, the second the group of inputs of the control unit is connected to the first and second inverse inputs and the direct input of the fifth element And, the output of which is connected to the inverse input of the eighth element And, the output of which is connected to the fifth enable input of the fifth trigger, the clock and reset inputs of which are connected to the clock and reset inputs of the first, second, third, fourth, sixth, seventh, eighth, ninth triggers, register and are the clock and reset inputs of the control unit, the sixth group of inputs of which are connected to the second group of inputs of the node to compare the stabilization parameters of the QC and with the third group of inputs of the combinational circuit, and the output of the first element And is connected to the second input of the third element And, the output of the third element OR with is dined with the second inverse input of the seventh element And and the direct input of the sixth element And, the output of which is connected to the information input of the fourth trigger, whose inverse enable input is connected to the output of the seventh element And, and the output is the first output of the control unit, and the output of the fifth OR element is connected to direct output of the tenth element And, the output of which is connected to the enable input of the register. 7. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the CMND signal conditioning unit comprises a first trigger, a first register, a second register, a first adder, a second adder, a first comparator, a second comparator, a third comparator, a first group of multiplexers, the second group of multiplexers, the element 3 AND-OR, the first element AND, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, the seventh element And, the eighth element And, the first element OR, the second element OR, the third element IL the output of which is connected to the inverse enable input of the second register, the group of outputs of which is the first group of outputs of the group of outputs of the signal conditioning unit CMND, the second group of outputs of which is connected to the group of outputs of the first register, the information inputs of which are connected to the group of outputs of the first group of multiplexers, the first group of inputs which is connected to the first groups of inputs of the first and second adders, the second and third comparators, with the first group of inputs of the second group of multiplexers and is gray by my group of inputs of the CMND signal conditioning unit, the first output of which is connected to the first input of the 3-OR element and the output of the first trigger, the information input of which is connected to the output of the 3I-OR element, the second input of which is connected to the "power", the third input of which is connected to " case ", the first and second enable inputs of which are connected to the outputs of the first and second OR elements, the first input of the second OR element is connected to the sixth AND element, the inverse input of which is connected to the output of the second comparator and the first input of the quadrupole the And element, the output of which is connected to the first input of the first OR element, the second input of which is connected to the output of the fifth And element, the first input of which is connected to the direct input of the seventh element And the output of the third And element, the first input of which is connected to the inverse enable input of the 3I- element OR, by the direct input of the second AND element, it is the first input of the CMND signal conditioning unit, the first group of inputs of which is connected to the second group of inputs of the first adder, with the first group of inputs of the first comparator and with the inverse group the input of the second adder, the group of outputs of which is connected to the second group of inputs of the third comparator, the output of which is connected to the second input of the fifth element AND and the inverse input of the seventh element And, the output of which is connected to the second input of the second element OR, the second group of inputs of the CMND signal conditioning unit connected to the first, second and third inverse inputs of the first element And, the output of which is connected to the enable input of the trigger, the clock and reset inputs of which are connected to the clock and reset inputs the first and second registers and are the clock and reset inputs of the CMND signal conditioning unit, the third group of inputs of which is connected to the second group of inputs of the first group of multiplexers, the enabling input of which is connected to the enabling input of the second group of multiplexers and is the first signal of the sixth group of inputs of the CMND signal generating unit, the fourth group of inputs of which is connected to the second group of inputs of the second group of multiplexers, the group of outputs of which is connected to the information inputs of the second register, the first group of inputs of the signal conditioning unit CMND is connected to the second and inverse groups of inputs of the second and first adders, respectively, and to the second group of inputs of the first comparator, the output of which is connected to the second input of the third element And with the inverse input of the second element And, the output of which is connected to the direct input the sixth element And and the second input of the fourth element And, the second input of the signal conditioning unit CMND is connected to the inverse input of the third element OR and the direct input of the eighth element And, the output of which is connected to By the pit input of the third OR element and with an inverse enable input of the first register, the third input of the signal conditioning unit CMND is connected to the inverse input of the eighth AND element, and the group of outputs of the first adder is connected to the second group of inputs of the second comparator. 8. The electronic device of the ejection seat for an aircraft according to claim 1, characterized in that the MASK signal conditioning unit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a ninth trigger, and a first register, second register, first adder, second adder, first comparison scheme, second comparison scheme, first OR element, second OR element, third OR element, fourth OR element, first AND element, second AND element, third AND element, fourth AND element , at the path of which is connected to the enable input of the ninth trigger, the output of which is the second output of the MASK signal conditioning unit, the group of outputs of which consists of three signals: the first signal is connected to the output of the fifth trigger, the second signal is connected to the information and enable inputs of the fifth and eighth triggers and the output of the second trigger, the third signal is connected to the first inputs of the first and fourth elements And, with the direct input of the second element And and the output of the eighth trigger, the information input of which is connected to the information the input of the sixth trigger and the output of the seventh trigger, the enable input of which is connected to the output of the fourth trigger and is the first output of the signal conditioning unit MASK, the first group of inputs of which is connected to the first group of inputs of the first comparison circuit, the output of which is connected to the second input of the fourth AND element and inverse the input of the first element And, the output of which is connected to the enable input of the first adder, the group of outputs of which is connected to the information group of inputs of the first register, the group of outputs of which connected to the second group of inputs of the second comparison circuit and the group of inputs of the first adder, the second group of inputs of the signal conditioning unit MASK connected to the inverse inputs of the first, second, third and fourth elements OR, the outputs of which are connected to the information inputs of the first, second, third and fourth triggers respectively, the clock and reset inputs of which are connected to the clock and reset inputs of the fifth, sixth, seventh, eighth and ninth triggers, with the clock and reset inputs of the first and second the registers and are the clock and fault inputs of the MASK signal conditioning unit, the third group of inputs of which is connected to the first group of inputs of the first comparison circuit, the output of which is connected to the inverse input of the second element And and the first input of the third element And, the output of which is connected to the second input of the first element And and the third input of the fourth element And, and the output of the first trigger is connected to the information input of the ninth trigger, the output of the third trigger is connected to the enable input of the sixth trigger, the output of which is connected is connected with the second input of the third element And, moreover, the group of outputs of the second register is connected to the second group of inputs of the first comparison circuit and the group of inputs of the second adder, the group of outputs of which is connected to the information group of inputs of the second register, and the input allows the output of the second element And, the information input of the seventh trigger connected to the "power". 9. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the parameter selection node comprises counters, a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register , counter control unit, first combinational circuit, second combinational circuit, third combinational circuit, fourth combinational circuit, fifth combinational circuit, sixth combinational circuit, seventh combinational circuit, adder, multi group plexors, the first element And, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, the OR element, the output of which is connected to the inverse input of the adder, the group of outputs of which is connected to the first group of inputs of the group of multiplexers, group of outputs which is connected to the information group of the fifth register, the group of outputs of which is connected to the group of inputs of the sixth AND element, with the group of inputs of the OR element and is the first signal of the third group of outputs of the parameter selection node, the group of outputs of which connected to the first group of outputs of the counter node, the second group of outputs of which is the fourth group of outputs of the parameter selection node, the first group of outputs of which is connected to the group of outputs of the first register, the first and second groups of inputs of which are connected to the first and second groups of inputs of the parameter selection node, the second group the outputs of which consists of groups of outputs from the third, fourth, seventh and ninth registers, the third group of inputs of the parameter selection node is connected to the group of inputs of the first combinational circuit, the first the second, second and third outputs of which are connected to the first, second and third inputs of the first register, the first signal of the fourth group of inputs of the parameter selection node is connected to the first inputs of the second, third, fifth and seventh combinational circuits, with inverse inputs of the fourth and sixth combinational circuits and the first the input of the counter node, the second input of which is connected to the second inputs of the second, third, fifth and seventh combination circuits, with direct and inverse inputs of the fourth combination circuit, with a direct input of the sixth combination circuit with inverse inputs of the first, fourth and fifth AND elements, with the first input of the OR element, and is the second signal of the fourth group of inputs of the parameter selection node, the fifth group of inputs of which is connected to the first groups of inputs of the third and seventh combination circuits, the first and second outputs of the seventh combinational circuits are connected to the first and second inputs of the ninth register, the sixth group of inputs of the parameter selection node is connected to the first groups of inputs of the second, fourth and sixth combinational circuits and the second register m, with the second groups of inputs of the third and seventh combinational circuits, with the first group of inputs of the counter node, signals F1_V, F1_Vd, F1_Rec and the group of inputs F1_q of the sixth group of inputs are connected to the information input of the third register, the first and second inputs of the second and third elements And and direct the input of the fourth element And, with the group of inputs of the fifth combinational circuit and the group of inputs of the sixth register, respectively, the seventh group of inputs of the node of the selection of parameters is connected to the second groups of inputs of the group of multiplexers and the node of counters and the reset inputs of which are connected to the clock and reset inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth registers and are the clock and reset inputs of the parameter selection node, the first, second and third outputs of the second combinational circuit connected to the first second and third inputs of the second register, the group of outputs of which is connected to the third group of inputs by a third combinational circuit, the third and fourth inputs of which are connected to the first and second outputs of the second register, the group of outputs and the output of the third combinational circuit are connected to the group of inputs and the input of the fourth register, the output of the second element And is connected to the direct input of the first element And, the output of which is connected to the enable input of the third register, the output of the fourth element And is connected to the second input of the OR element, the first, the second and third outputs of the fourth combination circuit are connected to the first, second and third inputs of the sixth register, the first, second and third outputs of which are connected to the third, fourth and fifth inputs of the fifth combination th circuit, the first and second outputs of which are connected to the first and second inputs of the seventh register, the first, second and third outputs of the sixth combinational circuit are connected to the first, second and third inputs of the eighth register, the first, second and third outputs of which are connected to the third, fourth and the fifth inputs of the seventh combination circuit, and the output of the third element And connected to the direct input of the fifth element And, the output of which is connected to the control input of the group of multiplexers. 10. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the counter assembly comprises a first combinational circuit, a second combinational circuit, a first adder, a second adder, a third adder, a fourth adder, a fifth adder, a sixth adder, a seventh adder, a first multiplexer group, second multiplexer group, third multiplexer group, fourth multiplexer group, fifth multiplexer group, sixth multiplexer group, first register, second register, third register, fourth p register, fifth register, sixth register, seventh register, trigger and AND element, the output of which is connected to the information input of the trigger, the output of which is the first signal of the first group of outputs of the counter node, the group of outputs of which is connected to the group of inputs of the element And, with the group of inputs of the seventh adder and a group of outputs of the seventh register, the information group of inputs of which is connected to the group of outputs of the second combinational circuit, the output of which is connected to the enable input of the seventh register and with the inverse input of the seventh sum ora, whose output is connected to the input of the combinational circuit, the first group of inputs of which is connected to the group of inputs of the first combinational circuit and is the first group of inputs of the counter node, the second group of outputs of which is connected to the second, third, fourth, fifth, sixth and seventh groups of inputs of the second combinational circuits with groups of inputs of the first, second, third, fourth, fifth and sixth adders and with groups of outputs of the first, second, third, fourth, fifth and sixth registers, the information inputs of which are connected inens with output groups of the first, second, third, fourth, fifth and sixth groups of multiplexes, the first groups of inputs of which are interconnected and are the second group of inputs of the counter node, the fourth group of inputs of which are connected to the first and second inputs of the first combinational circuit, the first, second , the third, fourth, fifth and sixth outputs of which are connected to the inverse inputs of the first, second, third, fourth, fifth and sixth adders, the output groups of which are connected to the second groups of inputs of the first, second, third x, fourth, fifth and sixth groups of multiplexers, the control inputs of which are connected to the seventh, eighth, ninth, tenth, eleventh and twelfth outputs of the first combinational circuit, respectively, and the clock and reset inputs of the counter node are connected to the clock and inverse reset inputs of the first, second, third, fourth, fifth, sixth, seventh registers and trigger. 11. The electronic device of the ejection seat for an aircraft according to claim 1, characterized in that the ZBV (bar-time bolt) assembly comprises a first counter, a second counter, a third counter, a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, and a sixth trigger , seventh flip-flop, eighth flip-flop, ninth flip-flop, tenth flip-flop, first delay shaper FZ1, second delay shaper FZ1, first delay shaper FZ2, second delay shaper FZ2, third delay shaper FZ2, fourth delay shaper FZ 2, delay driver FZ3, first OR element, second OR element, third OR element, fourth OR element, fifth OR element, sixth OR element, seventh OR element, first AND element, second AND element, third AND element, fourth AND element, the fifth element And, the sixth element And, the output of which is the output of the ZBV node, the first group of inputs of which is connected to the direct input of the first OR element (first CM signal), with the direct input of the second OR element (second signal DX), with the eighth input of the second delay driver FZ1 (third signal SH_S), with direct the course of the first element And, with the first input of the second element And, with eight inputs of the third and fourth formers delay FZ2 (fourth signal B_M), with the inverse and second input of the first and second elements And (fifth signal M_M), the output of the first element And is connected to the eighth the inputs of the first and second delay drivers FZ1 and FZ2, the output of the second element And is connected to the eighth inputs of the first delay driver FZ2 and the delay driver FZ3, the input groups of which are connected to the input groups of the first and second delay drivers FZ1, of the second, third and fourth delay drivers FZ2 and a group of outputs of the third counter, the clock input of which is connected to the first inputs of the first and second delay drivers FZ1, the first, second, third and fourth delay drivers FZ2 and the delay driver FZ3, with the clock input of the second counter and the output the first counter, the clock input of which is connected to the inverse clock input of the eighth trigger and is the first input of the ZBV node, the first input of the sixth element And is connected to the reset input of the third counter and you ode of the tenth trigger, whose inverse clock input is connected to the output of the seventh OR element, the direct input of which is connected to the output of the ninth trigger, the information input of which is connected to the “power”, with the enable input of the third counter with information inputs of the seventh and tenth triggers, whose inverse reset input connected to the inverse dump inputs of the seventh, eighth and ninth triggers, with the inverse inputs of the first and second elements OR, with the reset input of the first counter and is the second input evil ZBV, the third input of which is connected to the first inverse input of the fourth AND element, whose output is connected to the first input of the sixth OR element, the output of which is connected to the second input of the sixth AND element, the fourth input of the ZBV node connected to the inverse input of the fifth AND element and the second the inverse input of the fourth AND element, the direct input of which is connected to the output of the fourth OR element, the first, second and third inputs of which are connected to the outputs of the first delay driver FZ1, the first and third delay drivers FZ2 with accordingly, the second and fourth delay drivers FZ2 and the delay driver FZ3 are connected to the inputs of the fifth OR element, the output of which is connected to the direct input of the fifth AND element, the output of which is connected to the second input of the sixth OR element, the third input of which is connected to the output of the second delay driver FZ1, moreover, the second output of the first counter is connected to the clock inputs of the first, second, third, fourth, fifth and sixth flip-flops, the installation inputs of which are connected to the outputs of the first and second elements OR, p what with the “case” are connected the information inputs of the first and second triggers, the outputs of which are connected to the information inputs of the third and fourth triggers, the outputs of which are connected to the information inputs of the fifth and sixth triggers, the outputs of which are connected to the inverse clock input of the seventh trigger and the inverse input of the seventh OR element accordingly, the output of the eighth trigger is connected to the clock input of the ninth trigger and the inverse enable input of the second counter, the output of the seventh trigger is connected to the inverse reset gaussian input of the second counter group whose output is connected to inputs of the third group element and the first OR input of the third AND gate, a second input coupled to an output of the third OR gate, and an output coupled to the data input of the eighth flip-flop. 12. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the delay driver FZ1 comprises a first trigger, a second trigger, a first OR-NOT element, a second OR-NOT element, a first AND element, a second AND element, the output of which is connected with the information input of the first trigger, the output of which is connected to the clock input of the second trigger, the output of which is the output of the delay driver FZ1, the group of inputs of which is connected to the input groups of the first and second elements OR-NOT and the first element AND, the outputs of which They are the inputs and the second element, wherein the first input FZ1 delay generator connected to the clock input of the first flip-flop reset input of which is the eighth input of the delay FZ1 and connected to the reset input of the second flip-flop having an information input coupled to "power". 13. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the delay driver FZ2 comprises a first trigger, a second trigger, an OR-NOT element, a first element And, a second element And and a third element And, the output of which is connected to the information input the first trigger, the output of which is connected to the clock input of the second trigger, the output of which is the output of the delay driver FZ2, the group of inputs of which is connected to the groups of inputs of the first and second elements AND and the element OR-NOT, the outputs of which are inputs retego AND gate, the first input FZ2 delay generator connected to the clock input of the first flip-flop reset input of which is the eighth input of the delay FZ2 and connected to the reset input of the second flip-flop having an information input coupled to "power". 14. The electronic device of the ejection seat for an airplane according to claim 1, characterized in that the delay driver FZ3 comprises a first trigger, a second trigger, an OR-NOT element, a first element AND, a second element And and a third element And, the output of which is connected to the information input the first trigger, the output of which is connected to the clock input of the second trigger, the output of which is the output of the delay driver FZ3, the group of inputs of which is connected to the groups of inputs of the first and second elements AND and the element OR NOT, the outputs of which are inputs retego AND gate, the first input FZ3 delay generator connected to the clock input of the first flip-flop reset input of which is the eighth input of the delay FZ3 and coupled to reset input of the second flip-flop having an information input coupled to "power".

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