RU2649622C1 - Ferroelectric memory cell - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to the field of devices of non-volatile memory based on the phenomenon of ferroelectricity with destructive readout, to which stringent requirements are applied for the resource, retention time and energy intensity. Invention is based on a cell of ferroelectric memory. Technical result is achieved by using an additional overlap between the layers of the lower electrode and the ferroelectric and the ferroelectric and the upper electrode.

EFFECT: technical result of this invention is to create a ferroelectric memory cell with a simplified and more reliable design that can be used to create large capacity memory circuits.

3 cl, 5 dwg

Description

Technical field

The invention relates to the field of non-volatile memory devices based on the phenomenon of ferroelectricity (FeRAM, ferroelectric random access memory).

State of the art

A device for ferroelectric memory based on PZT, which is an analogue, which is proposed in the patent T. Noda - Ferroelectric memory device and method for manufacturing the same // US Patent, Pub. No. US 2009/0127604, (2009) [1]. This device includes:

a substrate;

a ferroelectric capacitor formed above the substrate and consisting of two electrodes and a ferroelectric layer;

a first barrier layer that insulates the ferroelectric capacitor;

an interlayer dielectric formed after the first barrier layer;

and metal wiring electrically connected to the upper electrode of the memory cell.

The metal wiring also includes two barrier layers and directly a metal layer formed after these barrier layers.

The disadvantages of this device is the excessive complexity of the technology for creating this design, which consists in the use of additional barrier layers and a larger number of lithographs; poor processability of the PZT material, which is used as a ferroelectric layer; the high cost of one bit of information and the low memory density, which are the result of the first two drawbacks.

As a prototype, a ferroelectric memory cell, proposed in T. Boscke's patent - Integrated circuit including a ferroelectric memory cell and method of manufacturing the same // US Patent, Pub. No. US 2009/0261395, (2009) [2].

The ferroelectric memory cell proposed in the patent includes a substrate, a transistor, and a storage element in which there is: an oxide layer that is at least partially crystallized and contains oxygen and at least hafnium or zirconium; upper and lower electrodes.

The main disadvantage of the prototype, which is eliminated by the invention, is the excessive complexity of the technology for creating a memory cell. This unnecessary complexity is due to the fact that after creating the layers of the lower electrode, oxide and upper electrode, a number of basic technological operations must be performed on the resulting stack, such as: etching of the composite stack lower electrode / oxide / upper electrode (hereinafter “storage element"), deposition dielectric (usually silicon oxide), chemical-mechanical polishing of the dielectric (CMP) to smooth the relief, deposition of the dielectric, etching of transition windows, deposition of a Ti / TiN layer on the surface of the windows, subsequent filling of tungsten, followed by chemical-mechanical polishing of tungsten for forming bumps in transient oknahpered so as to start forming the subsequent metallization layers needed for the electrical connection elements of the integrated circuit. At the same time, the number of lithographs does not increase (remains). In the prototype: a stack, transition windows, metal wiring. In the invention: lower electrode, ferroelectric layer, upper electrode and metal wiring (at the same time).

Another disadvantage of the prototype is that with a decrease in the thickness of the ferroelectric layer, the reliability of the storage element during the etching operation of the composite stack decreases. When etching such a stack, there is the possibility of leaks and shorting along the side surface of the stack between the lower and upper electrodes. The invention eliminates the possibility of leaks and shorting along the side surface of the stack due to the spacing of the side surface of the lower electrode, the ferroelectric layer, the upper electrode (by using overlaps between the ferroelectric and the electrodes).

Disclosure of invention

The objective of the invention is to create a cell ferroelectric memory with a simplified and more reliable design, which can be used to create memory circuits of large capacity.

The problem is solved due to the fact that in the cell of the ferroelectric memory, including the substrate, a sampling transistor and a storage element in which there is: a lower electrode of titanium nitride; an oxide layer that is at least partially crystallized and contains oxygen and at least hafnium or zirconium; the upper electrode of titanium nitride, the following difference is provided: the oxide layer overlaps the region of the formed lower electrode, isolating it from the upper electrode, and the upper electrode of titanium nitride with a layer of metal wiring located on it overlaps the region of the formed oxide so as to completely isolate the oxide layer from the overlying metal wiring layer.

In addition, the oxide layer may contain combinations of hafnium with the following elements: zirconium, silicon, aluminum, magnesium, gadolinium, yttrium, lanthanum in a percentage ratio from 0.5% to 50% with respect to the concentration of hafnium.

Also, aluminum wiring can be used as metal wiring.

Due to the overlap between the ferroelectric and the electrodes, it becomes possible to form a metal wiring simultaneously with the top electrode of the storage element (one lithography is used). The invention eliminates the possibility of leaks and shorting along the side surface of the stack due to the spacing of the side surface of the lower electrode, the ferroelectric layer, the upper electrode (by using overlaps between the ferroelectric and the electrodes). In this case, the cell area increases slightly ~ 20%.

This difference allows to increase the reliability of the design, avoiding possible leaks and shorts along the side surface of the storage element, as well as to simplify the technology in terms of the formation of the storage element and metal wiring, namely:

- allows not to use the operation of the etching of the composite stack, and to individually etch the layers of the lower electrode, the ferroelectric layer and the upper electrode together with the metal wiring;

- allows you to form a subsequent metallization layer combined with the top electrode of titanium nitride without additional operations, such as: deposition of a dielectric (usually silicon oxide), chemical-mechanical polishing of a dielectric (CMP) to smooth the relief, deposition of a dielectric, etching transition windows, deposition of a Ti / TiN layer on the surface of the windows, their subsequent filling with tungsten, followed by chemical-mechanical polishing to form tungsten columns in the transition windows.

In connection with the foregoing, the invention allows to achieve improved manufacturability and reliability, as well as a high level of yield while maintaining a high integration density of non-volatile memory circuits.

Brief Description of the Drawings

The technical nature and principle of operation of the proposed device are illustrated by drawings:

FIG. 1 - Lateral section of a memory cell FRAM 1T-1C

FIG. 2 - A fragment of a side section with an enlarged scale

FIG. 3 - Sketch of the topology of the transistor without a storage element (the main layers are shown)

FIG. 4 - Sketch of the topology of the memory cell 1T-1C (main layers are shown).

FIG. 5 - Dependence of the value of the polarization vector on the applied voltage.

The implementation of the invention

We will demonstrate the possibility of implementing the claimed invention by considering an example of a memory cell in which hafnium oxide with zirconium (chemical formula Hf _0.5 Zr _0.5 O ₂ ) is used as a ferroelectric, and titanium nitride (chemical formula TiN) as electrodes.

The design of the 1T-1C topology ferroelectric memory cell consists of a silicon substrate, a sampling transistor, which is formed in the substrate, and a storage element, which is a ferroelectric capacitor and formed after the sampling transistor in metallization layers.

In FIG. 1 is a side sectional view illustrating a structure of a memory cell.

To form the ferroelectric memory, a silicon substrate 1 with an orientation <100> and an epitaxial layer 2 is used. In this substrate, STI-isolation regions (gap insulation) are formed 5. Then a p-pocket 3 is formed to create an n-channel transistor and an n-pocket in it 4 to create a p-channel transistor.

Next, a layer of gate dielectric 10 is applied. As a gate gate dielectric, a layer of silicon oxide is used with a thickness of 3 nm to 10 nm (the thickness varies for different transistors). After that, a polysilicon layer 13 is formed, which is a gate of the transistor. To reduce the effect of hot carriers, p-type 8 and n-type 9 LDD regions are created in the transistor channel.

Then there is the creation of a spacer 11 for lateral isolation of the shutter. Then, in the p-pocket 3, n + drain-source regions 6 are created, and in the n-pocket 4, p + drain-source regions 7. Then, the structure is silicidized 12, covered with dielectric 15 and contact windows 14 are formed. The side walls and the bottom of the windows are coated Ti / TiN, and then the windows are filled with tungsten. In this case, the formation of the dielectric 15, the windows and their filling with tungsten occurs sequentially in two stages.

After that, the plate undergoes chemical-mechanical polishing to smooth the relief for the subsequent formation of layers of metal wiring.

At this stage, the so-called FEOL (front-end) transistor production cycle is completed. Integration with the memory element will occur in the BEOL cycle (back-end), that is, at the stage of creating metallization layers.

One or more metallization layers may be used to form the electrical wiring. If there is no need for metallization layers between the ferroelectric capacitor and the sampling transistor, then the capacitor can be formed immediately after creating contact windows to the transistor.

In FIG. 1 shows an example of a cell in which 2 metallization layers were used between the memory element and the sampling transistor. 16, 19 and 24 - aluminum metallization, 17, 20 and 25 - interlayer dielectrics, 18 - transition windows filled with tungsten.

In FIG. Figure 2 shows a fragment of a side section of an enlarged memory cell.

Layers 21, 22 and 23 - are a ferroelectric capacitor. 21 is a lower electrode made of titanium nitride, which can be applied both by magnetron sputtering, atomic layer deposition or vapor deposition.

22 is a ferroelectric layer that is grown by atomic layer deposition from organometallic precursors of hafnium (tetrakis (ethylmethylamino) hafnium, denoted as TEMAN) and zirconium (tetrakis (ethylmethylamido) zirconium, denoted as TEMAZ). The ferroelectric layer can be grown using chemical vapor deposition methods. The ferroelectric may be oxides of various transition metals and combinations of these oxides. The oxide layer may contain combinations of hafnium with the following elements: zirconium, silicon, aluminum, magnesium, gadolinium, yttrium, lanthanum in a percentage ratio of 0.5% to 50% with respect to the concentration of hafnium.

This layer acts not only as a ferroelectric, but also reliably isolates the electrodes from each other, due to the overlap relative to the lower electrode.

It is possible to grow this layer using chemical vapor deposition methods.

23 - the upper electrode of the ferroelectric capacitor. The electrode consists of titanium nitride and can be deposited by vapor deposition followed by annealing of the structure or by atomic layer deposition with automatic annealing, as shown in [3]. Annealing is necessary for the formation of a noncentrally symmetric orthorhombic phase, which possesses the necessary ferroelectric properties.

After the ferroelectric capacitor is created, the wiring is done with a layer of metal 24, a well-conducting material, for example, aluminum, is used as the metal. Particular attention should be paid to the fact that metallization 24 is created in the same lithography with the upper electrode of the memory element.

In FIG. Figure 3 shows a sketch of the topology of the sampling transistor for the proposed memory cell. Pocket 1 is a doped region in which drain-source regions 2 are formed. Above the channel lies a dielectric layer on which is located a layer of a control gate 3 made of polysilicon or another metal. Transition windows are created in the area above the drain to provide electrical contact between the drain of the transistor and the lower electrode of the storage element.

In FIG. 4 shows a sketch of the topology of a memory cell with a sampling transistor and a storage element. Regions 1, 2 and 3 correspond to FIG. 3. The lower electrode 4 is formed above the drain, transition windows and underlying metallization are not shown. With overlapping relative to the lower electrode 4, a ferroelectric 5 is deposited, and then with an additional overlapping, the upper electrode 6 is formed. The metallization, which is used for wiring, repeats the contours of the upper electrode, as it is done in the same lithography with the electrode.

The ferroelectric memory cell described above works as follows:

In the mode of recording / erasing information, the voltage necessary to open the transistor channel is supplied to the gate of the control transistor, thereby providing access to the storage element, the source and substrate are grounded, and a pulse of a given duration and amplitude is supplied to the upper electrode of the storage element write a specific logical state to the storage element. To record various logical states on the plates of a ferroelectric capacitor, a potential difference of different polarity is created.

The selection of cells to be recorded / erased is carried out by the sampling transistor. A voltage opening the channel is applied to the gates of the transistors of the sample of cells of interest to us; voltage is applied to the gates of the transistors of the cells, which should not be reprogrammed, at which the channel of the transistor is closed.

Information is read by supplying a voltage pulse with a predetermined sign to the upper electrode of the storage element and detecting the current pulse through the cell. In this case, if the direction of the external electric field coincides with the direction of the polarization vector in the cell, then when a current pulse is detected through the memory cell, a value close to zero will be recorded. If the electric field and the polarization vector in the cell are directed in opposite directions, then when reading the memory cell will be re-polarized and a current pulse different from zero will be detected.

Based on the presence or absence of a current pulse when reading information from a cell, we can say in what initial state the cell was in before the read operation. However, after the read operation, the cell will definitely be in the state of a logical unit (or logical zero, depending on the polarity of the read voltage). This method of reading is called destructive, because when reading information, the initial state changes and corresponds to the voltage pulse used for the read operation.

Information is stored in the absence of external applied voltage, therefore this type of memory is called non-volatile.

Technical characteristics of the proposed cell ferroelectric memory:

In FIG. Figure 5 shows the dependence of the polarization vector on the applied voltage for a memory cell with the following characteristics:

- as a ferroelectric layer of hafnium oxide with zirconium is used - Hf _0.5 Zr _0.5 O ₂ ;

- lateral dimensions of the ferroelectric capacitor 2 × 2 μm ² ;

- the thickness of the ferroelectric layer is 10 nm;

- the electrodes are made of titanium nitride TiN;

- the upper electrode is formed with aluminum wiring using a single lithography.

The graph shows that for this cell, the write voltage is 2.5 V, while the residual polarization, which defines the memory window, is 20 μC / cm ² . This means that when overwriting a bit of information, a current pulse of 800 fC will flow through a cell of this size. This level obviously exceeds modern circuitry capabilities for detecting a current pulse, which allows us to conclude that this cell can be used in high-capacity memory circuits.

Bibliography

[1] T. Noda - Ferroelectric memory device and method for manufacturing the same // US Patent, Pub. No. US 2009/0127604 (2009).

[2] T. Boscke - Integrated circuit including a ferroelectric memory cell and method of manufacturing the same // US Patent, Pub. No. US 2009/0261395 (2009).

[3] A. Chernikova, et al. - Confinement-free annealing induced ferroelectricity in Hf _0.5 Zr _0.5 O ₂ thin films // Microelectronic Engineering, vol. 147, pp. 15-18 (2015).

Claims (3)

1. A ferroelectric memory cell, which includes a substrate, a sampling transistor and a storage element in which a lower electrode of titanium nitride is present; an oxide layer that is at least partially crystallized and contains oxygen and at least hafnium or zirconium; a titanium nitride upper electrode, characterized in that in the storage element the oxide layer overlaps the region of the formed lower electrode, isolating it from the upper electrode, and the titanium nitride upper electrode with the metal wiring layer located on it overlaps the region of the formed oxide so as to completely isolate the layer oxide from the overlying metal wiring layer. 2. A ferroelectric memory cell according to claim 1, characterized in that the oxide layer may contain hafnium combinations with the following elements: zirconium, silicon, aluminum, magnesium, gadolinium, yttrium, lanthanum in a percentage ratio of 0.5% to 50% with respect to to hafnium concentration. 3. A ferroelectric memory cell according to claim 1, characterized in that aluminum wiring can be used as a metal wiring.

Images