RU2624587C1 - Device for multiplying number by module - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device contains: two AND elements, three OR elements, a decoder, a register, a switch, five groups of AND elements, five encoders, a digital comparator, a NO element, and communications between them.

EFFECT: expanding the functionality of the device through the implementation of both commutative and non-commutative operations.

2 dwg, 2 tbl

Description

The invention relates to the field of automation and computer engineering and can be used in computing structures operating in a modular number system.

A device (analog) is known (ed. St. USSR No. 1716511, MKI G06F 7/72, B.I. No. 8, 1992), containing a group of blocks of AND elements, a group of blocks of multiplication by a constant modulo, two blocks of OR elements , decoder, group of OR elements, OR element, two blocks of AND elements, NOT element and code converter. The disadvantage of this device is its low functionality.

A device (analogue) is also known (RF patent No. 2143723, MKI G06F 7/52, 7/72, B.I. No. 36, 1999), containing two converters of the binary code of a number into a unitary code according to the first internal module of the device, two a converter of a binary code of a number to a unitary code according to the second internal module of the device, two converters of a unitary code of a number to a binary positional code, six blocks of AND elements, an adder modulo the device. The disadvantage of this device is its low functionality.

The closest in technical essence (the prototype of the alleged invention) is a device (ed. St. USSR No. 1667055, MKI G06F 7/49, 7/72, B.I. No. 28, 1991) containing five elements And, two elements OR, a decoder, two groups of elements OR, two groups of elements AND, a switch, a register, an encoder, two triggers and an adder modulo two.

The disadvantage of the prototype is low functionality due to the fact that only a commutative operation is implemented.

The technical problem, the solution of which the claimed device is directed, consists in the unification of promising samples of computer technology.

The technical result is expressed in expanding the functionality of the device.

The technical result is achieved in that the device containing the first and second elements AND, the first OR element, a decoder, a register, a switch and a first encoder, and the inputs of the first and second operands of the device are connected respectively to the first inputs of the first and second elements And, the second inputs of which are connected respectively, with the first and second control inputs of the device, and the outputs, respectively, with the first and second inputs of the first OR element, the output of which is connected to the decoder input, and the register outputs are connected to the corresponding the existing inputs of the switch, it is distinguished by the fact that a digital comparator, five groups of AND elements, the second and third elements of OR, the second, third, fourth and fifth encoders and the element NOT are introduced into it, the decoder output connected to the register input, the first group of switch outputs connected with the first inputs of the corresponding elements And the first and third groups, the second inputs of which are connected to the output of "Equal" digital comparator, the first and second inputs of which are connected respectively to the first and second control inputs of the device two, the second group of outputs of the switch is connected to the first inputs of the corresponding elements AND of the second, fourth and fifth groups, the second inputs of which are connected to the output “Less” of the digital comparator, the output “More” of which is connected to the second inputs of the elements And the fourth group, the outputs of the elements And the first , the second, third, fourth and fifth groups are connected to the corresponding inputs of the first, second, third, fourth and fifth encoders, respectively, the output of "Equal" digital comparator through the element is NOT connected to the second input MI elements of the second group, the outputs of the first and second encoders are connected to the first and second inputs of the second OR element, respectively, the output of which is the first output of the device, the outputs of the third, fourth and fifth encoders are connected to the first, second and third inputs of the third element, respectively, the output which is the second output of the device.

In FIG. 1 presents a structural diagram of the proposed device.

In FIG. Figure 2 shows the switch diagram (for m = 5, where m is the operation module).

.Table 1 shows the results of the operation

.

, где x - результат операции 0⁰, т.е. неопределенность.Table 2 shows the results of the operation

, where x is the result of operation 0 ⁰ , i.e. uncertainty.

отличается симметрией относительно левой диагонали по сравнению с таблицей 2 для модулярной операции

(некоммутативной операции), где А и В - операнды, а m=5 - модуль операции.The invention consists in the following. The imposition of unitary codes of operands A and B (we call this representation the unitary code of a binary operation) can be unambiguously mapped to the result of a commutative operation, as was done in the prototype. For non-commutative operations, the spatial dependence of the result of the operation on the rearrangement of its elements in the proposed device is replaced by an analysis of the temporal order of their sequence. At the same time, it becomes possible to simultaneously conduct two types of binary operations (commutative and non-commutative) using the same basic nodes of the device. Considering tables 1 and 2, it can be noted that table 1 for operation

differs in symmetry with respect to the left diagonal in comparison with table 2 for the modular operation

(non-commutative operation), where A and B are operands, and m = 5 is the operation module.

. Тогда для А=3 и В=2 наложение унитарных кодов имеет вид:Let's consider simple examples. Let the operation be necessary

. Then for A = 3 and B = 2 the imposition of unitary codes has the form:

0-1-1-0-0.

The result of the corresponding operation has the representation:

0-0-0-1-0.

для А=3 и В=2 (А=2 и В=3) наложение унитарных кодов имеет вид:It will not change if A = 2 and B = 3. For modular operation

for A = 3 and B = 2 (A = 2 and B = 3), the imposition of unitary codes has the form:

0-1-1-0-1,

and the result of the operation in the first case:

1-0-0-0-0,

and in the second:

0-1-0-0-0.

Due to the fact that in the circuit of FIG. 1 are used to implement various operations common elements, then increases the unification of the device.

Presented in FIG. 1 structural diagram of the proposed device contains: 1 - input of the first operand, 2 - input of the second operand, 3 - the first element And, 4 - the second element And, 5 - the first control input, 6 - the second control input, 7 - the first element OR, 8 - decoder, 9 - register, 10 - switch, 11 - first group of AND elements, 12 - third group of AND elements, 13 - digital comparator, 14 - second group of AND elements, 15 - fourth group of AND elements, 16 - fifth group of AND elements 17 — first encoder, 18 — second encoder, 19 — third encoder, 20 — fourth encoder, 21 — fifth encoder, 22 — element NOT, 23 - the second OR element, 24 - the first output of the device, 25 - the third OR element, 26 - the second output of the device.

- выходы разрядов регистра, 28_i - первая группа выходов коммутатора, 29_j

- элементы И, 30_j - вторая группа выходов коммутатора.Presented in FIG. 2 diagram of switch 10 (for m = 5) contains: 27 _i

- outputs of the bits of the register, 28 _i - the first group of outputs of the switch, 29 _j

- elements And, 30 _j - the second group of outputs of the switch.

The inputs of the first 1 and second 2 operands are connected respectively to the first inputs of the first 3 and second 4 AND elements, the second inputs of which are connected respectively to the first 5 and second 6 control inputs of the device, and the outputs are respectively to the first and second inputs of the first 7 OR element, output which is connected to the input of the decoder 8, the output of which is connected to the input of the register 9, the outputs of which are connected to the corresponding inputs of the switch 10, the first group of outputs of which is connected to the first inputs of the corresponding elements AND first 11 and the third 12 groups, the second inputs of which are connected to the output of "Equal to" the digital comparator 13, the first and second inputs of which are connected respectively to the first 5 and second 6 control inputs of the device, while the second group of outputs of the switch 10 is connected to the first inputs of the corresponding elements the second 14, fourth 15 and fifth 16 groups, the second inputs of which are connected to the output “Less” of the digital comparator 13, the output “More” of which is connected to the second inputs of the elements And the fourth 15 groups, the outputs of the elements And the first 11, second 14, 12, fourth 15 and fifth 16 groups are connected to the corresponding inputs of the first 17, second 18, third 19, fourth 20 and fifth 21 encoders, respectively, the output of "Equal" digital comparator 13 through the element NOT 22 is connected to the second inputs of the elements And the second 14 groups , the outputs of the first 17 and second 18 encoders are connected to the first and second inputs of the second 23 OR element, the output of which is the first 24 output of the device, the outputs of the third 19, fourth 20 and fifth 21 encoders are connected to the first, second and third inputs of the third 25 element respectively, the output of which is the second 26 output of the device.

Consider the operation of the device. Before starting work, all the bits of the register 9 are set to zero. At the inputs 1 and 2, the input operands in binary code go to the first inputs of the corresponding elements And 3 and And 4. At the first control input 5 of the device receives a signal, and from the output of the element And 3 operand A goes through the first element OR 7 to the input of the decoder 8, the output of which receives a signal at one of the inputs of the register 9. Next, the signal is supplied to the second control input 6 of the device, and operand B likewise passes from the output of the second 4 elements And through the elements considered to one of the inputs of the register 9. Operands A and B also receive on the first and second inputs, respectively, of the digital comparator 13, a signal appears on one of the three outputs (A> B, A = B and A <B). The outputs 27 _{i of the} bits of the register 9 are connected to the corresponding inputs of the switch 10. Three cases are possible depending on the ratio of the operands.

и

поступают в двоичных кодах на первый 24 и второй 26 выходы устройства соответственно.When A = B, the signal from the second output of the digital comparator 13 goes to the second inputs of the first 11 and third 12 groups of elements And, one of the first inputs of which receives a signal from the output of the first group of outputs 28 _{i of the} switch 10 (this group implements the left diagonals of tables 1 and 2). Then through the first 17 and third 19 encoders, and then the second 23 and third 25 elements OR, respectively, the results of operations

and

come in binary codes to the first 24 and second 26 device outputs, respectively.

When A> B, the signal from the first output of the digital comparator 13 goes to the second inputs of the fourth 15 groups of elements And, and through the element NOT 22 to the second inputs of the second 14 groups of elements I. From the output of the second 30 _j group of outputs of the switch 10 (off-diagonal elements of tables 1 are implemented and 2) a signal arrives at one of the first inputs of the second 14 and fourth 15 groups of AND elements, the outputs of which receive a signal at the inputs of the second 18 and fourth 20 encoders. The results of both modular operations are similarly output to the outputs 24 and 26 of the device.

) и на вторые входы пятой 16 группы элементов И (реализуется нижняя часть таблицы 2 относительно первой диагонали для некоммутативной операции

). Также с одного выхода второй 30j группы выходов коммутатора 10 поступает сигнал, и последующие процессы проходят подобно первым двум случаям за исключением того, что результат второй операции

поступает на второй 26 выход устройства через пятый 21 шифратор.When A <B, the signal from the third output of the digital comparator 13 also passes through the element 22 to the second inputs of the second group 14 (the symmetry of table 1 for the commutative operation

) and to the second inputs of the fifth 16 group of AND elements (the lower part of table 2 is implemented relative to the first diagonal for a non-commutative operation

) Also, a signal is received from one output of the second 30j of the group of outputs of the switch 10, and subsequent processes proceed like the first two cases, except that the result of the second operation

arrives at the second 26 device output through the fifth 21 encoder.

поступает через второй 23 элемент ИЛИ на первый 24 выход устройства. Также сигнал с выхода 28₃ поступает на первый вход второго элемента третьей 12 группы, а затем через третий 19 шифратор двоичный код 010₂ результата операции

через третий 25 элемент ИЛИ на второй 26 выход устройства.Example 1. Let A = B = 3. In this case, on the bits of register 9, a unitary code 0-1-0-0-0 is formed. The signal from the output 28 _{3 of the} first group 28 _{i of the} switch 10 is fed to the first input of the fourth AND element of the first 11 group, at the second input of which a signal from the second output (A = B) of the digital comparator 13 is present. Next, the signal is fed to the input of the first 17 encoder, the output of which is binary code 100 _{2 of the} result of a commutative operation

enters through the second 23th OR element to the first 24th output of the device. Also, the signal from the output 28 ₃ goes to the first input of the second element of the third 12 groups, and then through the third 19 encoder binary code 010 _{2 of the} result of the operation

through the third 25th OR element to the second 26th device output.

через второй 23 элемент ИЛИ поступает на первый 24 выход устройства. Сигнал с выхода 30₂ второй группы выходов 30_j коммутатора 10 также поступает на первый вход четвертого элемента четвертой группы 15 элементов И, и далее через четвертый 20 шифратор и третий 25 элемент ИЛИ результат операции

поступает на второй 26 выход устройства.Example 2. Let A = 3, B = 2. In this case, on the bits of register 9, a unitary binary operation code 0-1-1-0-0 is generated. The signal from the output 30 _{2 of the} second group of outputs 30 _{j of the} switch 10 is fed to the first input of the first element of the second group of 14 AND elements, at the second input of which there is a signal from the output of the element NOT 22. Next, the signal goes to the input of the second 18 encoder, the output of which is the result of the operation

through the second 23 element OR goes to the first 24 output of the device. The signal from the output 30 _{2 of the} second group of outputs 30 _{j of the} switch 10 also enters the first input of the fourth element of the fourth group of 15 AND elements, and then through the fourth 20 encoder and the third 25 element OR the result of the operation

goes to the second 26 output of the device.

работа устройства происходит подобным образом, как в предыдущем примере, ввиду коммутативности операции. Для второй операции сигнал с выхода 30₂ второй группы выходов 30_j коммутатора 10 поступает на первый вход третьего элемента пятой группы 16 элементов И. На второй его вход поступает сигнал с третьего выхода (А<В) цифрового компаратора 13, и результат операции

через соответствующие элементы поступает на второй 26 выход устройства.Example 3. Let A = 2, B = 3. For operation

the operation of the device occurs in a similar manner as in the previous example, due to the commutativity of the operation. For the second operation, the signal from the output 30 _{2 of the} second group of outputs 30 _{j of the} switch 10 is fed to the first input of the third element of the fifth group of 16 elements I. At its second input, a signal is received from the third output (A <B) of the digital comparator 13, and the result of the operation

through the corresponding elements, it enters the second 26 output of the device.

The device reflects the development of modular computing structures based on a tabular implementation and shows the way of unification through the union of commutative and non-commutative operations.

Claims (2)

A device for multiplying numbers modulo comprising the first and second AND elements, the first OR element, a decoder, a register, a switch and a first encoder, the inputs of the first and second operands of the device being connected respectively to the first inputs of the first and second AND elements, the second inputs of which are connected respectively with the first and second control inputs of the device, and the outputs, respectively, with the first and second inputs of the first OR element, the output of which is connected to the decoder input, and the register outputs are connected to the corresponding the switch’s moves, characterized in that a digital comparator, five groups of AND elements, the second and third elements of OR, the second, third, fourth and fifth encoders and the element NOT are introduced into it, the decoder output connected to the register input, the first group of switch outputs connected to the first inputs of the corresponding elements And the first and third groups, the second inputs of which are connected to the output of "Equal" digital comparator, the first and second inputs of which are connected respectively to the first and second control inputs of the device, the second the group of outputs of the switch is connected to the first inputs of the corresponding elements AND of the second, fourth and fifth groups, the second inputs of which are connected to the output "Less" of the digital comparator, the output "More" of which is connected to the second inputs of the elements And the fourth group, the outputs of the elements And the first, second, the third, fourth and fifth groups are connected to the corresponding inputs of the first, second, third, fourth and fifth encoders, respectively, the output of "Equal" digital comparator through the element is NOT connected to the second inputs of the element in AND of the second group, the outputs of the first and second encoders are connected to the first and second inputs of the second OR element, respectively, the output of which is the first output of the device, the outputs of the third, fourth and fifth encoders are connected to the first, second and third inputs of the third  element OR, respectively, the output of which is the second output of the device.

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