RU2618941C2 - Correlator - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device comprises an input informational bus of the input signal comprising a mixture of the desired signal, interference and noise with the quasi-harmonic pulse shape, an ADC, a comparison processor, a coincidence counter, a shift register, a ROM, a synchronizer, an authorization scheme.

EFFECT: constructing the correlator for the quasi-harmonic pulses.

2 dwg

Description

The invention relates to electronic equipment and can be used in information transfer systems to determine the correspondence (identity) of the code received from the transmitter, the signal to the code stored in the receiver.

In the general case (from the point of view of theory), a correlator is a device capable of calculating the correlation function between two processes.

The use of correlators in digital communication systems used to transmit information for discrete log states. "Zero" or log. the "unit" implementation of the correlators is classical, see L. Varakin "Communication systems with noise-like signals, M, Radio and Communications, 1985, p. 384.

The problem is the technical implementation of correlators using quasi-harmonic pulses.

There is a theoretical development for the implementation of such a correlator, see ACF RESEARCH OF NOISE-LIKE SIGNALS WITH HARMONIC FORM PULSES WITH SPECTRUM WIDTH LIMITS. Malygin I.V., Komissarova A.V. In the collection: microwave equipment and telecommunication technologies, 25th International Crimean Conference, 2015.

The disadvantage of this development: this is only a theory, but it is still far from a practical implementation.

An object of the invention is to construct a practical correlator circuit for quasiharmonic pulses, as indicated in FIG. one.

The technical result is achieved by constructing a structural electrical circuit shown in FIG. 2.

To solve this problem, a correlator is proposed that contains an input information bus with a quasi-harmonic pulse shape, characterized in that it contains an ADC, a comparison processor, a coincidence counter, a shift register, ROM, and a synchronizer with the following connections.

The input signal bus (a mixture of useful signal, interference, and noise) is connected to the ADC signal input, the outputs of which are connected to the first inputs of the comparison processor, the output of which is connected to a coincidence counter, the first output of the counter is connected to a synchronizer, the output of which is connected to a resolution circuit, and the second the output of the coincidence counter through the shift register and through the storage device is connected to the second input of the processor, the second input of which is connected to the input of the ADC start.

In FIG. 1 shows diagrams of classical digital rectangular and quasiharmonic digital signals (11-bit Barker code).

In FIG. 2 shows a structural electrical diagram of the proposed correlator.

In FIG. 1 lines 1 shows the waveform with rectangular pulses, the 2nd quasiharmonic lines.

In FIG. 2 shows:

3 - ADC

4 - comparison processor

5 - hit counter

6 - storage device (ROM)

7 - shift register

8 - synchronizer

9 is a signal resolution scheme (CXP)

The circuit of FIG. 2 has the following compounds.

The input signal bus (a mixture of useful signal, interference and noise) is connected to the ADC 3 signal input, the outputs of which are connected to the first inputs of the comparison processor 4, the output of which is connected to the match counter 5, the first output of the counter 5 is connected to the synchronizer 8, the output of which is connected to the resolution circuit 9, and the second output of the hit counter 5 through the shift register 7 and through the storage device 6 is connected to the second input of the processor 4, the second input of which is connected to the input to the input of the ADC 3.

The correlator works as follows.

A mixture of useful signal, noise and noise from the output of the high-frequency part of the receiver is fed to the ADC input, where it is converted to digital form. The comparison processor, bit by bit, with the necessary clock frequency, checks the correspondence of the received signal with the source code stored in the device’s memory. If the number of matches is insufficient, determined by the counter of coincidences on the output signal of the comparison processor, the shift register shifts the code in the memory to the right (or left) by one clock cycle, after which the comparison procedure is repeated. The coincidence counter and the shift register should be implemented on one FPGA. If the number of matches, ideally equal to the length of the used pseudo-random sequence, is sufficient, the synchronizer generates a synchronization pulse to start receiving useful information by the receiving device. The synchronizer can be implemented on the basis of a microcomputer. A separate memory microcircuit is not planned, since processor memory, FPGA memory, and microcomputer memory can be used for this purpose. In this case, a sequential correlator circuit is described; to accelerate the correlation procedure, a parallel circuit can also be applied, which will require the use of microcircuits of greater capacity and processing power.

Claims (1)

A correlator containing an input information bus of an input signal containing a mixture of useful signal, noise and noise with a quasi-harmonic pulse shape, characterized in that it contains an ADC, a comparison processor, a coincidence counter, a shift register, ROM, a synchronizer and a resolution circuit with the following connections: input bus signal — a mixture of useful signal, noise, and noise — is connected to the ADC signal input and the resolution circuit; the ADC outputs are connected to the first inputs of the comparison processor, the output of which is connected to the match counter The first counter output is connected to the synchronizer, the output of which is connected to the scheme permits, and the second output coincidence counter through the shift register and through the storage device is connected to a second input of the processor, a second input coupled to the input of the ADC trigger, the output resolution is the output of the correlator circuit.

Images