RU2618365C2 - Three-channel redundant control system c-01 - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: three-channel redundant control system in each module A, B, C, further introduced node bus Q-bus interface unit synchronization timers, pulse signals and the reception processing unit, and a processing unit receiving the signal potential, the node registers with corresponding connections.

EFFECT: expansion of the functionality in the part of the reception and processing of external pulse signal, and the potential signal, and the reference time interval.

3 cl, 11 dwg

Description

The invention relates to the field of computer engineering and can be used in the construction of highly reliable computing control systems designed to receive information from subscribers, process received information and provide the resulting information to the subscriber.

A known computer system [1], correcting a single error, which contains a first system module with a first processor, with a bus of the first processor and the first I / O bus (input / output), a second system module with a second processor, with a bus of the second processor and a second bus I / O, a third system module with a third processor, with a third processor bus and a third I / O bus, the first system module comprising a first memory, a first processor, a first I / O control unit, a first bridge comparing data of the first processor bus with data second second and third processor buses, wherein the first output of the first module is connected to the first inputs of the second and third module, the first output of which is connected to the first input of the first module and the second input of the second module, the first output of which is connected to the second inputs of the first and third module, each the memory module is connected to the processor, the processor is connected to the bridge, the bridge is connected to the I / O control unit, the output of which is the second output of the module, the second module of the system including the second memory, the second processor, the second block ok I / O control, a second bridge comparing the data of the second processor bus with the data of the first and third processor buses, the third module of the system including the third memory, the third processor, the third I / O control unit, the third bridge comparing the data of the third processor bus with the data first and second processor buses.

This system does not provide majorization of bidirectional lines and cannot work with a multiplex channel.

Known three-channel redundant control system [2], correcting a single error, which contains the first system module A, the second system module B, the third system module C, and each module A, B, C includes a processor with a processor bus P-bus, RAM, ROM, a group of majority elements, a generator, a first group, a second group, a third group of major devices, a controller of functional units, the first, second, third, fourth transceiver devices, the first and second controllers of the multiplex communication channel, per serial controller, buffer RAM, Q-bus and L-bus, the first bidirectional group of inputs / outputs of which is connected to a bi-directional group of inputs and outputs of the first controller of the multiplex communication channel, the first and second inputs of which are connected to the outputs of the first and second transceiver devices whose input-output groups are the first and second system input-output groups, respectively, the third and fourth input-output groups of which are the input-output groups of the third and fourth transceiver triads, the outputs of which are connected to the first and second inputs of the second controller of the multiplex communication channel, the group of inputs and outputs of which is the second group of inputs and outputs of the L-bus, and the first group of outputs of module A consists of the first groups of outputs of the second and third groups of majority devices and connected to the first groups of inputs of the second and third groups of majority devices of modules B and C, the first group of outputs of module B consists of the first groups of outputs of the second and third groups of majority devices of module B and connected to by the input groups of the inputs of the second and third groups of majority devices of module A and with the second input groups of the second and third groups of majority devices of module C, the first output group of module C consists of the first output groups of the second and third groups of majority devices of module C and is connected to the second input groups of the second and the third group of majority devices of modules A and B, and the second group of outputs of the second group of majority devices is connected to the first group of inputs of the peripheral controller, the first group of inputs and outputs of which connected to the first group of inputs and outputs of the third group of majority devices, the second group of inputs and outputs of which is connected to the first group of inputs and outputs of the Q-bus, the second group of inputs and outputs of which is connected to the first group of inputs and outputs of the controller of functional units, the second group the inputs and outputs of which are connected to the groups of inputs and outputs of RAM, ROM and the first group of inputs and outputs of the first group of majority devices, the second group of inputs and outputs of which is a P-bus and connected to the group of inputs and outputs RA, the group of outputs of which is connected to the first group of inputs of the group of majority elements, the first group of outputs of which is connected to the group of inputs of the processor, the input of which is connected to the output of the generator, with the inputs of the first, second and third groups of majority devices, the first and second controllers of the multiplex communication channel, peripheral controller and functional node controller, the first and second groups of outputs are connected to the RAM and ROM input groups, respectively, the third L-bus input-output group is connected to the the second group of inputs and outputs of the peripheral controller, the second group of inputs of which is connected to the second group of outputs of the third group of majority devices, the third group of inputs of which is connected to the first group of inputs of the system, the second group of inputs of which is connected to the first group of inputs of the first group of majority devices, the second group of inputs which is connected to the third group of outputs of the controller of functional nodes, the fourth group of outputs of which is connected to the first group of inputs of the Q-bus, the first group of outputs of which connected to the first group of inputs of the controller of functional nodes.

This system does not provide the reception and processing of external pulsed and potential signals and the countdown of time intervals.

The described device as the closest to the alleged taken as a prototype.

The objective of the invention is to provide:

• program access to the registers of functional nodes (ie support for exchanges on the Q-bus);

• issuing requests to interrupt the program for events in functional nodes and managing this issue;

• Configuring the functional node of synchronization timers (as a part of three TmrSn), including to select a clock source;

• countdown on synchronization timers;

• receiving and processing 16 external pulse signals or

receiving and processing 7 external pulse signals and recording signals of single-channel failures on 9 input channels;

• receiving and processing 16 external potential signals;

• control of the issuance of potential signals (relay commands) of programmable duration;

• control of the issuance of potential signals of a program-generated 8-bit program telemetry code in parallel code;

• control of the issuance in parallel code of potential signals of a software-generated 2-bit code "product operation mode".

The essence of the claimed invention, the possibility of its implementation and industrial use are illustrated by the drawings shown in FIG. 1-11, where:

• in FIG. 1 is a functional diagram of a three-channel redundant control system S-01;

• in FIG. 2 is a functional diagram of a synchronization timer assembly;

• in FIG. 3 shows a functional diagram of a synchronization timer;

• in FIG. 4 is a timing diagram of a read operation from RAM;

• in FIG. 5 is a timing chart of a write operation in RAM;

• in FIG. 6 shows the format of the register of signs and interrupt masks (RFM);

• in FIG. 7 shows the format of the control register (RC (j));

• in FIG. 8 shows the formation of the signal “TC (j)”;

• in FIG. 9 shows the format of a memory error register (REr);

• in FIG. 10 is a timing chart for polling potential interrupts;

• in FIG. 11 shows the format of the input and output control register Roff 81.

These advantages of the claimed system over the prototype are achieved due to the fact that in the three-channel redundant control system C-01, containing the first system module A, the second system module B, the third system module C, and each module A, B, C includes a processor 1, s processor bus P-bus 2, RAM 3, ROM 4, group of majority elements 5, generator 6, first 7 group, second 8 group, third 9 group of majority devices, controller of functional units 10, first 11, second 12, third 13, fourth 14 transceivers, the first 15 and second 16 controllers of the multiplex communication channel, the peripheral controller 17, the buffer RAM 18, the Q-bus 19 and the L-bus 20 connected to the BOSE 18, the first 21 bidirectional group of inputs / outputs of which are connected to a bi-directional group of inputs / outputs the first 15 controller multiplex communication channel, the first 22 and second 23 inputs of which are connected to the outputs of the first 11 and second 12 of the transceiver, the input-output groups of which are the first 24 and second 25 groups of inputs and outputs of the system, respectively, the third 26 and four the 27th group of inputs / outputs of which are the input / output groups of the third 13 and fourth 14 transceivers, the outputs of which are connected to the first 28 and second 29 inputs of the second 16 controller of the multiplex communication channel, the group of inputs / outputs 30 of which is the second group of inputs the outputs of the L-bus 20, the first 31 output group of module A consisting of the first output groups of the second 8 and third 9 groups of major devices and connected to the first input groups of the second 8 and third 9 groups of major devices of modules B and C, the first 32 group of outputs of module B consists of the first groups of outputs of the second 8 and third 9 groups of majority devices of module B and is connected to the first groups of inputs of the second 8 and third 9 groups of majority devices of module A and with the second groups of inputs of the second 8 and third 9 groups of majority devices of the module C, the first 33 group of outputs of module C consists of the first groups of outputs of the second 8 and third 9 groups of majority devices of module C and is connected to the second groups of inputs of the second 8 and third 9 groups of majority devices of modules A and B, and the second 34 groups the outputs of the second 8 group of majority devices is connected to the first group of inputs of the peripheral controller 17, the first 35 group of inputs and outputs of which are connected to the first group of inputs and outputs of the third 9 group of majority devices, the second 36 group of inputs and outputs of which are connected to the first group of inputs and outputs of the bus Q-bus 19, the second 37 group of inputs and outputs of which are connected to the first group of inputs and outputs of the controller of functional units 10, the second 38 group of inputs and outputs of which is connected to the groups of inputs and outputs of RAM 3, ROM 4, and the first group a solder of inputs and outputs of the first 7 group of majority devices, the second group of inputs and outputs of which is the 2 P-bus and connected to the group of inputs and outputs of the processor 1, the group of outputs of the 2 P-bus of which is connected to the first group of inputs of the group of majority elements 5, the first group of outputs which is connected to the group of inputs of the bus 2 of the P-bus of processor 1, the input of which is connected to the output 39 of the generator 6, with the inputs of the first 7, second 8 and third 9 groups of major devices, the first 15 and second 16 controllers of the multiplex communication channel, the periphery controller 17 and functional unit controller 10, the first 40 and second 41 groups of outputs of which are connected to the input groups of RAM 3 and ROM 4, respectively, the third 42 group of inputs and outputs of the L-bus is connected to the second group of inputs and outputs of the peripheral controller 17, the second the group of inputs of which is connected to the second 43 group of outputs of the third group of majority devices 9, the third group of inputs of which is connected to the first 44 group of inputs of the system, the second 45 group of inputs of which is connected to the first group of inputs of the first group of majority 7 devices, the first 46 group of outputs and the second group of inputs which are connected to the second group of inputs and to the third 47 group of outputs of the controller of the functional units 10, the fourth 48 group of outputs of which are connected to the first group of inputs of the Q-bus 19, the first 49 group of outputs of which connected to the first group of inputs of the controller of the functional units 10, the second 50 group of outputs of module A consists of a second output of the generator 6 and second groups of outputs of the group of majority elements 5 and the first group of majority devices 7 and is connected to third groups of inputs of modules B and C, the second 51 group of outputs of module B consists of a second output of the generator 6 and second groups of outputs of the group of majority elements 5 and the first 7 of the group of majority devices of module B and is connected to the third group of inputs of module A and the fourth group of inputs of module C, the second 52 group of outputs of module C consists of the second output of the generator 6 and the second groups of outputs of the group of majority elements 5 and the first group of majority devices 7 of module C and is connected to the fourth groups of inputs of modules A and C, and the third group of inputs s of modules connected to the first input of the generator 6, with the second group of inputs of the group of majority elements 5 and the third group of inputs of the first group of majority devices 7, the fourth group of inputs of the modules connected to the second input of the generator 6, with the third group of inputs of the group of majority elements 5 and the fourth group of inputs the first 7 groups of majority devices, with each module A, B, C additionally introduced, a Q-bus 53 interface node, a synchronization timer node 54, a pulse signal receiving and processing unit 55, a receiving and processing node bots of potential signals 56, a node of registers 57, a group of inputs and outputs 58 of which are connected to groups of inputs and outputs of a node for receiving and processing potential signals 56, a node for receiving and processing pulse signals 55, a node for a Gibus 53 bus interface, a node for synchronization timers 54, the first group the inputs of which are connected to the first groups of inputs of the register node 57, the pulse signal receiving and processing node 55, the potential signal receiving and processing node 56 and the group of outputs 59 of the Q-bus 53 interface node, the input-output group 60 of which is connected with the third group of inputs and outputs of the Q-bus 19, the second 61 group of outputs of which is connected to the group of inputs of the Q-bus 53 interface node, the second 62 group of outputs of which is connected to the second group of inputs of the Q-bus 19, and the third 63 group of inputs the system is connected to the second group of inputs of the register node 57, the group of outputs of which is the first 64 group of outputs of the system, the second 65 group of outputs of which is the group of outputs of the node for receiving and processing potential signals 56, the second group of inputs of which is the fourth 66 group of inputs of the s topics, the fifth 67th group of inputs of which is the second group of inputs of the node for receiving and processing pulse signals 55, the third group of inputs of which is connected to the first 68th group of outputs of the node of synchronization timers 54, the first output of which is connected to the first 69th output of the system, the sixth 70th group of inputs of which is the second group of inputs of the node synchronization timers 54, the third 71 and fourth 72 groups of inputs of which are connected to the third output groups of the module B and C, respectively, and the input of the register node 57 is connected to the output 39 of the generator 6, the output d 73 node receiving and processing pulse signals 55 is connected to the input of the node receiving and processing potential signals 56, and the output 74 of the controller of the functional nodes 10 is connected to the input of the synchronization timer unit 54, the second 75 group of outputs of which are connected to the first group of inputs of the Q- bus interface node bus 53, the third 76 group of outputs of the synchronization timer unit 54 is the third group of outputs of module A and is connected to the third groups of inputs of modules B and C, and the third groups of outputs of modules B and C are connected to the fourth groups of inputs in modules C and B, respectively.

The synchronization timer assembly 54 contains a first 77, a second 78 and a third 79 synchronization timers, a multiplexer 80, a register 81, a first 82, a second 83 and a third 84 majority elements, an OR element 85 and an And 86 element, the output of which is connected to the first input of the OR element 85 the output of which is the first 69 output of the synchronization timer unit 54, the first 68 group of outputs of which is the group of outputs of the register 81, the first output of which is connected to the first input of the AND element 86, the second input of which is the first signal of the second 70 group of inputs of the synchronization timer unit ronization 54, which is connected to the first groups of inputs of the first 77, second 78 and third 79 synchronization timers and the first and second inputs of multiplexer 80, the output of which 87 is the second output of the synchronization timer unit and connected to the first inputs of synchronization timers (77, 78, 79) the first outputs of which are connected to the first, second and third inputs of the OR element 85, the second 75 group of outputs of the synchronization timer unit 54 connected to the first groups of outputs of the first 77 and second 78 synchronization timers, the second outputs of the sync timers the lowerings (77, 78, 79) are connected to the first inputs of the first 82, second 83, and third 84 majority elements and are the third 76 group of outputs of the synchronization timer unit 54, the group of input-output 58 of which is connected to the group of input-output of the first 77, second 78 and the third 79 synchronization timers and register 81, the second output of which is connected to the third input of the multiplexer 80, the first 59 group of inputs of the synchronization timer node is connected to the group of inputs of the register 81, with the second groups of synchronization timer inputs (77, 78, 79), the second inputs of which connected to the first 74 input of the synchronization timer unit 54, the third 71 and fourth 72 groups of inputs of which are connected to the first and second groups of inputs of the first 82, second 83 and third 84 majority elements, the output 88 of the first 82 majority element is connected to the third inputs of the first 77 and second 78 synchronization timers, the output 89 of the second 83 majority element is connected to the fourth input of the second 78 synchronization timer and the third input of the third 79 synchronization timer, the output 90 of the third 84 majority element is connected to the fourth inputs Dams of the third 79 and the first 77 synchronization timers.

The synchronization timer (77, 78, 79) contains the control register 91, the configuration control register 92, the counter register 93, the hold register 94, the preset register 95, the first 96 multiplexer, the second 97 multiplexer, the third 98 multiplexer, the fourth 99 multiplexer, the first 100 element And, the second 101th element And, the third 102th element And, the fourth 103th element And, the fifth 104th element And, the sixth 105th element And, the seventh 106th element And, the eighth 107th element And, the ninth 108th element And, the tenth 109th element And, the eleventh 110th element And, the twelfth 111 element of And, the thirteenth 112 element of And, four the twelfth 113th element And, the fifteenth 114th element And, the sixteenth 115th element And, the OR element 116, the output of which is connected to the first inputs of the tenth 109, the eleventh 110, the fourteenth 113 and the fifteenth 114 elements And, the outputs of which are connected to the first inputs of the register counter 93 lower order , register register 94 low-order bits, register counter 93, register register 94, respectively, the group of inputs and outputs of which are connected to groups of inputs and outputs of the preset register 95 low order bits, register preset 95, control register conf by the control 92, the control register 91 and are a group of inputs / outputs 58 of a synchronization timer (77, 78, 79), the second 59 group of inputs of which is connected to the groups of inputs of the control register 91, the preset register 95 low order bits, the preset register 95, the counter register 93 low bits, counter register 93, latch register 94 low-order bits, latch register 94 and configuration control register 92, the first output of which is connected to the first input of the third 98 multiplexer, the output of which is connected to the first inputs of the third 102 and gray there are 106 elements And and the fourth 99 multiplexer, the output of which is connected to the first input of the eighth 107 element And, the output of which is connected to the second input of the counter register 93, the first and second outputs of which are connected to the second inputs of the eleventh 110 and fifteenth 114 elements And, the outputs of which are connected with the first inputs of the register of fixation 94 low-order bits and register of fixation 94, and the first group of outputs 75 of the synchronization timer (77, 78, 79) is connected to the outputs of the fourth 103, fifth 104, twelfth 111 and thirteenth 112 elements And, the first e inputs of the fourth 103 and fifth 104 elements And are interconnected and with the output of the first 100 element And, and the first inputs of the twelfth 111 and thirteenth 112 elements And are interconnected and with the output of the ninth 108 element And, the first and second inputs of which are connected to the first ( QI) and the second (MI) outputs of the control register 91, the first (ErQI) and second (QI) inputs of which are connected to the second input of the eighth element 107 And the output of the seventh 106 element And, the second input of which is connected to the third (Off) output of the control register 91, fourth (Cyc), fifth (SI) and sixth (Push) in whose moves are connected to the first inputs of the sixth 105 AND element, the first 96 multiplexer and the OR element 116, respectively, the second input of which is connected to the output of the sixth 105 AND element, the second input of which is connected to the third (ErQ) and fourth (Q) inputs of the control register 91 and the third 88 synchronization timer input (77, 78, 79), the first 69 output of which is connected to the output of the sixteenth 115 element And, the first input of which is connected to the fifth (OffO) input of the control register 91, the seventh (ExP) output of which is connected to the second input of the third 102 elements And, in the output of which is connected to the third input of the OR element 116, the second 76 output of the synchronization timer (77, 78, 79) is connected to the third output of the counter register 93 and the second input of the sixteenth 15 of the And element, the first 70 group of inputs of the synchronization timer (77, 78, 79 ) is connected to the first inputs of the first 96 and second 97 multiplexers and the second input of the first 96 multiplexer, the output of which is connected to the second input of the third 98 multiplexer, the third input of which is connected to the fourth 90 input of the synchronization timer (77, 78, 79), the first 87 and second 74 entries with connected to the second input of the second 97 multiplexer and the first input of the second 101 And element, the output of which is connected to the second input of the fourth 99 multiplexer, the third input of which is connected to the eighth (Tic) output of the control register 91, the second output of the configuration control register 92 is connected to the second inputs of the fourth 103 and twelfth 111 AND elements and inverse inputs of the fifth 104 and thirteenth 112 AND elements, the ninth (Q) and tenth (M) outputs of the control register 91 are connected to the first and second inputs of the first 100 AND elements, the third output is reg tra configuration control 92 is connected to a third input of the second multiplexer 97, whose output is connected to a second input of the second AND gate 101, the preset register 95 outputs the lower level and the preset register 95 are connected to second inputs 109 of the tenth and fourteenth elements 113 I.

Three-channel redundant control system C-01 operates as follows.

The proposed system consists of three of the same type of backup channels, which are denoted by the letters A, B, C (Fig. 1), connected by majority ties 31, 32, 33, 50, 51, 52. Majority elements 5 of the backup channels and majority devices 7, 8, 9 operate on a two-out-of-three basis.

The system uses the following interface buses to exchange information between functional devices (FUs):

• processor bus - P-bus 2;

• local bus of input-output devices (I / O) - L-bus 20;

• intermodular bus -Q-bus 19.

The processor bus - the P-bus - is a functional unit of the parallel interface implemented in the processor.

Connected to the P-bus: processor 1, memory 3, 4, functional unit controller 10 (KFU). On the P-bus bus, processor 1 provides programmatic access to memory 3, 4 and KFU 10. On the P-bus, processor 1 receives interrupt requests (the first group of inputs).

Local air-to-air bus - L-bus 20 is a functional unit implemented as part of input-output devices. Connected to the L-bus: peripheral controller 17, controllers MKO0-15, MKO1-16 and BOZU 18.

The inter-module bus - Q-bus 19 (GOST R 52070-2003) - is a functional node of the parallel interface, implemented as part of the system.

The processor 1 is connected to the Q-bus 19 (through KFU10 (37) the peripheral controller 17 (through the majority devices 9 (36) and the Q-bus 53 (60) bus interface node. The interaction on the Q-bus 19 is provided by:

• controller of functional units 10;

• peripheral controller 17

• Q-bus 53 interface node.

On the Q-bus 19, the processor 1 provides programmatic access to the registers of KFU 10, a peripheral controller 17, a node for synchronization timers 54, a node for receiving and processing pulse signals 55, a node for receiving and processing potential signals 56, and a node for registers 57.

Each channel includes a processor 1, which ensures the execution of a program located in ROM 4. Some programs can be located in RAM3, where they can be downloaded from ROM4 or external interfaces of the system. When executing this program in the "user" mode, the processor 1 can access the part of RAM3 allocated for the user programs. When executing programs in the "system" mode, processor 1 can access all RAM3 and the registers of external devices.

Processor 1 can address the following data items on the P-bus:

• byte - 8-bit data element (smallest addressable unit);

• half-word - 16-bit data element;

• word - 32-bit data item.

All addresses issued by the processor are 32-bit.

The main memory of RAM3 and ROM4 connected directly to the P-bus consists of 32-bit cells whose addresses are aligned with the “word boundary” (that is, the address of the main memory cell is a multiple of four). The main memory provides all the addressing types indicated above.

KFU10, connected directly to the P-bus, incorporates 32-bit registers. KFU10 provides only word addressing.

KFU10 provides processor 1 with programmatic access to KFU 10 registers, to RAM 3 and ROM 4 memory, to registers and to BOSU 18 of all air-blast units.

KFU 10 issues processor 1 signals to the processor 1 when it starts and restarts, interrupt requests.

The format of the address of the object on the air-blast, issued by the processor 1, provides:

• 12-bit attribute field defining the air-blast address zone (Q-bus zone 19);

• 2-bit air-blast number field defining the air-blast address zone.

The system provides interaction with external subscribers via two duplexed multiplexed channels of information exchange (MCO) in accordance with GOST R 52070-2003 and with processor 1 via the Q-bus interface 19. Electrically, each MCO consists of two main lines: main and backup. The exchange for each MCO is controlled by its own controller (KMK0 15, KMK1 16) which can be programmatically set to the controller mode channel (KK) or to the terminal device (OS) mode. Majorization of the signals of the same name is carried out according to the principle of voting “two out of three” (the third group of majoritarian devices 9).

The overall control of the MCO is performed by the processor 1, referring to PC 17, the MCO controllers (KMK0 15 and KMK1 16) and BOZU 18. PC 17 is the dispatcher of the local L-bus 20, regulating the calls (KMK0 15, KMK1 16 and processor 1 to BOZU 18 .

Each duplicated MCO interface is controlled by its own CMC, which can be programmatically set to QC or OS. In any mode, KVM provides a complete list of formats and commands of GOST R 52070-2003, as well as control of the reliability of information words received from MCOs.

In the OS mode, the received command words are checked for validity. The admissibility of one or another command is set programmatically. The address of the OS is also set programmatically.

BOSE 18 with a volume of 32K × 16 is divided into eight equal zones (pages). In any mode, KVM works with one page, which is assigned programmatically. The processor 1 has access to the entire volume of BOZU 18, which can be combined with exchanges of both KMK 15, 16 via MCO. BOSU 18 contains control and control information for each exchange, as well as a buffer of received and transmitted data. In op-amp mode, the buffer address is determined by the sub-address from the received control word.

The PP of the device 11, 12, 13, 14 carry out the electrophysical coupling of the reservation channels with the MCO lines. In the MCO, the transmitter is active only one channel redundancy, others are blocked. The selection of the active backup channel is programmed. Reception from MCO is carried out in all reservation channels.

Each backup channel has two nodes of majority devices (second 8 and third 9 groups of major devices). In one node, the majority signals of the Q-bus 19 bus (third 9 group of majority devices), in the other (second 8 group of majority devices) - sequential codes issued to the transmitter and received from the PP receiver.

Information interaction between the processor 1, OZU3, ROM4 and KFU 10 is carried out on thirty-two bit bi-directional multiplex bus, the cross section of which includes the first group of major devices 7 correcting information in a bi-directional bus. The first group of majority devices 7 is connected to the processor 1 by the first group of inputs / outputs (P-bus 2), and with RAM3, PZU4 and KFU10, by the second group of inputs and outputs 38. The first group of majority devices 7 of all redundant channels are connected by majority bonds 50, 51, 52, which ensures the operability of the system in case of failures arising in individual channels. When exchanging with RAM3 and ROM4, information is written to the specified cell, or information is read from the specified cell. The information exchange between the processor 1 and KFU 10 is carried out as a result of the implementation of procedures for writing and reading information in relation to programmatically accessible registers contained in KFU10. When performing write and read procedures with respect to memory and registers, the first group of inputs / outputs 38 operates in a time-sharing mode: first, a cell or register address code is transmitted along it, and then information.

The Q-bus 53 interface node supports exchange operations on the Q-Bus, generates an interrupt request signal - “IRQ” 62 and internal register control signals.

The timing diagrams of the Q-Bus exchange are shown in FIG. 4 and FIG. 5. When performing the write operation to the output relay signal registers RReI and the telemetry register RTIm, the “CVR” and “CVT” signals are generated (Fig. 5), respectively, which are embedded in the “DOUT” signal and their duration is 500 ns.

The "IRQ" signal 62 is generated (low level) if there is at least one interrupt request (RFL) unmasked in the RFM register.

The Q-bus 53 interface node contains a software-accessible register of signs (“flags”) and RFM interrupt masks.

The format of the RFM register is shown in FIG. 6.

Assignment of bits of the RFM register:

• F0 - a sign of the presence of impulse interrupt requests (ZPR) of "line 0"; readable; it is set by hardware when RQI <i> = 1 (register of pulsed RRs), if RMI <i> = 0 (register of masks of pulsed RRs), and RNI <i> = 0 (register of line numbers of pulsed RRs) (i = 0 ... 15) ; reset by hardware when software resetting the corresponding RQI bits, software setting the corresponding RMI bits to "1" or software setting of the corresponding RNI bits to "1"; upon arrival of the signal "SR" (70) (initial setting) is set to "0";

• M0 - mask for interruption by F0, "1" masks the interruption; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F1 - a sign of the presence of pulse ZPR "line 1"; readable; it is set in hardware when RQI <i> = 1, if RMI <i> = 0 and RNI <i> = 1 (i = 0 ... 15); reset by hardware when software resetting the corresponding RQI bits, software setting the corresponding RMI bits to "1" or software setting of the corresponding RNI bits to "0"; upon arrival of the signal, “SR” (70) is set to “0”;

• M1 - mask for interruption by F1; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F2 - a sign of the presence of potential ZPR "line 0"; readable; it is set by hardware when RQP <i> = 1 (register of potential RPS), if RMP <i> = 0 (register of masks of potential RPS) and RNP <i> = 0 (register of line numbers of potential RPS) (i = 0 ... 15); reset by hardware when software resetting the corresponding RQP bits, software setting the corresponding RMP bits to "1" or software setting of the corresponding RNP bits to "1"; upon arrival of the signal, “SR” (70) is set to “0”;

• M2 - mask for interruption according to F2; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F3 - a sign of the presence of potential ZPR "line 1"; readable; set by hardware when RQP <i> = 1, if RMP <i> = 0 and RNP <i> = 1 (i = 0 ... 15); reset by hardware when software resetting the corresponding RQP bits, software setting the corresponding RMP bits to "1" or software setting of the corresponding RNP bits to "0"; upon arrival of the signal, “SR” (70) is set to “0”;

• M3 mask for interruption according to F3; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F4 - a sign of the presence of a ZPR for triggering TmrSn [j] (77, 78, 79), if RCS [j] <reQ> = 0 (configuration register 92); readable; it is set in hardware with RC [j] <Q> = 1 (control register 91) (the value of RC [j] <ErQ> 91 is not taken into account) if RC [j] <M> 91 = 0; hardware reset when software resetting RC [j] <Q> 91 or setting RC [j] <M> 91 = 1; upon arrival of the signal “SR” (70) is set to “0” (j = 0 ... 2);

• M4 - mask for interruption according to F4; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F5 - a sign of the presence of ZPR upon the arrival of an external signal at TmrSn [j] (77, 78, 79), if RCS [j] <reQ> 92 = 0; readable; it is set by hardware with RC [j] <QI> 91 = 1 (the value of RC [j] <ErQI> 91 is not taken into account) if RC [j] <MI> 91 = 0; hardware reset when software resetting RC [j] <QI> 91 or setting RC [j] <MI> 91 = 1; upon arrival of the signal “SR” (70) is set to “0” (j = 0 ... 2);

• M5 - mask for interruption according to F5; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F6 - a sign of the presence of a ZPR on the triggering of TmrSn [j] (77, 78, 79), if RCS [j] <reQ> 92 = 1; readable; it is set by hardware with RC [j] <Q> 91 = 1 (the value of RC [j] <ErQ> 91 is not taken into account) if RC [j] <M> 91 = 0; hardware reset when software reset RC [j] <Q> or set RC [j] <M> = 1; upon arrival of the signal “SR” (70) is set to “0” (j = 0 ... 2);

• M6 - mask for interruption according to F6; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• F7 - a sign of the presence of ZPR upon the arrival of an external signal at TmrSn [j] (77, 78, 79), if RCS [j] <reQ> 92 = 1; readable; it is set by hardware with RC [j] <QI> 91 = 1 (the value of RC [j] <ErQI> 91 is not taken into account) if RC [j] <MI> 91 = 0; hardware reset when software resetting RC [j] <QI> 91 or setting RC [j] <MI> 91 = 1; upon arrival of the signal, “SR” (70) is set to “0”;

M7 - mask for interruption according to F7; It is installed and reset software; upon arrival of the signal “SR” (70) is set to “1”.

Synchronization timers (77, 78, 79) TmrSn [j] (j = 0 ... 2) are the same and are designed to provide synchronization of various external systems and software, as well as to synchronize the selected signal: an external time stamp from the MV input (70) , an external pulse signal from the input IP6 (70) or from the previous TmrSn (77, 78, 79).

The functional diagram of TmrSn (77, 78, 79) is shown in FIG. 3.

The composition of each timer TmrSn [j] includes:

control register RC [j] 91;

• RCS configuration control register [j] 92;

• counter register RT [j] 93;

• low-order counter register RTL [j] 93;

• preset register RPL [j] 95;

• low order register RPL [j] 95;

• register register RFx [j] 94;

• low-order register RFxL [j] 94;

• multiplexers, logic elements (96-116).

The format of the RC [j] 91 register is shown in FIG. 7.

The assignment of bits of the register RC [j] 91:

• Q - a sign of a single operation TmrSn (77, 78, 79) (the counter counted to zero), the signal "TC" 76 is issued and, if the mask RC <M> 91 = 0 is removed, RFM <F4> = 1 is set, if RCS <ReQ> 92 = 0 or RFM <F6> = 1 if RCS <ReQ> 92 = 1; when RC <M> 91 = 1 is set, the RFM <F4> or RFM <F6> bits are not set; The bit Q is set in hardware, is reset by program record "0" (in this case, the corresponding "flag" in the RFM register is reset); record "1" does not change the state of the bit; upon the arrival of the signal “SR” (70), the bit Q is set to “0”;

• ErQ - a sign of the re-triggering of TmrSn (77, 78, 79); it is set in hardware to “1” if the timer triggered when RC <Q> 91 = 1; software reset; record "1" does not change the state of the bit; upon arrival of the signal, “SR” (70) is set to “0”;

• M - mask for interruption from TmrSn (77, 78, 79), "1" - masks the interruption - does not allow to establish RFM <F4> = 1 or RFM <F6> = 1; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• Push - census signal from the preset register RP [j] 95 to the counter register RT [j] 93 (RPL [j] 95 to RTL [j] 93, respectively); set to "1" programmatically, reset hardware after recording, and always read "0"; upon arrival of the signal, “SR” (70) is set to “0”;

• Tic - digit for selecting the clock frequency of the counter, “0” corresponds to 1 μs (generated from the input frequency of 12 MHz or from the inputs F1A, F1B (70) of the precision frequency of 1 MHz), “1” - to the external signal from the input MV (RC <SI > 91 = 0, RCS <Link> 92 = 0), from IP6 input (70) (RC <SI> 91 = 1, RCS <Link> 92 = 0), or by triggering the previous synchronization timer (RCS <Link> 92 = 1); it is set and reset by software; upon arrival of the signal “SR” (70) it is set to “0”;

• Exp - a sign of the census permission ("1") from RP [j] 95 to RT [j] 93 (RPL [j] 95 to RTL [j] 93, respectively) upon receipt of the signal (high level) at the input MV (70) (RC <SI> 91 = 0, RCS <Link> 92 = 0) either to IP6 input (70) (RC <SI> 91 = 1, RCS <Link> 92 = 0) or by triggering the previous synchronization timer (RCS < Link> 92 = 1); It is installed and reset software; upon arrival of the signal, “SR” (70) is set to “0”;

• Cyc - a sign of the permission of the census from RP [j] 95 to RT [j] 93 (RPL [j] to RTL [j], respectively) for the activation of the synchronization timer (77, 78, 79), ie upon the arrival of a signal (high level) at the input of TCM [j] (88, 89, 90); It is installed and reset software; upon arrival of the signal, “SR” (70) is set to “0”;

• Off - prohibition of the receipt of counting pulses to the input of the counter 93, while the census by setting RC <Push> 91 to "1" is possible; It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• QI - sign of an external signal arriving at the input MV (70) (RC <SI> 91 = 0, RCS <Link> 92 = 0) or at the input IP6 (70) (RC <SI> 91 = 1, RCS <Link> 92 = 0) or by triggering the previous synchronization timer (RCS <Link> 92 = 1); reset by program record "0"; record "1" does not change the state of the bit; upon arrival of the signal, “SR” (70) is set to “0”;

• ErQI - a sign of the re-arrival of an external signal; hardware-set to "1" if an external signal arrived at RC <QI> 91 = 1; software reset; record "1" does not change the state of the bit; upon arrival of the signal, “SR” (70) is set to “0”;

• MI - mask for interruption from TmrSn (77, 78, 79) upon the arrival of an external signal, "1" - masks the interrupt - does not allow RFM <F5> = 1 (RCS <ReQ> 92 = 0) or RFM <F7> = 1 (RCS <ReQ> 92 = 1); It is installed and reset software; upon arrival of the signal, "SR" (70) is set to "1";

• SI - bit for selecting an external signal, "0" corresponds to the signal from the input "MV" (70), "1" - to the external signal from the input IP6 (70); it is set and reset by software; upon arrival of the signal, SR (70) is set to "0"; with RCS <Link> 92 = 1, the value of the SI bit is indifferent, since in this case the trigger signal of the previous synchronization timer is used;

• OffO - bit for prohibiting the issuance of a signal "TCC" 69, "1" prohibits the issuance of, "0" - allows; it is set and reset by software; upon arrival of the signal “SR” (70) it is set to “1”.

The assignment of the bits of the RCS [j] 92 configuration control register is as follows:

• Link - with RCS <Link> 92 = 1, the triggering signal TmrSn [j-1] (90, 88, 89) is used as an external external signal for TmpSN [j] (77, 78, 79), while for TmrSn 77 it is used the response signal from TmrSn2 79 is used; with RCS <Link> 92 = 0 MV 70 (with RC <SI> = 0) or IP6 70 (with RC <SI> = 1) is used as an external signal; upon arrival of the signal, “SR” (70) is set to “0”.

• ReQ - this bit determines to which bits of the RFM register interrupt requests are sent; with ReQ = 0, the interrupt request for the activation of the synchronization timer (77, 78, 79) is sent to RFM <F4>, and the interrupt request for the arrival of an external signal in RFM <F5>, with ReQ = 1, the request is not an interrupt for the synchronization timer (77, 78, 79) is sent to RFM <F6>, and a request for interruption upon the arrival of an external signal in RFM <F7>, naturally, requests are sent to RFM only if they are not masked; upon arrival of the signal, “SR” (70) is set to “0” for TmrSn0 77, TmrSn2 79 and to “1” for TmrSn1 78;

• Prs - this bit indicates the source of counting pulses of 1 μs for the counter of the synchronization timer (77, 78, 79); at Prs = 0, counting pulses of 1 μs are generated from the input frequency of 12 MHz; at Prs = 1, counting pulses are taken from the inputs F1A (70) (with Roff <GeP> = 0) or F1B (70) (with Roff <GeP> = 1); upon arrival of the signal, “SR” (70) is set to “0”.

All of the above bits of the register RCS 92 are programmatically accessible by writing and reading. Digits 3-15 are absent and are read by zero values.

Note. For TmrSn0 77 and TmrSn2 79 the initial value of the discharge is ReQ = 0, for TmrSn1 78 the initial value of the discharge is ReQ = 1.

The counter register RT [j] 93 and the low-order counter register RTL [j] 93 together form a 20-bit counter whose upper 16 bits are in RT [j] 93, and the lower 4 bits are in RTL [j] 93. Bits 4- 15 RTL [j] 93 are not used and are read by zero values.

The initialization signal SR (70) registers RT [j] 93, RTL [j] 93 are set to "0".

Writing to RT [j] 93, RTL [j] 93 is performed exclusively from the preset registers RP [j] 95, RPL [j] 95 according to any of the following conditions:

• program record "1" in the discharge RC <Push> 91;

• timer operation with RC <Cyc> 91 = 1;

• the arrival of an external signal with RC <Exp> 91 = 1 and RC <Off> 91 = 0.

The current value RT [j] 93, RTL [j] 93 at the time of writing is stored in the hold registers RFx [j] 94, RFxL [j] 94.

Direct program writing to RT [j] 93, RTL [j] 93 is not possible, these registers are read-only. When reading, you must first read the 16 high order bits from the register RT [j] 93, and then read the 4 low order bits from the register RTL [j] 93.

Notes:

• with RC <Off> 91 = 1, writing RT [j] 93, RTL [j] 93 is actually possible only by the condition of program writing “1” to the category RC <Push> 91; In this case, the timer cannot be triggered, since with RC <Off> 91 = 1 the arrival of counting pulses is prohibited, and recording by the arrival of an external signal is prohibited;

Recording by the arrival of an external signal is delayed until the arrival of the nearest counting pulse.

If the 20-bit counter 93 contains a single value and a counting pulse is supplied to it, then the counter 93 goes to zero and TmpSn [j] (77, 78, 79) is triggered - a timer signal “TC [j]” is issued 76 Recording a zero value, including when a unit value is contained in counter 93, does not trigger the timer.

The formation of the signal duration "TC" 76 at the output is shown in FIG. 8. The signal generation circuit "TC [j]" provides a signal with a duration of 3 to 4 μs no more than once every 16 μs. The input signal "TCM [j]" (88, 89, 90) is a majorized signal "TC [j]" 76 in a three-channel redundant system.

The signal "TCM [j]" is used for inter-channel synchronization of the timer. In systems without redundancy, it is necessary to connect the terminals TC [j] and TCM [j].

When a signal TCM [j] (88, 89, 90) arrives, the discharge RC <Q> 91 is set to "1", if this bit already contained "1", then RC <ErQ> 91 is also set to "1", with RC <Cyc> 91 = 1 censuses RP [j] 95, RPL [j] 95 → RT [j] 93, RTL [j] 93 → RFx [j] 94, RFxL [j] 94.

As counting pulses for the counter, one-microsecond pulses from a 1 MHz frequency source from a frequency divider or from an external source, or (with RC <Tic> 91 = 1) external signals can be used (for RC <Tic> 91 = 0).

The supply to the pulse counter 93 1 μs can be blocked by an external signal BLT 74. The external signal BLT 74 is not affected. Both 1 μs pulses and external signals are disabled when RC <Off> 91 = 1.

The preset register RP [j] 95 and the low-order preset register RPL [j] 95 together form a 20-bit preset register 95, the higher 16 bits of which are in RP [j] 95 and the lower 4 bits are in RPL [j] 95 .

When writing, you must first write the 4 least significant bits in the register RPL [j] 95, then you need to write the 16 most significant bits in the RP [j] 95, while fixing the full value in the 20-bit total register.

When reading, you must first read the 16 high order bits from the register RP [j] 95, and then read the 4 low order bits from the register RPL [j] 95.

The register register RFx [j] 94, and the register register low-order bits RFxL [j] 94 together form a 20-bit register register, the highest 16 bits of which are in RFx [j] 94, and the lower 4 bits - in RFxL [j] 94.

When writing, you must first write the 4 least significant bits in the register RFxL [j] 94, then you need to write the 16 most significant bits in RFx [j] 94, while fixing the full value in the 20-bit total register.

When reading, you must first read the 16 high order bits from the register RFx [j] 94, and then read the 4 low order bits from the register RFxL [j] 94.

The node receiving and processing pulse signals (Ypres) 55 provides the reception and processing of 16 pulse interrupts.

IPR includes software-accessible registers:

• RQI - register of pulse ZPR with memorization;

• RMI - register of pulsed masks;

• RNI - register of line numbers of pulse ZPR;

• REr - error register with memory.

The register of pulse ZPR with memorization is available for reading and writing "0", program record "1" in the register category does not change its state.

The bits of the register of pulsed ZPR with memorization Q <i>, where i = 0 ... 15, are hardware set to "1" when a high level appears on the corresponding input IP <i> 67 and the presence of "log. 0 "in the bits of the input disable register Roff <OffHI> 81.68 (low order) and Roff <OffHI> 81 (high order). The bits Q <i> are reset by program record "0" to the corresponding bit of the register; upon receipt of the signal "SR" (70), all bits of the register are set to "0".

If Roff <OffLI> 81.68 = 1, then Q <i>, where i = 0. 6 are not set, regardless of the status of inputs IP0-IP6 70, if Roff <OffHI> 81.68 = 1, then Q <i>, where i = 7 ... 15 are not set regardless of the status of inputs 70 IP7 ÷ IP15.

The register of pulsed masks ZPR RMI is available for reading and writing.

When M <i> = 0, where i = 0 ... 15, it is possible to issue an RFQ from the corresponding bit Q <i> to the bit RFM <F0> or RFM <F1> in accordance with the value of the corresponding bit N <i> of the RNI register; when M <i> = 1 ZPR is not formed.

Upon receipt of the signal "SR" (70), all bits of the register are set to "1".

The register of line numbers of pulse ZPR RNI is available for reading and writing.

When N <i> = 0, where i = 0 ... 15, Zpr Q <i> when M <i> = 0 goes to RFM <F0>,

when N <i> = 1, where i = 0 ... 15, ZPR Q <i> when M <i> = 0 is sent to RFM <F1>.

Upon receipt of the signal "SR" (70), all bits of the register are set to "0".

The error register with storing REr is shown in FIG. 9 is available for reading and writing "0", program record "1" does not change the state of the corresponding discharge.

The register bits are set to “1” in hardware when a high level appears on the corresponding input 70 IP7 - IP15, and the presence of “log. 0 "in the category of the register of switching off the input signals Roff <OffE> 81.68. If Roff <OffE> 81.68 = "log. 1 ”, then the bits are not set _A regardless of the state of the inputs 70 IP7 - IP15.

Discharge Er0A corresponds to input 70 IP7, then in order to discharge Er2C corresponds to input 70 IP15.

The REr bits are reset by program record "0", upon the arrival of the signal "SR" 70, all bits of the register are set to "0". Digits 0 through 6 do not physically exist and read "0".

The node receiving and processing potential signals 56 (PPR) provides the reception and processing of 16 potential interruptions.

Potential interrupts are fed to the input of the CRM 66 in a serial code. The 16-bit interrupt code is read by the signal "S1" 66, the repetition period of which is 1 millisecond. Signal "S1M" 66 is a majorized signal "S1" and is used in redundant systems for inter-channel synchronization. In systems without redundancy, it is necessary to connect the terminals S1 and S1M.

The signal at the input of the CRM 66 is the result of a sequential survey of the status of 16 sensors of potential (contact) interruptions. The survey is performed for 16 clock cycles of frequency C. The timing diagram of the survey of potential interruptions is presented in FIG. 10.

The structure of the PPR node includes software-accessible registers:

• RQP - register of potential ZPR with memorization;

• RMP - register of masks of potential ZPR;

• RNP - register of line numbers of potential ZPR;

• RFP - a register of signs of potential ZPR without memorization.

The register is read and write "0", program record "1" in the register category does not change its state; program record "1" does not change the state of the corresponding bit.

The discharge QP <i>, where i = 0 ... 15, is hardware-set to "1" with a high signal level at the input of the KRM 66 during the negative edge of the i-th polling pulse at the output of "C" and the presence of "0" in the discharge Roff < OffP> 81, reset to "0" by program writing; upon arrival of the signal "SR" 70, all bits of the register are set to "0".

The register of masks of potential ZPR RMP is sixteen-bit.

The register of potential RMP masks is read and write.

When Mp <i> = 0, where i = 0 ... 15, it is possible to issue an RFL from the corresponding bit QP <i> to the bit RFM <F2> or RFM <F3> in accordance with the value of the corresponding bit NP <i> of the RNP register; when MP <i> = 1 ZPR is not formed.

Upon receipt of the signal "SR" 70, all bits of the register are set to "1".

The register of line numbers of potential ZPR RNP sixteen-bit.

The RNP register is read and write.

When NP <i> = 0, where i = 0 ... 15, Zpr QP <i> with MP <i> = 0 goes to RFM <F2>,

with NP <i> = 1, where i = 0 ... 15, Zpr QP <i> with MP <i> = 0 goes to RFM <F3>.

Upon receipt of the signal "SR" 70, all bits of the register are set to "0".

The register of signs of potential ZPR without memorizing RFP is sixteen-bit.

The register is read-only, FP <i>, where i = 0 ... 15, are hardware-set to "1" at a high level at the input of the KRM 66 during the negative edge of the i-th polling pulse at the output of "C" and are reset to "0 "at a low level at the input of KPM 66 at this moment.

Upon receipt of the signal "SR" 70, all bits of the register are set to "0".

The input and output control register Roff 81 is designed to enable and disable various groups of input signals.

The register is accessible by writing and reading.

The purpose of register bits is as follows:

• OffE 68 - the presence of "0" in this category allows the input of signals from the IP7 - IP15 70 inputs to the single-channel error register REr, "1" - prohibits; by the signal "SR" 70, this bit is set to "1";

• OffLI 68 - the presence of "0" in this category allows the input of signals from inputs 70 IP0-IP6 to the pulse register RQI RQI, "1" - prohibits; by the signal "SR" 70, this bit is set to "1";

• OffHI - the presence of “0” in this category allows the input of signals from the IP7 - IP15 67 inputs to the pulse register RQI, “1” - prohibits; by the signal "SR" 70, this bit is set to "1";

• OffP - the presence of “0” in this category allows the signal from the input of the KPM 66 to the pulse register ZPR RQP, “1” - prohibits; by the signal "SR" 70, this bit is set to "1";

• GeP - this bit controls the choice of an external frequency input of 1 MHz; when GeP = 0, the input F1A 70 is used; when GeP = 1, the input F1B 70 is used; by the signal "SR" 70, this bit is set to "0";

• Nor - the presence of “1” in this category allows the broadcasting of the timestamp signal from the input of MV 70 to the output of TCC 69, “0” - prohibits; by the signal "SR" 70, this bit is set to "0".

Digits 6 through 15 are physically absent and read as “0”.

The register node 57 consists of a register for issuing relay signals RreI, a register for issuing telemetry RTIm and a register for operating modes RR.

The register of relay signals RReI is designed to ensure the issuance of a signal CVR 64 when performing a program write operation in this register.

The timing diagram of the CVR signal is shown in FIG. 5.

The RReI register is sixteen-bit.

When performing a read operation, the register is always read as “0”.

The telemetry register RTIm is designed to provide a CVT 64 signal during a telemetry operation.

The timing diagram of the CVT signal is shown in FIG. 5.

The RTIm is a 16-bit register.

The register is accessible by writing and reading. Upon receipt of the signal "SR" 70, all bits of the register are reset to "0".

The register of operating modes RR is designed to control external signals RDY and RTST 64, indicating the operating mode of the system.

The RR register has the following format - RTST first bit, RDY - program record in this register and for storing code zero bit.

The register is accessible by writing and reading. Upon receipt of the signal "SR" 70, all bits of the register are reset to "0".

The discharge status of the RDY is displayed at the output of the RDY 64.

Claims (3)

1. A three-channel redundant control system comprising a first system module A, a second system module B, a third system module C, each module A, B, C comprising a processor with a P-bus processor bus, RAM, ROM, a group of majority elements, a generator, the first group, the second group, the third group of major devices, the controller of functional units, the first, second, third, fourth transceivers, the first and second controllers of the multiplex communication channel, the peripheral controller, the Q-bus and buffer RAM, soy shared with the L-bus, the first bidirectional group of inputs and outputs of which is connected to the bidirectional group of inputs and outputs of the first controller of the multiplex communication channel, the first and second inputs of which are connected to the outputs of the first and second transceivers, the input-output groups of which are the first and the second group of inputs and outputs of the system, respectively, the third and fourth groups of inputs and outputs of which are groups of inputs and outputs of the third and fourth transceiver devices, the outputs of which are connected with the first and second inputs of the second controller of the multiplex communication channel, the group of inputs and outputs of which is the second group of inputs and outputs of the L-bus, the first group of outputs of module A consisting of the first groups of outputs of the second and third groups of majority devices and connected to the first groups of inputs the second and third groups of majority devices of modules B and C, the first group of outputs of module B consists of the first groups of outputs of the second and third groups of majority devices of module B and is connected to the first groups of inputs of the second and third of groups of majority devices of module A and with second groups of inputs of the second and third groups of majority devices of module C, the first group of outputs of module C consists of the first groups of outputs of the second and third groups of majority devices of module C and is connected to the second groups of inputs of the second and third groups of majority devices modules A and B, and the second group of outputs of the second group of majority devices is connected to the first group of inputs of the peripheral controller, the first group of inputs and outputs of which are connected to the first group of inputs o-outputs of the third group of majority devices, the second group of inputs and outputs of which is connected to the first group of inputs and outputs of the Q-bus, the second group of inputs and outputs of which is connected to the first group of inputs and outputs of the controller of functional units, the second group of inputs and outputs of which are connected with groups of inputs and outputs of RAM, ROM and the first group of inputs and outputs of the first group of majority devices, the second group of inputs and outputs of which is the P-bus and connected to the group of inputs and outputs of the processor, the group of outputs of which are connected It is connected with the first group of inputs of the group of majority elements, the first group of outputs of which is connected to the group of inputs of the processor, the input of which is connected to the output of the generator, with the inputs of the first, second, and third groups of major devices, the first and second controllers of the multiplex communication channel, the peripheral controller, and the functional controller nodes, the first and second groups of outputs are connected to the groups of inputs of RAM and ROM, respectively, the third group of inputs and outputs of the L-bus is connected to the second group of inputs and outputs of the peripherals a controller, the second group of inputs of which is connected to the second group of outputs of the third group of majority devices, the third group of inputs of which is connected to the first group of inputs of the system, the second group of inputs of which is connected to the first group of inputs of the first group of majority devices, the second group of inputs of which is connected to the third group the outputs of the controller of functional nodes, the fourth group of outputs of which is connected to the first group of inputs of the Q-bus, the first group of outputs of which is connected to the first group of inputs controller of functional units, the second group of outputs of module A consists of the second output of the generator and second groups of outputs of the group of majority elements and the first group of majority devices and is connected to the third groups of inputs of modules B and C, the second group of outputs of module B consists of the second output of the generator and second groups the outputs of the group of majority elements and the first group of majority devices of module B and connected to the third group of inputs of module A and the fourth group of inputs of module C, the second group of outputs of module C consists of the second output of the generator and the second groups of outputs of the group of majority elements and the first group of majority devices of module C and connected to the fourth groups of inputs of modules A and C, the third group of inputs of the modules connected to the first input of the generator, with the second group of inputs of the group of majority elements and the third group of inputs the first group of majority devices, the fourth group of inputs of the modules is connected to the second input of the generator, with the third group of inputs of the group of majority elements and the fourth group of inputs of the first PP of majority devices, characterized in that a Q-bus interface node, a synchronization timer node, a pulse signal reception and processing node, a potential signal reception and processing node, a register node are additionally introduced into a three-channel redundant control system in each module A, B, C , the group of inputs and outputs of which is connected to the input-output groups of the node for receiving and processing potential signals, the node for receiving and processing pulse signals, the node for the Q-bus interface, the node for synchronization timers, the first group the moves of which are connected to the first groups of inputs of the register node, the node for receiving and processing pulse signals, the node for receiving and processing potential signals and the group of outputs of the Q-bus interface node, the group of inputs and outputs of which are connected to the third group of inputs and outputs of the Q-bus, the second group of outputs of which is connected to the group of inputs of the node of the Q-bus interface, the second group of outputs of which is connected to the second group of inputs of the Q-bus, and the third group of inputs of the system is connected to the second group of inputs of the register node, the group of outputs of which is the first group of outputs of the system, the second group of outputs of which is the group of outputs of the node for receiving and processing potential signals, the second group of inputs of which is the fourth group of inputs of the system, the fifth group of inputs of which is the second group of inputs of the node for receiving and processing pulse signals, the third group of inputs which is connected to the first group of outputs of the synchronization timer unit, the first output of which is connected to the first output of the system, the sixth group of inputs of which is the second group the inputs of the node of the synchronization timers, the third and fourth groups of inputs of which are connected to the third groups of outputs of the module B and C, respectively, where the input of the register node is connected to the output of the generator, the output of the receiving and processing unit of the pulse signals is connected to the input of the receiving and processing node of potential signals, and the output the controller of the functional nodes is connected to the input of the synchronization timer node, the second group of outputs of which is connected to the first group of inputs of the Q-bus interface node, the third group of outputs of the timer node in synchronization, it is the third group of outputs of module A and connected to the third groups of inputs of modules B and C, and the third group of outputs of modules B and C are connected to the fourth groups of inputs of modules C and B, respectively. 2. The three-channel redundant control system according to claim 1, characterized in that the node of the synchronization timers contains the first, second and third synchronization timers, a multiplexer, a register, the first, second and third majority elements, an OR element and an AND element, the output of which is connected to the first the input of the OR element, the output of which is the first output of the synchronization timer node, the first group of outputs of which is the group of outputs of the register, the first output of which is connected to the first input of the first AND element, the second input of which is is the first signal of the second group of inputs of the synchronization timers node, which is connected to the first groups of inputs of the first, second and third synchronization timers and the first and second inputs of the multiplexer, the output of which is the second output of the synchronization timers node and connected to the first inputs of synchronization timers, the first outputs of which are connected with the first, second and third inputs of the OR element, and the second group of outputs of the synchronization timer unit is connected to the first output groups of the first and second synchronization timers nation, the second outputs are connected to the first inputs of the first, second and third majority elements and are the third group of outputs of the synchronization timer unit, the group of inputs and outputs of which are connected to the input / output groups of the first, second and third synchronization timers and register, the second output of which is connected to the third input of the multiplexer, the first group of inputs of the node of the synchronization timers is connected to the group of inputs of the register, with the second groups of inputs of the synchronization timers, the second inputs of which are connected to the first input ohm of the synchronization timers node, the third and fourth groups of inputs of which are connected to the first and second groups of inputs of the first, second and third majority elements, the output of the first majority element is connected to the third inputs of the first and second synchronization timers, the output of the second majority element is connected to the fourth input of the second timer synchronization and the third input of the third synchronization timer, the output of the third majority element is connected to the fourth inputs of the third and first synchronization timers. 3. The three-channel redundant control system according to claim 1, characterized in that the synchronization timer comprises a control register, a configuration control register, a counter register, a hold register, a preset register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a first AND element, second element And, third element And, fourth element And, fifth element And, sixth element And, seventh element And, eighth element And, ninth element And, tenth element And, eleventh element And, twelfth element And, the thirteenth element And, the fourteenth element And, the fifteenth element And, the sixteenth element And, the OR element, the output of which is connected to the first inputs of the tenth, eleventh, fourteenth and fifteenth elements And, the outputs of which are connected to the first inputs of the register of the least significant bit counter, register register low-order bits, counter register, latch register, respectively, the input-output groups of which are connected to the input-output groups of the low-order preset register, preset register, control register configuration, the control register are a group of inputs / outputs of the synchronization timer, the second group of inputs of which is connected to the input groups of the control register, low-order preset register, preset register, low-order counter register, counter register, low-order latch register, latch register and control register configuration, the first output of which is connected to the first input of the third multiplexer, the output of which is connected to the first inputs of the third and seventh elements And and four the multiplexer, the output of which is connected to the first input of the eighth AND element, the output of which is connected to the second input of the counter register, the first and second outputs of which are connected to the second inputs of the eleventh and fifteenth AND elements, the outputs of which are connected to the first inputs of the low-order latch register and latch register moreover, the first group of outputs of the synchronization timer is connected to the outputs of the fourth, fifth, twelfth and thirteenth elements And, the first inputs of the fourth and fifth elements And are connected between battle with the output of the first element And, and the first inputs of the twelfth and thirteenth elements And are interconnected and with the output of the ninth element And, the first and second inputs of which are connected to the first (QI) and second (MI) outputs of the control register, the first (ErQI) and the second (QI) inputs of which are connected to the second input of the eighth element And and the output of the seventh element And, the second input of which is connected to the third (Off) output of the control register, the fourth (Cyc), fifth (SI) and sixth (Push) outputs of which are connected with the first inputs of the sixth element AND, the first multip an exponor and an OR element, respectively, whose second input is connected to the output of the sixth AND element, the second input of which is connected to the third (ErQ) and fourth (Q) inputs of the control register and the third input of the synchronization timer, the first output of which is connected to the output of the sixteenth AND element, the first the input of which is connected to the fifth (OffO) input of the control register, the seventh (ExP) output of which is connected to the second input of the third AND element, the output of which is connected to the third input of the OR element, the second output of the synchronization timer is connected to third the second output of the counter register and the second input of the sixteenth element And, the first group of inputs of the synchronization timer connected to the first inputs of the first and second multiplexers and the second input of the first multiplexer, the output of which is connected to the second input of the third multiplexer, the third input of which is connected to the fourth input of the synchronization timer, the first and second inputs of which are connected to the second input of the second multiplexer and the first input of the second element And, the output of which is connected to the second input of the fourth multi a lexor, the third input of which is connected to the eighth (Tic) output of the control register, the second output of the configuration control register is connected to the second inputs of the fourth and twelfth elements And and the inverse inputs of the fifth and thirteenth elements And, the ninth (Q) and tenth (M) outputs of the control register connected to the first and second inputs of the first element And, the third output of the configuration control register is connected to the third input of the second multiplexer, the output of which is connected to the second input of the second element And, the outputs of the register Novki LSBs and preset register connected to the second input of the tenth and fourteenth elements I.

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