RU2597477C1 - Frequency synthesizer - Google Patents

Abstract

FIELD: radar.

SUBSTANCE: invention relates to a frequency synthesizer. Synthesizer includes a phase-locked loop system, a direct digital synthesis (DDS) microcircuit consisting of in-series connected: a controller, a phase accumulator with feedback, an adder, an amplitude-phase converter, a DDS multiplier and a DAC, a control circuit including a phase memory device consisting of parallel sets of phase detuning registers and frequency registers and the first and the second multiplexers, a data former, herewith the phase memory device contains connected in parallel adders with feedback, and the DDS contains a sync pulse generator.

EFFECT: technical result is improvement of accuracy of determining parameters of target objects by onboard radars and reduction of weight and dimensions of the transceiving channel of the whole on-board radar due to optimization of the frequency synthesizer structure.

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Description

The invention relates to the field of radio engineering and can be used in radio communications, radio navigation systems and radar systems. In particular, the present invention is intended for high-precision airborne radar systems (radar) with a high level of noise immunity and stealth.

To ensure a high level of noise immunity and secrecy of radar systems, there is a need to generate a series of waves with different frequencies while maintaining phase coherence between series of waves of the same frequency, i.e. the need to maintain the same phase shift relative to the clock signal. In most cases, this problem is solved with the help of frequency synthesizers, providing the synthesis of many coherent frequencies.

For the synthesis of many coherent frequencies in radar systems, phase-locked loop (PLL) synthesizers are most often used. Although the advantage of PLL-based circuits is a fairly clean output signal spectrum and a much lower level of complexity compared to analog synthesizers, PLL-based synthesizers have significant drawbacks. One of them is a great adjustment time. Another disadvantage is the high level of phase noise, depending on the division ratio of the frequency divider. To reduce the total division coefficient, a frequency conversion circuit can be introduced into the frequency synthesizer or fractional division coefficients can be used. In the first case, optimization of the individual elements of the circuit is required due to the high sensitivity of the mixers to them, as well as the elimination of the problem of false frequency capture inherent in circuits based on frequency conversion, which is far from trivial tasks. In the second case, it is necessary to take into account that the fractional division mechanism is characterized by phase errors, which lead to an increased content of nonharmonic spectral components.

The most effective solution to the above problems is to use the direct digital frequency synthesis method, which is distinguished by a high resolution in frequency and phase, extremely fast frequency tuning without phase discontinuity and no need to use precise tuning of the reference frequency.

The closest in technical essence to the proposed technical solution is a frequency synthesizer (US application No. 2014240004 A1, “Phase-coherent signal generator”, published on 08.28.2014, H03B 21/00), which is adopted as a prototype.

The block diagram of the prototype device is shown in FIG. 1, where the following notation is introduced:

1 - phase locked loop (PLL);

2 - coupler;

3 - clock frequency divider;

4 is a control diagram;

5 - direct digital synthesis chip (DDS);

6 - phase memory device;

7 - counter;

8 - multiplier;

9 - frequency register;

10 - register phase detuning;

11 - the first multiplexer;

12 - second multiplexer;

13 - DDS configuration register;

14 - data generator;

15 - controller;

16 - phase accumulator;

17 - adder;

18 - amplitude phase converter;

19 - DDS multiplier;

20 - digital-to-analog converter;

f _CLK - DDS clock frequency;

f _SYS is the system frequency of the control circuit;

i is the frequency number;

POW - (phase offset word) - phase increment;

FTW - (frequency tuning word) - frequency value;

PTW - (phase tuning word) - value of phase detuning;

CW - (configuration word) - DDS configuration value;

IP - (instantaneous phase) - instantaneous phase value;

F _OUT - the output signal of the frequency synthesizer.

The frequency synthesizer contains a PLL system 1 and a coupler 2 connected in series, one output of which through a clock frequency divider 3 is connected to a control circuit 4 based on a programmable logic circuit (FPGA), and the other is directly connected to DDS 5. Control circuit 4 includes a device phase memory 6, organized as a counter 7, a multiplier 8, parallel-connected sets of frequency registers 9 and phase-off registers 10, as well as the first 11 and second 12 multiplexers, and a configuration register DDS 13, the output of which is connected n with one input of the data shaper 14. In this case, the outputs of the phase detuning registers 10 from each set are connected to the inputs of the first multiplexer 11, the output of which is connected to the multiplier 8, and the outputs of the frequency registers 9 from each set are connected to the inputs of the second multiplexer 12, the output of which is connected with one of the inputs of the data shaper 14. The other input of the shaper 14 is connected to the output of the multiplier 8.

DDS 5 contains a series-connected controller 15, a phase 16 accumulator, an adder 17, an amplitude-phase converter 18, a DDS multiplier 19, and a digital-to-analog converter 20, the output of which is the output of the frequency synthesizer. In this case, the output of the data shaper 14 of the control circuit 4 is connected to the input of the controller 15 of the DDS 5, and the outputs of the controller 15 are connected to the inputs of the phase 16 accumulator, the adder 17, and the DDS 19 multiplier.

The prototype device operates as follows.

At the input of the PLL 1, a low-frequency reference frequency signal is supplied, which is converted into a microwave signal f _CLK . From the output of the PLL 1, the signal f _{CLK is} supplied to the coupler 2, which separates this signal by power. One part of the divided microwave signal is fed to the input of the clock divider 3, and the other part is fed to the input DDS 5, where the clock signal f _{CLK is} branched and fed to the inputs of the controller 15, the battery of phase 16, and the digital-to-analog converter 20. Upon receipt of the microwave signal DDS 5 starts and waits for commands from the control circuit 4. At the same time, clock divider 3 tunes the received microwave signal in frequency and provides a sequence of clock pulses of system frequency f _SYS (f _SYS = f _CLK / K, where f _SYS is the system frequency, K is the division coefficient), by counter 7 of the phase memory device 6 and to one of the inputs of the data shaper 14, starting the control circuit 4. Counter 7 starts to accumulate clock pulses and after each clock cycle (1 clock = 1 period of the signal f _SYS ) gives the accumulated value in the form of a binary code to the multiplier 8 At the same time, a frequency selection signal (i - frequency serial number) is applied to the inputs of the first 11 and second 12 multiplexers.

The first multiplexer 11 processes the received signal and "selects" from the set of registers the desired phase detuning register 10 in accordance with the value of the frequency number i. The corresponding value of the increment of the phase POW _i in the form of binary code from the output of the selected register phase detuning 10 is supplied to one of the inputs of the first multiplexer 11, and then fed to the multiplier 8, where it is multiplied with the value accumulated in the counter 7. As a result of multiplication, the phase detuning value PTW _i is generated for a given frequency, which is input to the data former 14.

The second multiplexer 12 also processes the received signal and "selects" from the set of registers the desired frequency register 9 in accordance with the value of the frequency number i. The corresponding frequency value FTW _i in the form of a binary code from the output of the selected frequency register 9 is supplied to one of the inputs of the second multiplexer 12, and then fed to the other input of the data shaper 14.

To the free input of the data shaper 14 from the DDS 13 configuration register, the DDS CW configuration value (initial DDS operating conditions: output signal form, signal generation mode, etc.) is supplied in the form of a binary code.

The data shaper 14 processes the received data (PTW _i , FTW _i and CW) and provides a reset signal (RESET) to the input of the controller 15, resetting all DDS 5 registers, in order to avoid overwriting the recorded data on the residual. After that, the data shaper 14 sends the accumulated data on the values of the phase offset, frequency and configuration of the DDS to the controller 15 DDS 5.

The controller 15 analyzes the received code sequences (phase offset, frequency and DDS configuration values) and writes this data to the internal registers of the phase 16 accumulator along the edge of the clock frequency f _CLK .

The phase 16 accumulator adds the corresponding value of the frequency FTW _i with its own internal value (in binary code) and in each clock cycle gives the result of adding IP, which is the instantaneous value of the phase in binary code, to adder 17. At the same time, the same result of adding IP by feedback is fed to the second input of the battery of phase 16 and is added up again with the same preset corresponding frequency value FTW _i . The addition process continues continuously while the frequency synthesizer is working. To the other input of the adder 17, the controller 15 supplies the phase detuning value PTW _i , which is added to the instantaneous phase IP value.

From the output of the adder 17, the detuned phase value in the form of a binary code is fed to the input of the amplitude-phase converter 18. Converter 18 selects the sine function value in accordance with the obtained phase value and outputs the amplitude sine value to the input of the DDS 19 multiplier, to the other input of which is from the controller output 15, an ATW scaling factor is applied.

From the output of the DDS multiplier 19, the amplitude-scaled value of the signal is digitally supplied to a digital-to-analog converter 20, which converts this value into an analog form and outputs a F _OUT sine wave signal to the output of the DDS 5.

The disadvantage of the above frequency synthesizer is the complex timing algorithm of the used circuits, which requires the use of additional circuit components - a coupler and a clock divider. The prototype frequency synthesizer board is quite large.

A disadvantage is also the finite (finite) nature of the coherence of the synthesized frequencies, which is determined by the capacity of the counter phase memory used in the device. Upon reaching the value set by the digit capacity, the counter is reset to zero, there is a loss of useful information in the form of phase detuning values, which leads to a frequency mismatch at the output of the synthesizer. The lack of frequency coherence at the output of the synthesizer will lead to the fact that during further processing of the signal, an error will accumulate in the transceiver path of the airborne radar. As a result, the accuracy of determining the parameters of targets onboard radar will decrease.

The disadvantage of the synthesizer described above is the use of hardware reset of all the registers of the DDS chip, as a result of which the frequency synthesis process stops during the overwriting of the necessary registers. Those. the circuit is silent for a period and, thus, the useful time of the entire frequency synthesizer is reduced, which also leads to a decrease in the accuracy of determining the parameters of the target objects of the airborne radar.

The proposed technical solution is aimed at eliminating the above disadvantages. The technical result consists in providing high accuracy in determining the parameters of target objects by airborne radars and reducing the weight and size characteristics of the transceiver path of the entire airborne radar station by optimizing the structure of the frequency synthesizer.

The technical result is achieved by the fact that a frequency synthesizer containing a phase-locked loop, a direct digital synthesis chip (DDS), consisting of a series-connected controller, a phase feedback battery, an adder, an amplitude-phase converter, a DDS multiplier and a digital-to-analog converter, the controller outputs are connected to a phase accumulator, an adder and a DDS multiplier, respectively, and a control circuit including a phase memory device consisting of in parallel with sets of phase detuning registers and frequency registers and the first and second multiplexers, the free inputs of which are designed to receive values of the frequency serial number, and the output of each frequency register is connected to the corresponding inputs of the second multiplexer, a data shaper, one input of which is connected to the output of the first multiplexer, and its other input is connected to the DDS configuration register, while the output of the data driver is the output of the control circuit and connected to the input of the DDS controller, characterized in that the phase memory device contains parallel connected adders with feedback, the inputs of which are connected to the corresponding registers of the phase detuning, and the output of each adder is connected to the corresponding inputs of the first multiplexer, while the DDS contains a clock generator connected to the clock input of the control circuit, and communicates with each adder phase memory devices.

The structural diagram of the proposed frequency synthesizer is shown in FIG. 2, where the following notation is introduced:

1 - phase locked loop (PLL);

2 - direct digital synthesis chip (DDS);

3 - a clock generator;

4 - controller;

5 - phase accumulator;

6 - adder;

7 - amplitude phase converter;

8 - DDS multiplier;

9 - digital-to-analog converter

10 is a control diagram;

11 - phase memory device;

12 - register phase detuning;

13 - frequency register;

14 - adder;

15 - the first multiplexer;

16 - second multiplexer;

17 - data generator;

18 - DDS configuration register.

f _CLK - DDS clock frequency;

f _SYS is the system frequency of the control circuit; i is the frequency number;

POW - (phase offset word) - phase increment;

FTW - (frequency timing word) - frequency value;

PTW - (phase tuning word) - value of phase detuning;

CW - (configuration word) - DDS configuration value;

IP - (instantaneous phase) - instantaneous phase value;

F _OUT - the output signal of the frequency synthesizer.

The frequency synthesizer contains a phase locked loop (PLL) 1, the output of which is connected to the clock input of a direct digital synthesis chip (DDS) 2.

DDS 2 includes a clock generator 3, a controller 4 connected in series, a phase 5 battery in the form of an accumulating feedback adder, an adder 6, an amplitude-phase converter 7, which is a read-only memory (ROM), in which tabular values of one period are recorded sine function, and provided for processing the phase code, a DDS 8 multiplier and a digital-to-analog converter 9 for converting the amplitude-selected signal value from a digital form to analog and issuing a converter of the signal F _OUT sine wave to the DDS output, which is the output of the entire frequency synthesizer.

The frequency synthesizer also contains a control circuit 10, organized on the basis of the FPGA. The control circuit 10 includes a phase memory device 11, which is a parallel-connected sets of phase offset registers 12, frequency registers 13 and adders 14 with feedback for each frequency, while the output of each phase offset register 12 is connected to the input of the corresponding adder 14, and the first 15 and second 16 multiplexers, a data shaper 17 and a configuration register DDS 18 defining the initial operating conditions of the DDS 2. The outputs of each frequency register 13 are connected to the corresponding inputs of the first 15 multiplexer, and the outputs of each adder 14 are connected to the corresponding inputs of the second 16 multiplexer. The outputs of the multiplexers 15 and 16 are connected to the inputs of the shaper 17. The output of the shaper 17 is the output of the control circuit 10 and connected to the input of the controller 4 DDS 2. The clock input of the control circuit 10 is connected to the output of the clock generator 3 DDS 2.

The device operates as follows.

At the input of the PLL 1, a low-frequency reference frequency signal is supplied, which is converted into a microwave signal f _CLK . From the output of the PLL 1, the signal f _CLK is fed to the clock input of the DDS 2 circuit and, branching, is fed to the inputs of the controller 4, the phase 5 accumulator, the digital-to-analog converter 9, and the clock generator 3. Upon receipt of the signal f _CLK, the clock generator 3 generates the system clock frequency f _SYS and feeds the pulse train to the clock input of the control circuit 10, starting it. The system frequency f _SYS is supplied to the inputs of each adder 14 of the phase memory device 11 and to one of the inputs of the data shaper 17. The incremental values of the POW _i phase increments in the form of binary codes corresponding to this set are supplied to the other inputs of the adder 14.

The values of the increments of the phase POW _i are pre-calculated by the formula values for each frequency value FTW _i and are stored in the corresponding registers of the phase offset 12:

Where

i is the serial number of the frequency corresponding to the value of the frequency recorded in the frequency register (i = 1, 2 ..., N);

POW _i is the phase increment value of the corresponding phase detuning register in binary code;

FTW _i is the frequency value of the corresponding frequency register in binary code;

f _CLK - the value of the clock frequency supplied to the DDS;

f _SYS is the value of the system frequency supplied to the control circuit.

The FTW _i values of the frequency registers are programmed and calculated by the formula based on the values of the F _OUT frequencies synthesized by DDS:

Where

F _OUTi - the value of the i-th frequency synthesized by DDS.

Each adder 14 adds the corresponding increment value of the POW _i phase with its own internal value and outputs the addition result PTW _i , which is the phase offset value in the form of a binary code, to the corresponding output of the second multiplexer 16. In this case, the addition result of PTW _i is fed back via feedback to the other input of the adder 14 and again added up with the same specified corresponding value of the phase increment POW _i . The addition process continues continuously while the frequency synthesizer is working.

The frequency select signal (i is the frequency serial number) is applied to the free input of the second multiplexer 16, on the basis of which the multiplexer 16 selects the corresponding set of phase offset registers 12 and adders 14 (for example, i = 1, the 1st set is selected) and supplies the phase value detuning PTW _i from the selected set to the input of the data shaper 17.

The frequency select signal is also fed to the free input of the first multiplexer 15, based on which the multiplexer 15 selects the corresponding set of frequency registers 13 and supplies the frequency value FTW _i from the selected set to the input of the data former 17.

The DDS CW configuration value (initial DDS operating conditions: output signal form, signal generation mode, etc.) stored in the DDS 18 configuration register is supplied to the free input of the data shaper 17.

Shaper data 17 processes the received data (PTW _i , FTW _i and CW) and sends the accumulated phase offset values PTW _i , frequency FTW _i and DDS configuration CW to the input of controller 4 DDS 2. Sending data by shaper 17 is carried out on the front of the system frequency f _SYS .

Controller 4 analyzes the received values, sends a reset signal (RESET) to the phase 5 accumulator, resetting its internal registers, sets the operating conditions of the DDS 2 and then writes the FTW _i frequency, phase offset values to the internal registers of the phase 5 accumulator, adder 6 and DDS 8 multiplier PTW _i and ATW amplitudes, respectively.

The phase 5 accumulator adds the obtained value of the frequency FTW _i with its own internal value and outputs the result of adding IP, which is the instantaneous value of the phase in the form of a binary code, to the adder 6. In this case, the instantaneous value of the IP phase is fed back to the other input of the phase accumulator 5 and again added to the frequency value FTW _i . The addition process continues continuously while the frequency synthesizer is working. At the other input of the adder 6 from the output of the controller 4, the phase offset value PTW _i is supplied, which is added to the instantaneous value of the IP phase.

From the output of adder 6, the detuned phase value in the form of a binary code is fed to the input of the amplitude-phase converter 7. Converter 7 selects the value of the sine function in accordance with the obtained phase value and provides the amplitude value of the sine to the input of the DDS 8 multiplier, to the other input of which is from the controller output 4, a scaling amplitude coefficient ATW is supplied.

From the output of the amplitude-phase converter 7, the scaled signal value in digital form is fed to a digital-to-analog converter 9, which converts this value into analog form and outputs to the DDS 2 output, which is the output of the frequency synthesizer, a F _OUT signal of a sinusoidal shape.

To build a control circuit, it is possible to use FPGAs from Altera and Xilinx (for example, EP3C5E144I7N, EP3C25E144I7N, EP3C120F484I7N, EP4CE115F23I7N, EP4CGX150CF23I7N, etc.). To build a direct digital synthesis chip (DDS), you can use chips from Analog Devices (for example, AD9914BCPZ, AD9915BCPZ). As a PLL system, it is possible to use microcircuits from Analog Devices, Hittite (for example, HMC440QS16G, HMC830PL6GE, HMC833LP6GE, ADF4350BCPZ, etc.).

To implement the present invention, a direct digital frequency synthesis circuit of the AD9914 series is used, comprising a clock generator. A clock generator is needed to synchronize the start time of several circuits used in a frequency synthesizer. In the claimed synthesizer, only one DDS circuit is used, and the output of the clock generator is connected to the clock input of the control circuit. Generator clocks trigger a control circuit. This connection allows you to abandon the use of additional electronic components in the frequency synthesizer circuit (in particular, a coupler and a clock divider) and, thereby, reduce the weight and size parameters of the frequency synthesizer board and the transceiver path of the entire radar, respectively.

The organization of the phase memory device of the control circuit in the form of a set of adders with feedback avoids the loss of useful information in the form of phase detuning values. This is achieved by the fact that the adder is free from zeroing, i.e. it can add phase offset values for each frequency indefinitely without loss of information about the remainder of the phase. Thus, the synthesis of the frequency throughout the entire operation of the device occurs continuously without phase disruption, which helps to improve the coherence of the signal in the frequency synthesizer. Due to this, the signal processing quality in the radar transceiver path is improved, and the radar can determine various parameters of the radar target objects with high accuracy.

Also, high accuracy in determining the parameters of radar targets is achieved by using a software reset in the DDS chip. In contrast to the hardware reset used in the prototype and zeroing all the registers of the microcircuit, a software reset when a signal appears about updating the data only resets the DDS phase battery, because for the synthesis of coherent frequencies, it is necessary to control only the phase value, i.e. resetting all DDS registers is not required. This allows DDS to synthesize the old frequency while writing new data to it. Thus, the switching time of the synthesizer between frequencies is reduced due to the absence of a period of silence of the circuit after a reset, which allows you to continuously process the signal in the transceiver path of the radar.

In FIG. Figure 3 shows the graphs of the output signals of the reference and test frequency synthesizers. When checking the frequency synthesizer, two synthesizers were simultaneously launched at the same frequencies. Each synthesizer was connected to one of the channels of the oscilloscope, synchronized along the front of one of the synthesizers (reference), relative to which the initial phase of the “test” synthesizer was measured. The oscilloscope sweep was set up so that the signals of two synthesizers could be distinguished: the amplitude sweep of the tested synthesizer was changed (graph of larger amplitude) relative to the reference (graph of smaller amplitude) so that its amplitude was two times the amplitude of the other (Fig. 3A, operation time 09 : 24: 56). Then, the frequency of the tested synthesizer was changed, and since the oscilloscope was synchronized along the edge of the signal from another synthesizer, the graph started to “tremble” (Fig. 3B, operation time 09:25:24). After that, the frequency of the tested synthesizer was again switched to the previous one. The synthesizer signal thus “rose” to the previous values of the initial phase relative to the reference synthesizer signal (Fig. 3B, operation time 09:25:56).

Tests have shown that when switching frequencies, the signals of the frequency synthesizer at different points in time remain coherent. Due to this, the signal processing quality in the radar transceiver path is improved, and the radar can determine various parameters of the radar target objects with high accuracy.

Claims (1)

A frequency synthesizer containing a phase-locked loop, a direct digital synthesis chip (DDS), consisting of a series-connected controller, a phase feedback battery, an adder, an amplitude-phase converter, a DDS multiplier and a digital-to-analog converter, while the controller outputs are connected to a phase accumulator, an adder and a DDS multiplier, respectively, and a control circuit including a phase memory device consisting of parallel sets of phase detuning registers and frequency registers and the first and second multiplexers, the free inputs of which are designed to receive frequency serial number values, and the output of each frequency register is connected to the corresponding inputs of the second multiplexer, a data shaper, one input of which is connected to the output of the first multiplexer, and its other input is connected to the register DDS configuration, while the output of the shaper is the output of the control circuit and is connected to the input of the DDS controller, characterized in that the phase memory device contains steam llelno connected adders with feedback inputs are connected to the respective registers of the phase detuning, and each combiner output being connected to respective inputs of the first multiplexer, the DDS comprises a clock generator connected to the clock input of the control circuit, and communicates with each adder phase memory device.

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