RU2565890C1 - Device to determine parameters of maintenance strategy of system facilities - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises: first memory unit 1, where source data arrives from 1-7 inlets of the device, the second memory unit 27, where the optimal value of maintenance period for the most complicated system facility is stored, a shift register 2, delay elements 3, 17, 18, 25, 35, valves 4, 6, 19, an anticipatory multivibrator 7, OR circuits 8, 12, accumulating summators 9, 11, non-linearity units 10, 14, 20, 22, a trigger 13, multiplication units 15, 16, 24, 28, 37, division units 34, 36, integrators 9, 11, subtractors 21, 23, a comparator 26, integrators 30, 32, summators 5, 31, 33 and a counter 29.

EFFECT: increased accuracy due to taking into account difference of values of facility fault intensity during variation of their functioning mode.

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Description

The invention relates to computer technology, in particular to control devices. It can be used in scientific research and the practice of operating technical systems to determine maintenance periods that ensure the required readiness of the system for use and the rhythm of their maintenance.

There are devices [3, 4] that allow you to determine the optimal periods of maintenance of system tools. Their scope is limited to continuous use systems. Known devices [5, 6], which determine the optimal periods of control and management of the technical condition of products with a variable mode of use. The scope of these devices is limited to products that are not directly part of complex complexes.

The closest in technical essence to the claimed invention is a device [6], containing a memory block, six gates, two accumulating adders, four nonlinearity blocks, two integrators, five adders, two subtractors, four multiplication blocks, a division block, an OR circuit, a multivibrator, four delay elements, two triggers, a comparator and four memory elements. As already noted, the scope of this device is limited to functionally separate products.

The aim of the proposed technical solution is to expand the functionality and scope of the device. The goal is achieved by introducing into the prototype circuit a number of functional elements that determine the periods of service of the system tools, allowing you to create a rational temporary program of technical maintenance of the system as a whole.

The system, as you know, includes a combination of means with numbers i = 1, ..., n, in relationships and connections with each other, forming a certain integrity, unity. Quantitative indicators of reliability and maintainability of the system tools are different, therefore, the optimal terms for their maintenance are different.

Each tool continuously spends its reliability potential, and the spending rate depends on the mode of use of the tool [1]. The change in mode is manifested in a change in the failure rate. This must be taken into account when determining the optimal time for maintenance of funds.

The process of applying various systems is cyclical in nature. Each cycle may include the operation of funds in nominal mode, in light mode, as well as in rest mode. Figure 1 presents a generalized diagram of the operation of the system. Each means corresponds to the duration of the application cycle τ, during which t ₁ is the duration of application of the agent in nominal mode with a load factor k _n = 1. In this case, the failure rate of the tool is λ _1i , where i is the number of the tool. On the interval t ₂ = τ-t ₁ various systems, depending on the technology of their application and the actual load, can be in one of the following modes:

a) lightweight mode in connection with the reduction of the load (for example, means of energy systems of continuous use);

b) rest after use (for example, technical equipment of enterprises working in one or two shifts).

In this regard, in the time interval t ₂ the failure rate λ _2i will have different values λ _2i = λ _1i k _n corresponding to a change in the load coefficient k _n . Note that, according to [2], in the case of a facilitated mode of operation of the means k _n <1, and in the rest mode, according to [1] 0 <k _n << 1.

To maintain the system in working condition, each of its facilities is periodically serviced and the time τ _{obsi is spent} . This takes an in-depth control of the state during the time τ _k1i, preventive maintenance and restoration of health in the event of failure, to that spent time τ _Bi, and at the end of this work is carried out a control check of state funds during the time τ _k2i. Note that the control of the technical condition is carried out in the conditions of the nominal operating mode. Therefore, at time intervals τ _k1i and τ _k2i , the failure rate will be equal to λ _1i . To carry out preventive and repair work, the funds are transferred to the rest mode, which corresponds to the failure rate λ _2i . In this regard, the total duration of the preventive work of each agent is expressed as follows:

or

- вероятность безотказной работы i-го средства системы на соответствующем интервале времени.Where

- the probability of failure-free operation of the i-th system tool on the corresponding time interval.

The duration of the service period T _i includes many application cycles of duration τ _j , j = 1, ..., m each, i.e.

Where

The duration T _qi of the service cycle of the i-th facility is

The probability of failure of the tool on the time interval T _i is expressed as

For many systems, it is true that sudden failures prevail in them, and each means corresponds to the exponential law of the distribution of the time of occurrence of failures. In this case, the following takes place:

The working time of the system means Τ _fi on the time interval T _i is determined by the formula

A comprehensive indicator of the quality of the functioning of funds is the coefficient of technical use (analogue of the coefficient of availability). Its value is expressed by the following relation

An analysis of the function K _g (T) shows that as Τ → 0 and as Τ → ∞, the function K _g (T) → 0. There is a maintenance period T ^* at which the availability factor has a maximum value of K ^* _g . Each of the system tools corresponds to an individual optimal maintenance period T ^* _i . The set of values Τ ^* _i , corresponding to the set of system tools, forms in time such a set of maintenance cycles that its practical implementation will be irrational or impossible. Therefore, it becomes necessary to streamline this aggregate by finding compromise, close to optimal values of service periods for each system tool. A constructive variant of ordering is to ensure the multiplicity of periods for servicing funds and the fulfillment of the condition

where T ^* _min is the optimal period of maintenance, providing max K _g (T) of the least reliable means of the system;

The beginning of each time interval q _i T ^* _min will correspond to the beginning of the service cycle of one or more close-in-reliability system tools. A separate tool will be serviced with a period close to optimal. Since the periods of servicing individual funds are found in terms of multiplicity, this ensures rational organizational maintenance of the funds of the system as a whole.

The proposed model can be implemented in hardware using the proposed device, a diagram of which is presented in Figure 2.

The device contains: the first memory block 1, which receives input data from 1-7 inputs of the device, shift register 2, delay elements 3, 17, 18, 25, 35, valves 4, 6, 19, a waiting multivibrator 7, OR circuit 8 , 12, accumulating adders 9, 11, non-linearity blocks 10, 14, 20, 22, trigger 13, multiplication blocks 15, 16, 24, 28, 37, division blocks 34, 36, integrators 9, 11, subtractors 21, 23, a comparator 26, a second memory unit 27, integrators 30, 32, adders 5, 31, 33 and a counter 29.

Before starting the operation of the device, the initial data (input values): λ _1i , t _1i , λ _2i , (τ _к1i + τ _к2i ), τ _вi , (τ _к2i + τ _вi ), τ are entered into the first memory block 1 through its inputs 1-7 respectively. Note that the memory unit 1 is divided into n zones according to the possible number of system tools.

The device operates as follows.

By the “Start” signal coming from the eighth input of the device, the shift register 2 is reset. The same signal, delayed by the first delay element 3, passing through the first circuit OR 8, sets the unit in the first category of the shift register 2, providing the reading of the values of the input quantities corresponding to the first (most complex and least reliable) means of the system from the first memory block 1 on the associated functional elements of the device. In addition, the “Start” signal sets the trigger 13 to a single state, the second memory block 27 and the counter 29 are reset to zero, and, passing through the second circuit OR 12, is fed to the input of the multivibrator 7. According to the signal of the shift register 2, the values of the input quantities corresponding to the first system tool, from the first memory unit 1 to the associated functional elements of the device. The output (single) signal of the multivibrator 7 opens the first 4 and second 6 valves. This ensures that the values of the parameter t ₁ from the second output of the memory unit 1 are received once in the first accumulating adder 9, and the values of the parameter τ from the seventh output of the memory unit 1 into the second accumulating adder 11. The single signal of the multivibrator 7 is also fed to the control inputs of the first 9 and second 11 accumulating adders, ensuring the implementation of the process of accumulation and transmission of the resulting data to the associated elements of the device circuit (the scheme and operating procedure of the accumulating adder are shown in patent No. 223 3482, 2004, G07C 3/08).

The output signal of the first accumulating adder 9 is transmitted to the second inputs of the third nonlinearity block 20, the first integrator 30 and the first subtracter 21. The output signal of the second accumulating adder 11 is input to the third delay element 18, as well as to the first inputs of the first subtractor 21 and the third adder 33. The subtractor 21 is realized difference t ₂ = τ-t _1, and is transmitted to the second inputs of the fourth unit 22 and the non-linearity of the second integrator 32. From the first output of the first storage unit 1 to the first inputs of the second 14 and third 20 blocks Nelin NOSTA transmitted value λ ₁ failure rate, and the third output of the storage unit 1 to the first input of the fourth unit 22 and the non-linearity to the second input of the first non-linearity unit 10 receives the value of the failure rate λ _2. In the third non-linearity block 20, a signal P ₁ (t ₁ ) is generated in accordance with (6) and transmitted to the first inputs of the fourth multiplication block 28 and the first integrator 30. In the fourth non-linearity block 22, in accordance with (7), a signal P ₂ (t ₂ ) and is transmitted to the first input of the second integrator 32 and to the second input of the fourth multiplication unit 28. In the first integrator 30, the working state time t _ф1 (t ₁ ) is calculated, and in the second integrator 32, the working state time t _ф2 (t ₂ ) is calculated. The output signals of the integrators 30 and 32 are respectively supplied to the first and second inputs of the second adder 31. The total value of t _f (τ) obtained in accordance with (10), from the output of the second adder 31 is transmitted to the second input of the first division unit 34.

Simultaneously with the above, the value of τ _obs . Thus the output from the fourth memory unit 1 to the second input of the second block 14 and the non-linearity to the first input of the first adder 5 receives the value of τ + τ _{k1 k2.} From the fifth output value of τ 1 _in the storage unit is transmitted to the second input of the first adder 5 and the first input of the first nonlinear unit 10. The output signal of the adder 5, an appropriate amount of τ + τ _{k1 k2} + τ _a, is supplied to a first input of the second subtractor 23. In blocks of nonlinearities 10 and 14, the values of Ρ (τ _in ) and Ρ (τ _к1 + τ _к2 ) are formed, respectively. The output signals of these non-linearity blocks go to the inputs of the first multiplication block 15. The result of multiplying Ρ (τ _in ) Ρ (τ _к1 + τ _к2 ) from block 15 is transmitted to the second input of the second multiplication block 16, the first input of which is from the sixth input of the first memory block 1, the value of the sum τ _in + τ _k2 arrives. The output signal of block 16 is transmitted to the second input of the third block of multiplication 24, the first input of which from the fourth block of multiplication 28 receives a signal corresponding, according to (5), to the value Ρ (τ) = P ₁ (t ₁ ) P ₂ (t ₂ ). In the third block of multiplication 24, the product of its input quantities is realized and transmitted to the second input of the second subtractor 23. In the subtractor 23, the value of τ _obs is displayed by the relation (1) and transmitted to the second input of the third adder 33. The signal corresponding to the sum τ + τ _Obs , from the adder 33 enters the first division unit 34 through its first input. The division result corresponding to the availability factor K _g calculated according to (11), from the output of the division block 34 goes directly to the first input, and through the fifth delay element 35 to the second input of the comparator 26. At the beginning of the operation of the device, the inequality Κ _rj (τ)> K _rj-1 (τ). Therefore, the control signal will appear at the first output of the comparator 26 and through the second OR circuit 12 it will enter the multivibrator 7. A single output pulse of the multivibrator 7 will open the first 4 and second 6 valves. As a result of this, the values of the output values of the first 9 and second 11 accumulative adders will increase by t ₁ and τ, respectively. Next, the process of calculating the availability coefficient K _rj (T) and comparing it with K _rj-1 (T) will be repeated, but with the values of Τ _φi , T _i , τ _obsi updated in accordance with (10), (2), (1) . As soon as it turns out in the comparator 26 that the next value of the availability factor is less than the previous one, a control signal will appear at the second output of the comparator 26 and will be fed to the input of the fourth delay element 25, to the second (allowing) input of the second memory unit 27, and to the input of the counter 29. At that at the same time, the output signal of the third delay element 18, corresponding to the optimal value of the service period of the means, will go directly to the first (information) input of the division unit 36, and through the third gate 19 to the second memory unit 27. B Khodnev unit 27 enters a signal dividing unit 36 and multiplication unit 37. At this stage of the device values of the input signal dividing unit 36 are equal, so its output to the first input of the fifth multiplier block 37 go signal corresponding unit. As a result, the output of the multiplication unit 37, which is the second output of the device, receives the optimal value of the service period of the first device of the system. At the output of the counter 29, which is the first output of the device, there will be a signal corresponding to the first means of the system.

Simultaneously with the above, the signal of the comparator 26 from its second output through the fourth delay element 25 will go to the input of the second delay element 17, as well as to the inputs "reset to zero" of the first 9 and second 11 accumulating adders, preparing them for work by the next means of the system. The output signal of the delay element 17 switches the trigger 13 to the zero state, and, having passed through the OR 8 circuit, translates the shift register 2 to read the initial data from the memory unit 1, corresponding to the next system tool. In addition, the output signal of the delay element 17 through the OR circuit 12 is transmitted to the input of the multivibrator 7, as a result of which the control signal from its output will go to the control inputs of the first 4 and second 6 gates, as well as the first 9 and second 11 accumulating adders. Further, the process of determining the optimal period of maintenance of this tool is similar to that discussed above.

With the appearance of the signal at the second output of the comparator 26, the value of the output signal of the counter 29 increases by one, the optimal value of the service period of the first system tool from the second memory unit 27 will go to the second inputs of the division unit 36 and the multiplication unit 37. The optimal value of the service period of this tool from the output of the element delay 18 is transmitted to the division unit 36 through its first input. The whole division result obtained in accordance with (13) is transferred from the output of block 36 to the first input of the multiplication block 37. The calculated value of the service period T _i = q _i T ^* _min from the output of block 37 will go to the second output of the device.

Similarly to the above, the values of the output values of all means of the system will be determined. After completion of the last cycle of the device, the control signal will appear in the n + 1 bit of register 2, which will provide an indication of the end of the operation. The output of this discharge is the third output of the device.

This completes the operation of the device.

The positive effect that can be obtained from the use of the proposed technical solution is that the device allows, on the basis of the principle of multiplicity, to determine the periods of maintenance of a complex system, calculated taking into account the variable mode of their use. The practical implementation of the proposed solution is rational from the point of view of organizing the maintenance and expenditure of material and time resources for the maintenance of the system, as well as the use of reliable resources of the tools that make up the system. The calculated values of the service periods allow you to reasonably plan the application and technical operation of the system.

  Information sources

1. Sedyakin N.M. About one physical principle of the theory of reliability. - Proceedings of the Academy of Sciences of the USSR, OTN, Technical Cybernetics, 1966, No. 3.

2. Polovko A.M. Fundamentals of reliability theory. - M.: Science, 1964.

3. Grishin V.D., Sokolov B.V., Petrova I.A. RF patent No. 2429542. IPC G07C 3/08, G05B 23/02, 2011.

4. Grishin V.D., Sokolov B.V., Ikonnikova A.V. RF patent No. 2429543. IPC G07C 3/08, G06F 11/30, G06F 17/00, 2011.

5. Sokolov BV, Grishin VD, Zelentsov VA, Tsivirko EG RF patent No. 2476934. IPC G07C 3/08, 2013.

6. Sokolov BV, Grishin VD, Zelentsov VA, Maydanovich OV RF patent No. 2479041. IPC G07C 3/08, 2013.

7. Tetelbaum I.M., Schreider Yu.R. 400 circuits for ABM. - M .: Energy, 1978.

Claims (1)

A device for determining the parameters of the maintenance strategy of the system tools, containing the first and second delay elements, the third valve, the first memory block, the information inputs of which 1 to 7 are the corresponding inputs of the device, and the first output is connected to the first inputs of the second nonlinearity block and the third nonlinearity block whose output is connected to the first inputs of the fourth multiplication unit and the first integrator, the output of which is connected to the first input of the second adder, and the second input to the second inputs the third nonlinearity block and the first subtractor, as well as with the output of the first accumulating adder, the first input of which is connected to the output of the first valve, the first input of which is connected to the second output of the first memory block, and the second input, together with the second input of the first accumulating adder, to the output of the multivibrator and to the second inputs of the second accumulating adder and the second gate, the first input of which is connected to the seventh output of the first memory block, and the output is connected to the first input of the second accumulating adder, the output to which is connected to the input of the third delay element and to the first input of the first subtractor, the output of which is connected to the second inputs of the second integrator and the fourth nonlinearity block, the first input of which is connected to the third output of the first memory block and the second input of the first nonlinearity block, and the output with the second input the fourth unit of multiplication and with the first input of the second integrator, the output of which is connected to the second input of the second adder, the output of which is connected to the second input of the first division unit, the first input of which connected to the output of the third adder, and the output to the input of the fifth delay element and to the first input of the comparator, the first input of which is connected to the second input of the second OR circuit, the output of which is connected to the input of the multivibrator, and the first input with the first input of the trigger and the eighth input of the device, the fifth output of the first memory block is connected to the second input of the first adder and to the first input of the first nonlinearity block, the output of which is connected to the first input of the first multiplication block, the second input of which is connected to the output of the second nonlinear block , and the output with the second input of the second multiplication unit, the output of which is connected to the second input of the third multiplication unit, the first input of which is connected to the output of the fourth multiplication unit, and the output to the second input of the second subtractor, the first input of which is connected to the output of the first adder, and the output with a second input of the third adder, characterized in that a shift register, a first OR circuit, a fourth delay element, a totalizing counter, a second division unit, a second memory unit, a fifth multiplication unit are introduced, the eighth input being the device is connected to the input of the first delay element, with the first input of the summing counter, with the reset to zero input of the second memory block and with the first input of the shift register, the second input of which is connected to the output of the first OR circuit, the first input of which is connected to the output of the first delay element and the second input is connected to the third input of the second OR circuit, with the second input of the trigger and with the output of the second delay element, the input of which is connected to the inputs "reset to zero" of the first and second accumulating adders, as well as to the output of the fourth the delay element, the input of which is connected to the second output of the comparator, with the second inputs of the second memory block and the summing counter, the output of which is the first output of the device, the second output of which is the output of the fifth multiplication block, the second input of which is connected to the output of the second memory block and to the second input the second division unit, and the first input with the output of the second division unit, the first input of which is connected to the output of the third delay element and to the information input of the third valve, the control input of which is connected inen with a trigger output, and the output with the first input of the second memory block, the third output of the device is n + 1 shift register output, from 1 to n outputs of which are connected to the corresponding control inputs of the first memory block, the fourth output of which is connected to the second input of the second block nonlinearity to the first input of the first adder, and the sixth output to the first input of the second multiplication unit, the output of the second accumulating adder is connected to the first input of the third adder, and the output of the fifth delay element with the second input to Oparator.

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