RU2543939C2 - Pseudodifferential cascade output buffer - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises the main controlled stable current source, the main reference voltage generator, a pair of the main current sources, a pair of the main keys, the main key backup, a pair of terminators, a pair of differential coils, an auxiliary current source, a pair of auxiliary keys, the auxiliary current source backup, auxiliary key backup, an auxiliary controlled stable current source and an auxiliary reference voltage generator.

EFFECT: reduction of output signal jittering and increase of differential sweep range for output voltage by ensuring probability of high-speed data flow transfer.

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Description

The invention relates to the field of switching environments for computing systems and can be used as an output buffer stage of the transmitter in high-speed multi-channel interfaces.

Known output buffer, which includes a common current source, a differential key pair, terminating resistors (US, Application No. 007446576 B2, CL HN 73/36, published. 2008).

The disadvantage of the described buffer is associated with the effect of decreasing the magnitude of the differential voltage of the output signal and increasing the reflection loss from the magnitude of the high level of the input signal.

The closest in technical essence and the achieved result is a pseudo-differential cascode output buffer, consisting of a main controlled source of stable current, a driver of the main reference voltage, a pair of main current sources, a pair of main keys, a backup of the main switch, a pair of termination resistors and a pair of differential coils (US, Patent No. 2013/0002311, CL H01H 73/36, published 2013).

The disadvantages of the described buffer are: firstly, it provokes additional jitter of the output signal caused by an increase in the frequency-dependent nature and degradation of parameters such as the separation time between the direct and inverse signals, imbalance of the front and the cutoff, and secondly, the buffer is unable to form the output voltage with a large differential scope.

The objective of the invention is to provide a device for transmitting a high-speed data stream.

This problem is solved by the fact that the pseudo-differential cascode output buffer, consisting of a main controlled source of stable current, a driver of the main reference voltage, a pair of main current sources, a pair of main keys, a backup of the main key, a pair of termination resistors and a pair of differential coils, according to the invention is additionally equipped with auxiliary a current source and a pair of auxiliary keys associated with a pair of primary current sources and a pair of primary keys, and contains an auxiliary backup Yelnia current source and doubler auxiliary key associated with the main reference voltage generator and a backup master key, the cascode output buffer comprises a controllable auxiliary source of constant current generator and the auxiliary reference voltage associated with the auxiliary power source and a backup of the auxiliary current source.

The technical result from the use of this invention is to reduce jitter of the output signal and increase the range of the differential amplitude of the output voltage by enabling the transmission of a high-speed data stream.

The invention is illustrated in the drawing, where figure 1 shows a schematic diagram of a pseudo-differential cascode output buffer.

The buffer consists of a driver of the main reference voltage on the transistor 1, the main current source on the transistor 2, the main current source on the transistor 3, the primary key backup on the transistor 4, the auxiliary key backup on the transistor 5, the primary key on the transistor 6, the auxiliary key on the transistor 7 , the auxiliary key on the transistor 8, the main key on the transistor 9, the driver of the auxiliary reference voltage on the transistor 10, the backup of the auxiliary current source on the transistor 11, the auxiliary current source on the transistor 12, a terminating resistor with a variable resistance 13, a terminating resistor with a variable resistance 14, a differential coil 15, a differential coil 16, a main controlled source of stable current 17, an auxiliary controlled source of stable current 18, a power source 19, a power source 20 .

The output buffer works as follows. The main controlled source of stable current 17 is connected to a power source 19, forming a stable reference current. The generator of the main reference voltage 1 converts the stable reference current into the main reference voltage Ucm1. The voltage Ucm1 is supplied to the gates of the main current source on transistor 2 and the main current source on transistor 3, forming the main current, the value of which is the same in both shoulders of the buffer. The source of the main current source on the transistor 2 is connected in series with the main key on the transistor 6, forming a cascode. The source of the main current source on the transistor 3 is connected in series with the main key on the transistor 9, forming a cascode. The main switch on transistor 9 operates inversely with respect to the main switch on transistor 6. If the input signal Uin opens the main switch on transistor 6, the current of the main current source on transistor 2 generates a voltage drop across the terminating resistor with variable resistance 13, decreasing the potential at the output of Uout. At the same time, the input signal Uinm closes the main switch on the transistor 9, there is no current of the main current source on the transistor 3, there is no voltage drop across the terminating resistor with a variable resistance of 14, the potential on the U _{EXT is} pulled to the power source 19.

In the process of leaving the primary key on the transistor 6 or the main key on the transistor 9, in the node U2 or U3, a residual charge is formed. A portion of this charge remaining at the time of opening the main key on transistor 6 or the main key on transistor 9 depends on the cutoff time, which increases the frequency-dependent nature of the output buffer. To eliminate this effect, the potentials in the node U2 or U3 are controlled by an auxiliary current source on the transistor 12. The shoulder to which the auxiliary current will be supplied is selected by the auxiliary key on the transistor 7 and the auxiliary key on the transistor 8. The auxiliary key on the transistor 8 is inverted relative to the auxiliary the key on the transistor 7.

Thus, the main key on the transistor 6 and the auxiliary key on the transistor 7 work in antiphase to the main key on the transistor 9 and the auxiliary key on the transistor 8. When a logical zero is supplied to the input Uinput, the logical unit is at the input Uinmm, the main key on the transistor 6 is in the cutoff , the auxiliary key on the transistor 8 is saturated, passing the current of the auxiliary current source on the transistor 12, forming a certain potential in the node U1. At the same time, the auxiliary key on the transistor 7 is in the cutoff, and the main key on the transistor 9 is saturated, passing the current of the main current source on the transistor 3. If the input signal Uinp / Umm is inverted to the opposite, the operation is performed exactly the opposite.

In order for the current of the auxiliary current source on the transistor 12 not to reduce the differential amplitude of the output voltage, its value should be at least two orders of magnitude less than the current value of the main current source on transistor 2 or the main current source on transistor 3.

Monitoring potentials at nodes U2 or U3 makes it possible to increase the voltage of power supply 19 by increasing the thick oxide of the gates of the driver of the main reference voltage at transistor 1, the main current source at transistor 2, and the main current source at transistor 3, which will increase the range of the differential output voltage range .

To form an auxiliary current source on the transistor 12, an auxiliary controlled constant current source 18 is used, connected to the power source 20. The auxiliary reference voltage generator on the transistor 10 converts the current of the auxiliary controlled constant current source 18 into a reference voltage Ucm2, which is supplied to the gate of the auxiliary current source on transistor 12.

It is necessary to reduce the error of current reflection in the current mirror, which consists of the driver of the main reference voltage on the transistor 1 and the main current source on the transistor 2, aligning the potential of the node U1 with the potential of the node U2. It is also necessary to reduce the error in the reflection of the current in the current mirror, which consists of the driver of the main reference voltage on the transistor 1 and the main current source on the transistor 3, aligning the potential of node U1 with the potential of node U3. To do this, in the source circuit of the generator of the main reference voltage on the transistor 1 is connected to the alternator of the main key on the transistor 4 and a series-connected alternator of the auxiliary key on the transistor 5 and the alternator of the auxiliary current source on the transistor 11. The alternator of the primary key on the transistor 4 emits the main key on the transistor 6 or the main key on the transistor 9. The backup key on the transistor 5 emits an auxiliary key on the transistor 7 or an auxiliary key on the transistor 8. The backup ceiling elements on the transistor current source 11 emits an auxiliary current source transistor 12. The gates of the doubler main switch transistor 4 and the auxiliary backup key on the transistor 5 is connected to a power source 20, keeping them constantly in an open state.

A differential coil 15 and a differential coil 16 are needed to isolate the output capacitance of the drains of the main current source on transistor 2 and the main current source on transistor 3, reducing reflection losses.

Thus, the proposed invention allows to reduce the jitter of the output signal by reducing its own contribution to the deterioration of such characteristics as the time span between the direct and inverse signals, the imbalance of the front and cut. Also in the proposed invention increased the range of the differential amplitude of the output voltage.

Claims (1)

A pseudo-differential cascode output buffer consisting of a main controlled source of stable current, a driver of the main reference voltage, a pair of main current sources, a pair of main keys, a backup of the main key, a pair of termination resistors and a pair of differential coils, characterized in that it is additionally equipped with an auxiliary current source and a pair of auxiliary keys associated with a pair of primary current sources and a pair of primary keys, and contains an alternate auxiliary current source and an understudy auxiliary key associated with the primary driver voltage reference and the backup of the primary key, while the cascode output buffer contains an auxiliary controlled source of stable current and the auxiliary driver voltage reference associated with the auxiliary current source and the backup of the auxiliary current source.