RU2542939C1 - Direct transform receiver having quadrature three-phase architecture, method for direct signal transform using said receiver and method of controlling tuning of said receiver - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: direct transform receiver having a quadrature three-phase architecture comprises: a radio frequency amplifier, a splitter, first and second balance mixers, a frequency synthesizer, first and second low-pass filters, first and second multiplying digital-to-analogue converters, first, second and third automatic controllers, a converter for converting two-phase voltage to three-phase voltage, a clock generator, first and second analogue-to-digital converters, a data bus register and a microcontroller.

EFFECT: improved image interference rejection while simplifying the device.

5 cl, 5 dwg

Description

The invention relates to the field of radio engineering, in particular to direct conversion radio receivers, and can be used as part of software-defined radio receivers (Software Defined Radio), as well as smartphones and tablet computers to create embedded software and hardware applications for radio and television broadcasting stations.

There are a large number of technical solutions for the reception of broadcast signals, and methods for controlling the settings of the radio receiving device. All their diversity can be divided into three large groups: direct amplification receivers, heterodyne receivers, superheterodyne receivers (see, for example, the article Polyakov VT, heterodyne reception. Radio Yearbook-88. M .: DOSAAF, 1988, p.24), moreover, the adjustment of such receiving devices is carried out mechanically using a capacitor of variable capacitance or a variometer, with the help of which a smooth change in inductance is carried out.

Known direct gain receivers described in the monograph V. Yershov Simple direct gain transistor receivers. M .: DOSAAF, 1972. These receivers, despite their simplicity, are not widely used due to their low selectivity and sensitivity.

Known superheterodyne receivers are described, for example, in RF patents No. 2062547, 2379836, 2381621, US patents No. 4666995, 4776040, 5280639, book Design of radio receivers. Ed. A.P. Sivers. M: Soviet Radio, 1976.

The disadvantage of this class of receivers is the presence of a mirror receiving channel and the need to use a concentrated selection filter (FSS) to obtain the necessary selectivity for the adjacent channel. The use of such a filter (ceramic, quartz, on LC-elements) prevents the creation of such receivers in microelectronic design.

There are known direct frequency conversion receivers, receivers with zero (Zero-IF) or near-zero (Low-IF) intermediate frequency or in domestic terminology asynchronous heterodyne receivers, described, for example, in the works of Tony J. Rouphael. RF and Digital Signal Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach. Elsevier Inc., 2009; Jeffrey H. Reed. Software Radio. A Modern Approach to Radio Engineering, Prentice Hall PTR, 2002; Polyakov V.T. Radio amateur on the technique of direct conversion. M .: Patriot, 1990; U.S. Patent Nos. 4,736,390, 5,761,615, 6,073,001, 7,272,375; in UK patent No. 2460418; in the description of the Si476x chip family (Si476x - High-Performance Automotive AM / FM Radio Receiver and HD Radio Tuner. Silicon Labs / http://www.silabs.com/Support%20Documents/TechnicalDocs/Si476x-short.pdf). This class of receivers has been overwhelming in recent years due to the presence of important advantages compared to superheterodyne receivers: the input RF signal with the help of quadrature balanced mixers is immediately converted to low-frequency, and all further operations to filter the signal from noise through adjacent and mirror channels, demodulation are carried out using low-frequency circuitry, which is the best suited for the CMOS technology used to create systems on a chip (System-on-Chip) (Mikkelsen JH Front-End Architectures for CMOS Radio Receivers. Aalborg University, IR-96-1003, 1998; also US Patent No. 7,272,375). So, instead of FSS bandpass filters, low-pass filters are used, which can be implemented as digital, active, or as filters on switched capacitors (see, for example, Makhlin A. Filters on switched capacitors. Components and technologies. No. 6, 2008).

However, the known direct frequency conversion receiving devices are very sensitive to imbalance in the quadrature channels both in amplitude and phase ratios of the quadrature signals, which must have an exact phase shift of 90 ° relative to each other. If this condition is violated, the interference suppression through the side reception channels decreases sharply. So, in the monograph Polyakov V.T. Radio amateur on the technique of direct conversion. M .: Patriot, 1990, p. 56, it is noted that imbalance in amplitude of 1 ÷ 2% and in phase of 1 ÷ 2 ° leads in practice to suppress interference by side receiving channels (mainly a mirror channel) by no more than 30 ÷ 40 dB. It is also noted there that to suppress interference by 50 dB (desired level), the amplitude imbalance should be less than 0.6%, and the phase deviations should be less than 0.3 °. Even greater requirements for the exact balance of amplitudes and phases are imposed when using a low-frequency intermediate frequency (Low-IF; usually selected from the condition f _IF > (1 ÷ 2) · f _in , where f _IF is the low-frequency intermediate frequency, f _{in the} high frequency useful signal). So, in an article by Crols J., Steyaert MSJ Low-IF Topologiers for High-Performance Analog Front Ends of Fully Integrated Receivers. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 45, No.3, March 1998, states that in the case of zero intermediate frequency (Zero-IF), the useful and unwanted signals of the mirror channel are in the same frequency band and have the same parameters. Therefore, to obtain a signal to noise ratio of 40 dB, it is sufficient to suppress the unwanted signal of the mirror channel by 40 dB as well. In the case of using Low-IF, the unwanted signal of the mirror channel may be larger than the useful signal, because in this case, the mirror channel may fall on the adjacent channel. For example, if the unwanted signal in the band of the mirror channel exceeds the useful by 30 dB, then to obtain the same signal-to-noise ratio of 40 dB, the degree of suppression of noise in the mirror channel should be already 70 dB.

To restore the balancing of quadrature signals, mainly algorithmic methods for processing quadrature signals using a signal processor are proposed. Such technical solutions are given in the works of Windisch M., Fettweis G. Blind I / Q imbalance parameter estimation and compensation in low-IF receivers. Technische Universitat Dresden, Germany, 2004; Valkama M., Renfors M. Digital filter design for I / Q imbalance compensation. Tampere University of Technology, 2000. However, in the case of using Low-IF, when the sampling frequency of the analog-to-digital converter (ADC) is only 2-4 times higher than the upper frequency of the useful signal, the error of approximation and quantization of the ADC is added to the phase unbalance errors ( Valkama M., Renfors M. Digital filter design for I / Q imbalance compensation. Tampere University of Technology, 2000). It follows that it is advisable to compensate for unbalancing errors before the ADC, or use faster and more accurate ADCs with a large volume of processed samples in the signal processor.

Among the known methods for controlling the settings of such receivers, a method stands out in which tuning is carried out using a mechanical wheel - a potentiometer - connected to the ADC. The digital code received at the ADC output controls the frequency synthesizer of the receiver. This method is implemented, for example, to manage settings in the Si482x and Si484x families of Silicon Labs chips (Designing Wheel-Tuned, Digital-Display Radios with Next-Generation Radio ICs. Http://www.silabs.com/Support0/o2QDocuments/TechnicalDocs /ATDD-Radio-White-Paper.pdf; Si4825 Demo Board User's Guide. Http://www.silabs.com/Support%20Documents/TechnicalDocs/Si4825DEMQ.pdf). The disadvantage of this solution is the presence of a mechanical unit - a multi-turn potentiometer with a limited service life.

Another well-known method of managing receiver settings is a method of control using a two-dimensional graphical user interface (GUI, Graphical User Interface) displayed on the screen of a personal computer using special software. Examples of such methods are the graphical interfaces of software-defined receivers G8JCFSDR (http://www.g8icf.dvndns.org/g8jcfsdr_drtl/downloads/QuickStartGuide.pdf), WiNRADIO G313 (http://www.winradio.com/home/g313e .htm), as well as the graphical interface of the evaluation (demo) board of the Si477x receiving microcircuit (Si477x Evaluation Board User's Guide. http://www.silabs.com/Support%20Documents/TechnicalDocs/Si477x-EVB.pdf). The disadvantage of this solution is the presence on the control panel of a large number of control buttons, indicators, switches, additional "windows". Their diversity makes it difficult to control the receiver. In the event of a new broadcast standard and the need to add new bands or operating modes of the receiver, you need to change the layout of the entire user interface panel, which turns any software update into a costly event. It is also difficult to use this control method for smartphones and tablet computers with a small screen area, where it is difficult to place a large number of graphic elements due to limitations on the accuracy of positioning of the touch point on the touch screen.

Known control methods using three-dimensional graphical interfaces. For example, in US patent No. 7562312 and US patent application No. 20070011617 provides options for grouping controls in the form of a rotating cylinder, parallelepiped, cube, prism. US Pat. No. 7,013,435 discloses an embodiment in the form of a rotating ball. The use of such methods for creating a graphical user interface allows you to concentrate a large number of control and display elements in a small spatial volume, which is especially important for smartphones and tablet computers.

Of the known solutions listed, the closest to the proposed method is a control method using a three-dimensional user graphic interface, according to which individual graphic widgets are made in the form of a rotating multifaceted prism (application for US patent No. 20070011617).

However, the known method makes it difficult to control the receiver due to unusual spatial combinations and at the same time changing all displayed forms. This complicates the perception of information, for example, the panoramic spectrum, tuning frequencies, the operational interpretation of which is more convenient in a spatially static format.

The closest technical solution to the claimed receiver is a direct conversion receiver with a three-phase architecture, described in US patent No. 5095536, containing a radio frequency amplifier, splitter, first, second and third balanced mixers, a frequency synthesizer with phase-shifting circuit, first, second and third low-pass filters (LPF), consisting of series-connected LC-filters, amplifiers and active filters, the outputs of which are connected to the inputs of the first, second and third multiplying digital-analogue, respectively converters (DAC), automatic controller (AR), clock, first, second and third analog-to-digital converters (ADC), microcontroller, and the output of the radio frequency amplifier is connected to the input of the splitter, the first, second and third outputs of which are connected respectively to the inputs of the first , the second and third balanced mixers, the outputs of which are connected respectively to the inputs of the first, second and third low-pass filters, the first, second and third inputs of the AR are connected respectively to the output of the first, second and third of its multiplying digital-to-analog converters (DACs), and the digital output is connected to the digital inputs of the first, second, and third multiplying DACs, the output of the clock generator is connected to the clock input of the AR, the DAC outputs are connected to the input of the microcontroller, from which the audio signal is taken.

A disadvantage of the known device is the lack of accuracy in maintaining the balance of phases and amplitudes of quadrature signals, as well as the difficulty in implementation. Thus, the amplitude balance is achieved by simultaneously averaging all three phases using a three-phase rectifier and maintaining their average level with the help of AR, regardless of the value of each of the amplitudes of the previous unbalance. The phase balance is established after the ADC using the calculation algorithms implemented in the microcontroller; this does not take into account the quantization errors that occur with comparable values of the sampling frequency and the upper frequency of the useful signal. Errors that occur during the formation of three-phase signals in a frequency synthesizer with a three-phase shift circuit are also not taken into account. In the known device, the phase-shifting circuit is proposed to be implemented using a frequency-dependent differential bridge formed by Chebyshev filters, with the help of which the phase values of heterodyne voltages of 0 °, 120 ° and 240 ° are obtained.

As noted in S. Bunimovich, L. Yaylenko. Amateur single-band communication technique. M: DOSAAF, 1970, p.126, multiphase systems (systems in which the number of channels is more than two) reduce the requirements for the accuracy of balancing the mixer signals and the identity of the channels, but the complexity of the device circuit becomes a payment for this, especially with an odd number of channels, t. to. Components produced by industry often contain only an even number of elements. This applies, for example, to operational amplifiers, ADCs, DACs, etc.

The technical result achieved using the inventive device is a significant increase in the degree of suppression of noise on the mirror channel while simplifying the device and using to control its settings an intuitive three-dimensional graphical user interface.

The specified technical result is achieved by the fact that the inventive receiver contains a radio frequency amplifier; splitter first and second balanced mixers; frequency synthesizer; the first and second low-pass filters, consisting of a series-connected LC-filter, amplifier and active filter, and the outputs of the low-pass filters are connected to the inputs of the first and second multiplying DACs, respectively; first automatic regulator; clock generator; first and second ADCs; microcontroller. The output of the RF amplifier is connected to the input of the splitter, the first and second outputs of the splitter are connected respectively to the first inputs of the first and second balanced mixers, the second inputs of the balanced mixers are connected respectively to the first and second outputs of the frequency synthesizer, and the outputs of the balanced mixers are connected respectively to the inputs of the first and second filters low frequencies. The first input of the first automatic controller is connected to the output of the first multiplying DAC, and the digital output of the automatic controller is connected to the digital input of the first multiplying DAC. The first output of the clock is connected to the second input of the first automatic controller. The outputs of the first and second ADCs are connected respectively to the first and second inputs of the microcontroller. The inventive device also contains a second and third automatic regulators, a two-phase voltage to three-phase voltage converter, an adder and a data bus register. In this case, the second output of the first automatic controller is connected to the reference voltage input of the second automatic controller, the first input of the second automatic controller is connected to the output of the second multiplying DAC, and the digital output of the second automatic controller is connected to the digital input of the second multiplying DAC. The outputs of the first and second multiplying DACs are connected respectively to the first and second inputs of the two-phase voltage to three-phase converter and the inputs of the first and second ADCs, respectively. The three-phase outputs of the two-phase to three-phase voltage converter are connected to the three corresponding inputs of the adder. The output of the adder is connected to the first input of the third automatic controller, the digital output of the third automatic controller is connected to the third input of the microcontroller, the first output of the microcontroller is configured to be connected via an exchange bus to an external control device, and the second output of the microcontroller via a data bus is connected to the input of the frequency synthesizer and to the input of the data bus register, multi-bit and single-bit digital outputs of the data bus register are connected to the digital inputs of the third automatic control torus. The first and second outputs of the clock are connected to the second inputs of the second and third automatic controllers, respectively.

As an external control device, any built-in, i.e. a non-mobile or mobile computer device containing software demodulators (SWD, Software Demodulators) and a graphical user interface (GUI) program.

Another object of the present invention is a method of direct signal conversion through the above receiver with a quadrature three-phase architecture. The inventive method of direct signal conversion includes the following stages:

- the formation of the initial phase code of the quadrature signals based on the code of the current receiver tuning frequency ω and its transmission to the data bus register and frequency synthesizer,

- generation by the synthesizer of quadrature harmonic signals with the receiver tuning frequency ω and initial phases 0 ° and 90 °,

- transmission of the generated quadrature signals to balanced mixers for their multiplication with the input radio frequency signal, pre-amplified radio frequency amplifier and split into two identical components in the splitter,

- transmission of the difference and total frequency components (ω-ωн) and (ω + ωн), where ωн is the carrier frequency of the input RF signal generated by multiplying the input RF signal with the quadrature signals of the synthesizer, to the inputs of the low-pass filters of the low-pass filters to suppress high-frequency components (ω + ωн),

- transmission of the obtained quadrature signals I = A ′ (t) · sin (ω-ωн) · t and Q = A (t) · cos [(ω-ωн) · t + Δφ], where A ′ (t) = k · A (T), k is the unbalance coefficient of quadrature signals in amplitude, Δφ is the error of unbalance in phase, A (t) is the modulating voltage of the useful signal, to the input of the node for adjusting the amplitudes of quadrature signals,

- multiplying the quadrature signal I in the multiplying DAC with the code coming from the counter of the automatic controller, with the formation of the resulting quadrature signal I ′,

- the supply of a quadrature signal I ′ to the input of the rectifier of the first automatic controller,

- the formation at the output of the rectifier voltage Um proportional to the average amplitude value of the quadrature signal I ′,

- comparing the voltage Um using a comparison circuit with a reference voltage Eop in the first automatic controller,

- the implementation of the stabilization of the amplitude level of the quadrature signal Q with respect to the amplitude level of the quadrature signal I at the output of the second automatic controller with a reference voltage Eop, determined by the value Um of the amplitude of the quadrature signal I,

- the supply of quadrature signals I ′ and Q ′ with normalized amplitudes to the input of the converter of two-phase voltage to three-phase,

- supplying the obtained three-phase voltage from the output of the two-phase voltage converter to three-phase voltage to the adder,

- transmission of quadrature signals I ′ and Q ′ to the ADC for digitization,

- transmitting digital quadrature signals I ′ and Q ′ to the microcontroller, and

- transmission of digital values of quadrature signals I ′ and Q ′ to the input of an external control device for demodulating quadrature signals I and Q and forming a panoramic spectrum and multimedia content of a graphical user interface.

The inventive method of direct signal conversion can significantly increase the degree of suppression of noise on the mirror channel in comparison with known analogues. Implementation of the proposed method in an appropriate receiver device, for example, of the type of the claimed direct conversion receiver with a quadrature three-phase architecture, allows to simplify the device itself and also use an intuitive three-dimensional graphical user interface to control it.

Another object of the present invention is a method for controlling the configuration of the aforementioned direct conversion receiver with a quadrature three-phase architecture, in particular comprising a radio frequency amplifier; splitter balanced mixers; frequency synthesizer; low pass filters; multiplying digital-to-analog converters; automatic regulators; a two-phase to three-phase voltage converter; clock generator; analog-to-digital converters; microcontroller.

The method for controlling the tuning of the direct conversion receiver with the quadrature-three-phase architecture is carried out by means of an external control device equipped with a graphical user interface containing a digital indicator to enable the display of the exact value of the tuning frequency and a window of the spectrum of the received signals to allow the spectrum of the received signals to be displayed, and includes a change in at least one parameter selected from: received broadcast standard by rotating the first three-dimensional drum graphic widget; a subband or channel of the received waves by rotating the second three-dimensional drum graphic widget.

In a preferred embodiment of the invention, the receiver tuning control method may further include changing at least one parameter selected from: a received frequency value by manipulating a coarse tuning scale and fine tuning scale; quick adjustment of the value of the received frequency by means of touch sensitive sensitive and coarse tuning indicators; fine tuning the receiver to the frequency of the received station by means of the button for setting the exact value of the received frequency

The inventive method for controlling the configuration of the above direct conversion receiver with a quadrature-three-phase architecture differs from the known ones in that it allows you to quickly, conveniently and visually control numerous settings for digital receivers even when using compact control devices, such as, for example, smartphone screens.

The invention is further described in detail with reference to the figures.

Figure 1 presents the structural diagram of the receiver with a quadrature-three-phase architecture.

Figure 2 presents a diagram of an automatic controller.

Figure 3 presents a diagram of a converter of quadrature signals into three-phase.

Figure 4 presents a vector diagram illustrating the operation of the phase Converter.

5 is a graphical user interface illustrating a method for managing receiver settings when using a tablet computer.

The quad-three-phase architecture receiver contains:

1 - radio frequency amplifier. Low-noise broadband amplifier, selected from the coverage of the desired frequency range. As such an amplifier can be used, for example, integrated operational amplifiers OPA 847, LMH 6629 company Texas Instruments;

2 - splitter. A component that splits an RF signal into two identical signals. It can be made in the form of an RF transformer, for example, type T1-1T from Mini-Circuits, or a symmetrical operational amplifier, for example, type THS 4520 from Texas Instruments;

3, 4 - balanced mixers. An analog heterodyne signal is multiplied with an input RF signal. Can be used integrated double balanced mixers type SA612 company NXP Semiconductors;

5 - frequency synthesizer. It generates a sinusoidal RF voltage with a frequency and phase determined by the control digital code. Direct Digital Synthesizer (DDS, Direct Digital Synthesizer) synthesizers can be used. There are models that immediately generate a quadrature signal, for example, AD9958 from Analog Devices;

6, 7 - low-pass filters. They are a four-terminal network, passing frequencies from 0 to a certain frequency Fcp, with monotonous suppression of all frequencies above Fcp. Passive low-pass filters can be used (Hanzel T.E. Filter calculation guide. Translated from English, Moscow: Sovetskoe Radio, 1974), active low-pass filters (Horowitz P., Hill W. Art of circuitry: in 3 volumes. Translated from English M.: Mir, 1993), Low-pass filter on switched capacitors (Makhlin A. Filters on switched capacitors. Components and technologies, No. 6, 2008);

8, 10 - multiplying DACs. The reference voltage is multiplied with a digital code. Often incorporate an output operational amplifier with a scaling gain. The popular domestic DAC K572PA1 can be used;

9, 11, 15 - automatic regulators. A circuit element containing a reversible counter 24, a comparison circuit (comparator) 25, a rectifier 26 (see Figure 2). Often used in automatic control systems, such as automatic gain control, servo ADCs, phase locked loop (PLL);

12 - clock generator. A device that generates clock pulses of constant frequency with parameters (amplitude, rise / fall rate) of digital logic. It can be implemented on NAND elements covered by positive feedback using an RC circuit, or by using a specialized integrated circuit, for example, an LM555 timer from Texas Instruments;

13 - converter of two-phase (quadrature) voltage into three-phase (see Figure 3). Built on the basis of a technical solution proposed in A.S. USSR No. 762131. It contains three operational amplifiers 34, 35 and 36 with connected weight resistors 27-33, the values of which are selected in a certain way, disclosed in the specified A.S. No. 762131. The procedure for calculating resistors is given below.

14 - adder. Performs arithmetic summation of three-phase signals with phases 0 °, 120 ° and 240 °. A summing operational amplifier can be used, given, for example, in Horowitz P., Hill W. The art of circuitry: in 3 volumes. Per. from English M .: Mir, 1993;

16 - data bus register. Carries out the reception and storage of the digital code sent from the microcontroller via the data bus for subsequent input into the reversible counter 24. Serves as a buffer device. It has its own unique address. For example, a 16-bit PCA9535 register for the I ² C data bus from NXP Semiconductors can be used;

17, 18 - analog-to-digital converters. Convert the analog variable signal into a digital code of a certain bit depth. A dual 24-bit ADC type UDA1361TS manufactured by NXP Semiconductors can be used;

19 - microcontroller. It transmits the digital values of the quadrature signals I and Q to an external control device, for example, a mobile computer device, controls data exchange via the exchange bus, generates control digital codes for controlling the frequency synthesizer by commands from an external control device, and controls data transfer via a data bus, for example I ² C or SPI. A general-purpose microcontroller can be used, for example, with an NXP Semiconductors series ARM Cortex-M3 core of the LPC1700 series, which has sufficient speed and a set of the required number of peripheral GPIO ports, exchange buses, for example USB (Universal Serial Bus), data buses, for example SPI and I ² C;

20 is an external control device, such as a stationary (built-in) or mobile computer device. It acts as a host device with respect to the microcontroller, transfers the power supply voltage to the receiver via the exchange bus, and with the help of a set of SWD software demodulators, processes digital quadrature I / Q signals: demodulation, channel decoding, audio / video decoding. A universal serial USB bus can act as an exchange bus. Using a graphical graphical user interface, the GUI manages the settings of the receiver and displays its current status: tuning frequency, subband, received broadcast standard. It also manages the display of the panoramic spectrum and multimedia content of digital broadcast formats. As an external control device, a smartphone, tablet computer, laptop, built-in device, such as a car multimedia center, and others can be used. 5, as an external control device, a tablet computer is shown as an example of a mobile computer device with a running control program presenting a graphical user interface with tactile input;

21 is a graphical user interface GUI and demodulation software SWD;

22 - node adjusting the amplitudes of the quadrature signals. Carries out the binding on the amplitude of the signal I to the adjustable reference voltage and the binding on the amplitude of the signal Q to the average value of the signal I;

23 - node adjustment phase quadrature signals I / Q. It determines the amount of phase mismatch, compares it with the set threshold value, corrects the digital value of the phase angle of 90 ° and sends this value through the microcontroller to the frequency synthesizer;

24 - reverse counter. Binary reversible counter with the ability to enter digital code in parallel. The state of this counter increases or decreases under the action of incoming clock pulses and the logical value of the reverse control voltage. Can be used, for example, a binary counter K564IE11;

25 - controlled inverter. Carries out the inversion of the input signal from the comparison circuit 26 under the action of a control signal. It can be implemented on logic elements 2I-NOT;

26 is a comparison diagram. Compares the reference voltage Eop with the voltage Um coming from the rectifier 27. In the event that Eop> Um, a logical “1” is formed at the output of the comparison circuit 26, and the counter operates in addition mode. Otherwise, i.e. if Um> Eop, a logical "0" is formed at the output of the comparison circuit 26, and the counter begins to decrease its value. Setting the value of Eop allows you to adjust the dynamic range of voltage variation Um. As a comparison circuit 26, an operational amplifier or a specialized comparator, for example K521CA3, can be used. The use of a two-threshold comparator with adjustable hysteresis, described, for example, in RF patent No. 2426222, gives good results;

27 - rectifier. Carries out the rectification of the input signal in order to determine its average amplitude value. As such a rectifier can be used precision rectifiers on operational amplifiers, described, for example, in Horowitz P., Hill W. The art of circuitry: in 3 volumes. Per. from English M .: Mir, 1993;

28-34 - resistors;

35-37 - operational amplifiers;

38 - a tablet computer as an external control device;

39 is a display field of a panoramic spectrum. Shows signal spectra in the area of the current receiver tuning frequency;

40 - the first three-dimensional rotating widget in the form of a drum with blades. Selects the broadcast standard: AM (amplitude modulation), FM (frequency modulation), DAB (Digital Audio Broadcasting), DRM (Digital Radio Mondiale), DVB-T (Digital Video Broadcasting Terrestrial);

41, 46 - buttons for setting the exact value of the received frequency;

42 is a scale for fine-tuning the received frequency with a touch-controlled pointer 45 for fine-tuning the scale;

43 - coarse tuning scale with a touch-controlled pointer 48 coarse scale settings;

44 - digital value of the tuning frequency;

45 - pointer settings accurate scale;

47 is a second three-dimensional rotating widget in the form of a drum with blades. Selects a subband or receive channel number;

48 is a rough scale setting indicator.

The work of the proposed receiver is as follows. When you turn on the external control device 20, such as a computer, and activate the graphical user interface program (Fig. 5), the supply voltage and the code of the current receiver tuning frequency ω are received via the exchange bus to the microcontroller 19 (Fig. 1). Based on the value of the tuning frequency code ω, the microcontroller 19 generates a code of the initial phase of the quadrature signals φ equal to 90 °, and sends it via the data bus to the data bus register 16 and to the frequency synthesizer 5. Using the data bus, the frequency synthesizer 5 receives from the microcontroller 19 also code of the current receiver tuning frequency ω. As a result, the frequency synthesizer 5 generates at its output quadrature harmonic signals with a frequency ω and initial phases of 0 ° and 90 °, respectively. These signals come from frequency synthesizer 5 to balanced mixers 3 and 4, where they are multiplied with an input radio frequency signal previously amplified by an RF amplifier 1 and split into two identical components in a splitter 2. Difference and total frequency components (ω-ωн) and ( ω + ωн), where ωн is the carrier frequency of the input RF signal, formed as a result of multiplying the input RF signal with the quadrature voltages of the frequency synthesizer 5, go to the inputs of the low-pass filter 6 and 7, where The pressure of high-frequency components (ω + ωn). Thus obtained quadrature signals I = A ′ (t) · sin (ω-ωн) · t and Q = A (t) · cos [(ω-ωн) · t + Δφ], where A ′ (t) = k · A (T), k is the unbalance coefficient of quadrature signals in amplitude, Δφ is the error of unbalance in phase, A (t) is the modulating voltage of the useful signal, fed to the input of the node for adjusting the amplitudes of quadrature signals 22. Signal I in the multiplying DAC 8 is multiplied with code N, coming from the counter 24 of the automatic controller 9. The resulting quadrature signal I 'is fed to the input of the rectifier 27 of the automatic controller 9. At the output of the rectifier 27 etsya voltage Um proportional to the average amplitude value of the quadrature signal I '. The voltage Um using the comparison circuit 26 is compared with the reference voltage Eop in the automatic controller 9 (Figure 2), and also serves as the reference voltage for the second automatic controller 11. As a result of the feedback formed by the circuit: the multiplying DAC 8 - rectifier 27 - circuit 26, the value of the digital code of the reverse counter 24 is stabilized near a certain value determined by the value of the reference voltage Eop. Similarly, the digital code is stabilized at the output of the second automatic controller 11, which, however, is determined not by the reference voltage Eop, but by the amplitude Um of signal I. Thus, the amplitude level of signal Q is stabilized with respect to the amplitude level of signal I, whose amplitude in turn, is determined by the value of the reference voltage Eop.

Quadrature signals I '/ Q' with normalized amplitudes are fed to the input of the converter 13 of the two-phase voltage to three-phase. As shown in FIG. 3, in the converter 13, the zero-phase signal “ a ” taken from the output of the operational amplifier 35 corresponds to the signal I ′. Buffer operational amplifier (op amp) 35 serves to align the amplitude-frequency and phase characteristics of channel “ a ” with channels “b” and “c”.

и вектора

(Фиг.4):Phase "b", taken from the output of OS 36, can be represented as the vector sum of the vector

and vectors

(Figure 4):

.

.

образуется из вектора

умножением на некоторый скалярный коэффициент k₁, а вектор

- умножением инверсного вектора

на некоторый скалярный коэффициент k₂:As follows from Figure 4, the vector

formed from vector

multiplying by some scalar coefficient k ₁ , and the vector

- by multiplying the inverse vector

by some scalar coefficient k ₂ :

Where

, т.к. длины векторов

и

одинаковы.

because vector lengths

and

are the same.

Similarly:

.

.

Then:

On the other hand, from figure 3 it follows that the output voltage of the phase "b" of the OS 36 is equal to:

Here R28 is a resistor 28; R29 - resistor 29, R32 - resistor 32; R33 - resistor 33.

Comparing expressions (1) and (2), we obtain the conditions for choosing the values of resistors 28, 29, 32, 33:

,

,

or

If R28 = R29 = R, then:

и инверсного вектора

(Фиг.4):Similarly, the phase "c", taken from the output of the op-amp 37, can be represented as the vector sum of the vector

and inverse vector

(Figure 4):

или

or

On the other hand, from figure 3 it follows that the output voltage of the phase "c" of the OS 37 is equal to:

Here R30 is the resistor 30; R31 is resistor 31, RS4 is resistor 34.

Comparing expressions (3) and (4), we obtain the conditions for choosing the values of resistors 30, 31, 34:

If R34 = R, then:

The obtained three-phase voltage (phases " a ", "b", "c") from the converter 13 of the two-phase voltage to the three-phase voltage is supplied to the adder 14, where they are added together. If the exact balance of amplitudes and phases is observed, the sum of the vectors of the three-phase voltage will be zero; otherwise, some error voltage will appear at the output of the adder 14. This error voltage is fed to the input of the rectifier 27 of the automatic controller 15 (Figure 2), where it is compared with the set reference voltage Eop≅0. Depending on the ratio of the voltages Um and Eop, a logical “1” or logical “0” is generated at the output of the comparison circuit, which is fed through a controlled inverter 25 to the input of the reverse control of the counter 24, in which the phase code corresponding to φ = 90 °.

The presence of an error voltage at the output of the adder 14 only indicates the presence of phase imbalance in the three-phase voltage (it is assumed that the amplitude imbalance is minimized in the amplitude correction unit 22), but does not unambiguously indicate the error sign Δφ: did it affect the increase or decrease of the phase shift φ = 90 °, i.e. the nature of the feedback can be either positive (undesirable) or negative. Let the feedback nature be negative, and the value of the phase shift code φ in the counter 24 under the action of clock pulses, for example, begin to decrease. The digital code of the corrected phase shift φ ′ from the output of the reverse counter 24 is fed to the input of the microcontroller 19, which after the verification procedure sends this code via the data bus to the phase register of the frequency synthesizer 5. The frequency synthesizer 5, having received a new value of the phase code φ ′, forms the output is a cosine voltage with a corrected phase value, which improves the phase balancing of both three-phase and quadrature signals, and reduces the error value at the output of the adder 14. Under the influence of negative feedback and phase φ 'at the output of the code-down counter 24, an automatic regulator 15 is stabilized near a certain value at which the error voltage value to the adder output goes to zero, which indicates reaching balancing as a three-phase and quadrature signals.

If the feedback is positive, a decrease in the value of the phase shift code φ in the counter 24 will, on the contrary, cause an increase in the error voltage at the output of the adder 14 with each cycle. To prevent this negative development of events, a procedure for checking the values of the phase shift code φ ′ in the microcontroller 19 to satisfy (90′-Δβ) <φ ′ <(90 ° + Δβ), where 2Δβ is the value of the phase “window”, in which the value of the phase shift code φ ′ should always be. The value of Δβ is set based on the maximum possible phase instability that can occur in quadrature channels. It can be assumed that always Δβ≤1 °. Then, in the case of positive feedback, when the value of the phase unbalance code φ ′ increases to values exceeding 90 ° + Δβ, or decrease lower than 90 ° -Δβ, the microcontroller 19 generates a counter reversal change command 24, which comes from a separate discharge of the bus register data 16 to the input of the controlled inverter 25 (Figure 2). As a result, the nature of the feedback becomes negative, a change in the value of the phase code φ ′ will lead to a decrease in the error voltage at the output of the adder 14 and stabilization of the phase code φ ′ near the value at which the best phase balance will be achieved. If there is a violation of a monotonous change in the phase code φ ′ and its abrupt change occurs, for example, due to a system failure, the microcontroller 19 forcibly corrects the phase code φ ′ to a nominal value of 90 ° and sends it to the data bus register 16 and frequency synthesizer 5 .

The parallel data entry mode in the counter 24 and the forced reverse control mode are used in automatic controller 15. In automatic controllers 9 and 11, these modes are not used.

Thus, in contrast to the well-known receiver adopted for the prototype, the proposed solution provides more accurate frequency-independent balancing of the quadrature signals, due to which there is a more significant suppression of interference on the side reception channels. The formation of three-phase voltages using a two-phase to three-phase voltage converter is carried out in a simpler and more accurate way than using an additional balanced mixer and a local oscillator, and makes it possible to exclude the third ADC.

Thus obtained quadrature signals I ′ / Q ′ are fed to the ADC 17, 18, where they are digitized, and then fed to the microcontroller 19. Then, via a data bus, for example USB, digital values of quadrature signals I ′ / Q ′ are fed to the input of an external device control 20, running software 21, for demodulating quadrature I / Q signals and generating a panoramic spectrum and multimedia content for a graphical user interface.

The software for demodulating quadrature I / Q signals consists of separate software modules available in the memory of an external control device, such as the mobile computer device shown in FIG. These can be modules for demodulating both analog broadcast standards, for example AM, FM, and digital: DAB, DRM, DVB-T. During the execution of these programs, an audiovisual content is formed in the external control device that is accessible for perception by the user. With the advent of new broadcasting standards, it is only necessary to add a new demodulation software module without changing the overall architecture of the receiving device.

To control the receiving device, as well as to display visual content, a graphical user interface is used - special software that provides visualization of the virtual control panel of the receiving device.

Figure 5 is an example of a graphical user interface for receiving signals of the digital broadcasting standard DRM. A tablet computer 38 is used as an external control device.

The received broadcast standard is selected by rotating the first three-dimensional drum graphic widget 40. In the case shown in FIG. 5, the DRM mode is set.

Using the second three-dimensional drum graphic widget 47, a subband or channel of received waves is set. In the case shown in FIG. 5, medium waves MW (Medium Wave) are set.

The frequency value is set by manipulating the settings of the coarse tuning scale 43 and fine-tuning scale 42. For quick tuning, touch sensitive sensitive indicators of fine 45 and coarse tuning 48 are used. The exact frequency value can be set using the buttons for setting the exact value of the received frequency 41 and 46. The exact value of the tuning frequency lights up with a digital indicator 44. In the case shown in FIG. 5, the receiver is tuned to a frequency of 1400 kHz. Field 39 displays the spectrum of the received signals.

The inventive method of managing the settings of the receiving device provides several advantages. Firstly, it allows you to maintain the familiar appearance of the radio panel with an intuitive arrangement of controls, while providing the ability to control a large number of receiver parameters on a relatively small surface of the screen of the control device. Secondly, with the advent of new broadcast standards and accepted wave ranges, it is enough to simply add new “blades” in three-dimensional drum widgets without significantly changing the overall layout of the graphical interface.

Claims (5)

1. Direct conversion receiver with a quadrature-three-phase architecture, including a radio frequency amplifier, splitter, first and second balanced mixers, a frequency synthesizer, first and second low-pass filters (LPFs), consisting of a series-connected LC filter, an amplifier and an active filter, the outputs of the low-pass filter are connected to the inputs of the first and second multiplying digital-to-analog converters (DAC), the first automatic controller, clock, the first and second analog-to-digital converters (ADCs), mic the controller, while the output of the RF amplifier is connected to the input of the splitter, the first and second outputs of the splitter are connected respectively to the first inputs of the first and second balanced mixers, the second inputs of the balanced mixers are connected respectively to the first and second outputs of the frequency synthesizer, and the outputs of the balanced mixers are connected respectively to the inputs the first and second low-pass filters, the first input of the first automatic regulator is connected to the output of the first multiplying DAC, and the digital output of the first automatic regulator and connected to the digital input of the first multiplying DAC, the first output of the clock generator is connected to the second input of the first automatic controller, the outputs of the first and second ADCs are connected respectively to the first and second inputs of the microcontroller, characterized in that it contains the second and third automatic controllers, a two-phase voltage converter three-phase, adder, data bus register, and the second output of the first automatic controller is connected to the voltage input of the second automatic controller , the first input of the second automatic controller is connected to the output of the second multiplying DAC, and the digital output of the second automatic controller is connected to the digital input of the second multiplying DAC, the outputs of the first and second multiplying DACs are connected respectively to the first and second inputs of the two-phase voltage to three-phase converter and the inputs of the first and the second ADC, the three-phase outputs of the two-phase voltage to three-phase converter are connected to the three corresponding inputs of the adder, the output of the adder is connected is connected to the first input of the third automatic controller, the digital output of the third automatic controller is connected to the third input of the microcontroller, the first output of the microcontroller is configured to be connected via an exchange bus to an external control device, and the second output of the microcontroller via a data bus is connected to the input of the frequency synthesizer and to the register input data buses, multi-bit and single-bit digital outputs of the data bus register are connected to the digital inputs of the third automatic controller, the first and second moves clock generator connected to the second inputs respectively of the second and third automatic regulators. 2. The direct conversion receiver according to claim 1, characterized in that the external control device is a mobile or integrated computer device with a touch screen and includes software demodulators (SWD) and a graphical user interface (GUI) program. 3. A method of direct signal conversion using a receiver with a quadrature-three-phase architecture, including
generating a code for the initial phase of the quadrature signals based on the code of the current receiver tuning frequency ω and its transmission to the data bus register and frequency synthesizer,
synthesizer generation of quadrature harmonic signals with the receiver tuning frequency ω and initial phases 0 ° and 90 °,
transmission of the generated quadrature signals to balanced mixers for their multiplication with the input radio frequency signal, pre-amplified radio frequency amplifier and split into two identical components in the splitter,
transfer of difference and total frequency components (ω-ωн) and (ω + ωн), where ωн is the carrier frequency of the input radio frequency signal, formed as a result of multiplying the input radio frequency signal with the quadrature voltage of the synthesizer, to the inputs of the low-pass filter of the low-pass filter to suppress high-frequency components ( ω + ωн),
transmission of the obtained quadrature signals I = A ′ (t) · sin (ω-ωн) · t and Q = A (t) · cos [(ω-ωн) · t + Δφ], where A ′ (t) = k · A (t), k is the unbalance coefficient of the quadrature signals in amplitude, Δφ is the error of the unbalance in phase, A (t) is the modulating voltage of the useful signal to the input of the node for adjusting the amplitudes of the quadrature signals, multiplying the quadrature signal I in the multiplying DAC with the code received from the counter of the automatic controller, with the formation of the resulting quadrature signal I ′,
applying a quadrature signal I ′ to the input of the rectifier of the first automatic controller,
the formation at the output of the rectifier voltage Um proportional to the average amplitude value of the quadrature signal I ′,
comparing the voltage Um using a comparison circuit with a reference voltage Eop in the first automatic controller,
the implementation of the stabilization of the amplitude level of the quadrature signal Q with respect to the amplitude level of the quadrature signal I at the output of the second automatic controller with a reference voltage Eop, determined by the value Um of the amplitude of the quadrature signal I,
the supply of quadrature signals I ′ and Q ′ with normalized amplitudes to the input of the converter of two-phase voltage to three-phase,
supplying the obtained three-phase voltage from the output of the two-phase voltage converter to the three-phase voltage to the adder,
transmission of quadrature signals I ′ and Q ′ to the ADC for digitization,
transmitting the digital quadrature signals I ′ and Q ′ to the microcontroller, and
transmitting digital values of quadrature signals I ′ and Q ′ to the input of an external control device for demodulating quadrature signals I and Q and displaying a panoramic spectrum and multimedia content using the graphical user interface. 4. A method for controlling the tuning of a direct conversion receiver with a quadrature-three-phase architecture according to claim 1 or 2 by means of an external control device containing software demodulators (SWD) and a graphical user interface (GUI), including a digital indicator to display the exact value of the tuning frequency and a spectrum window received signals, characterized in that it includes changing at least one parameter selected from: the received broadcast standard by rotating the first three-dimensional drum a graphic widget, and
a subband or channel of the received waves by rotating the second three-dimensional drum graphic widget. 5. The method of controlling the configuration of the receiver according to claim 4, characterized in that it further includes changing at least one parameter selected from:
values of the received frequency by manipulating the coarse tuning scale and fine tuning scale,
quickly adjusting the value of the received frequency by means of touch sensitive sensitive and coarse tuning indicators, and
fine tuning the receiver to the frequency of the received station by means of the button for setting the exact value of the received frequency.

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