RU2541894C1 - Trigger for complementary microcircuit of metal-oxide-semiconductor structure - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: trigger consists of pairs of interconnected NMOS and PMOS transistors with power supply bus, control and output lines; the transistors are jointed in two blocks, each of them containing two groups of two NMOS and two PMOS transistors, at that two blocks of transistors are placed at integrated circuit crystal at distance from each other, which is equal to threshold value or bigger than this value in order to exclude simultaneous impact of single nuclear particle on both blocks of transistors at the level more than the threshold value.

EFFECT: improving stability to impact of single nuclear particles without excess increase in square area occupied by the trigger at crystal included into composition of integral CMOS microcircuit.

1 tbl, 2 dwg

Description

The invention relates to logic elements of microcircuits with nanoscale design standards for highly reliable computer technology and can be used in control elements of microprocessor microcircuits and reading elements of memory devices.

The closest in technical essence and the achieved result is a trigger of a complementary metal-oxide-semiconductor structure of the microcircuit, consisting of pairs of NMOP and RMOS transistors interconnected with the power supply bus, control lines and output lines and placed on the integrated circuit chip (see. Wang W., Gong N. Edge triggered pulse latch design with delayed latching edge for radiation hardened application // IEEE Trans. Nucl. Science. 2004. V.51. No. 6. P.3616-3630).

The disadvantage of this trigger is the lack of noise immunity and reduced radiation resistance of the trigger transistors to the effects of single nuclear particles.

The technical result expected from the use of the invention is to increase the failure resistance to the effects of single nuclear particles without an excessive increase in the area occupied by the trigger on the chip.

The specified technical result is achieved by the fact that in the trigger of the complementary metal-oxide-semiconductor structure of the microcircuit, consisting of pairs of NMOS and RMOS transistors connected together, with a power supply bus, control lines and output lines and placed on an integrated circuit chip, according to the invention, transistors combined into two blocks, each of which contains two groups of two NMOS transistors and two RMOS transistors, the drains of the RMOS transistors in each group are connected to the gate of the first NMOS transistor the transistor in the group, the drain of which is connected to the gate of the first of the two RMOS transistors, and the source with the drain of the second NMOS transistor in this group, the drain of the first RMOS transistor of the first group of the block is connected to the drain of the first NMOS transistor of the second group of this block, and two blocks of transistors are placed on integrated circuit chip from one another at a distance equal to or greater than the threshold distance, to exclude the simultaneous impact of a single nuclear particle on both blocks of transistors with a level greater than the threshold.

The indicated set of features makes it possible to reduce the probability of a failure of a trigger state when exposed to a single nuclear particle while reducing the area occupied by the trigger on the chip.

The invention is illustrated by drawings, where in Fig.1 shows an electrical schematic diagram of a trigger, Fig.2 shows a diagram of the relative position of the transistors in the blocks of the trigger and the blocks relative to each other.

The trigger contains two blocks I, II of transistors, the first block I has five pins 1, 2, 3, 4, 5, the second block II has five pins 6, 7, 8, 9, 10. The first block I contains four NMOS transistors 11, 12, 13, 14 and four RMOS transistors 15, 16, 17, 18, the second block II includes four NMOS transistors 19, 20, 21, 22 and four RMOS transistors 23, 24, 25, 26. Conclusions 3 and 8 blocks I and II are two direct outputs of the trigger, terminal 27, combining the terminals 4 and 10 of blocks I and II, and terminal 28, combining the terminals 5 and 9 of blocks I and II, are two inverse outputs of the trigger, terminals 1, 2, 6 , 7 are the trigger control inputs.

Transistors 11, 12, 15, 16 form the first group of transistors of the first block I, transistors 13, 14, 17, 18 form the second group of transistors of the first block I, transistors 19, 20, 23, 24 form the first group of the second block II, transistors 21, 22, 25, 26 form the second group of the second block II.

The distance between the two blocks of transistors must be equal to or greater than the threshold and is determined from the expression:

L _1,2 ≥L _POR = {(πQ _TP2 S _SB2 D _{n, p} / (8Δl _TP )) (R _OUT . _OPEN · λ _N λ _OUT / U _PER )} ^1/3 × tgθ,

where Q _TP2 is the charge formed on the segment of the track Δl _TP closest to the second block II of transistors;

S _SB2 = Δl _SB2 × w _SB2 - charge collection area in the second block II of transistors;

Δl _SB2 - the size of the charge collection area in one direction with the direction of the track, and

w _SB2 - in the transverse direction;

D _{n, p} is the coefficient of ambipolar diffusion of charge carriers;

Δl _TP - the length of the segment of the track, from the region of which nonequilibrium carriers diffuse into the second block II of transistors;

R _OUT.OKR - output resistance (average value) of an open MOS transistor connected by its own drain to the drain of a transistor collecting charge in the second block II of transistors;

U _PER - switching voltage of the transistor of the second block II of the trigger;

θ is the angle of inclination of the particle track relative to the normal to the crystal surface; λ _N = (τ _N / τ _SP ) ^a , a = τ _N / (τ _SP- τ _N ).

The constants of the rise time τ _Н and decay τ of the _SP of the photocurrent pulse formed by charge diffusion from the particle track depend on the diffusion time constant of nonequilibrium carriers τ _D from the track region to the charge-collecting region of the second block II of the cell transistors and their relation is known (see Fulkerson DE A physics-based engineering methodology for calculating soft error rates of bulk CMOS and SiGe heterojunction bipolar transistor integrated circuits // IEEE Trans. Nucl. Science. 2010. Vol.57. No. 1. pp.348):

τ _SP = τ _D = 4r ² / (π ² D _{n, p} ) and τ _N = τ _SP / 9,

where D _{n, p} is the coefficient of ambipolar diffusion of charge carriers.

The coefficient λ is defined as λ _{OUTPUT OUTPUT} = (τ _OUT / τ _SP) ^{a, a} = τ _OUT / (τ _{SP OUTPUT} -τ) where _OUT τ = R × C _{VYH.OTKR.2 NODE} - the time constant of the trigger assembly of overcharging; C _NODE - node capacity, charge Q _PER on which forms an impulse of interference with the amplitude switching the trigger.

The charge Q _TP2 follows from the expression:

Q _TP2 = q × LET × ρ _Si × Δl _TP / E _{p, n} ,

where LET - linear particle energy loss;

q is the electron charge;

Δl _TP - the length of the segment of the track, from the region of which nonequilibrium carriers diffuse;

ρ _Si is the density of silicon;

E _{p, n} is the energy of formation of one electron-hole pair.

The described device can operate in one of two modes: storage and recording of data.

In the storage mode, at the outputs 3, 8, 27, 28 of the trigger, the logical signal levels “0” and “1” set during recording are saved, with duplication of one logical data level at pins 3 and 8, and the other at pins 27, 28. The trigger is in the mode storage can be in two stable states: in one state at two outputs 3 and 8 the signal levels are “0”, and on the other two outputs 27, 28 - levels are “1”. In another stable state of the trigger, the logic levels of the signals at these outputs change.

In recording mode, under the influence of control signals at pins 1, 2, 6, 7, the trigger is set to one of two stable states. It is possible to change the trigger state during recording only by supplying two control signals with logic levels “0” to terminals 2 and 7 in the mode when logic signals with levels “0” are located at outputs 3 and 8, and logic signals are located at outputs 27, 28 with levels “1”. In this case, the control signals at pins 2 and 7 switch the trigger state, closing the positive feedback circuit in the trigger. It is similar to change the trigger state when logic signals with levels “1” are located at outputs 3 and 8, and logic signals with levels “0” are located at outputs 27, 28, only by supplying two control signals with logic “0” levels to the outputs 1 and 6.

The reduction in the area occupied by the trigger on the chip is ensured by the close arrangement of all transistors in the blocks and the reduction of the links between the blocks to two buses.

When a single nuclear particle is affected by a trigger, when the particle track is directed from a locked transistor of one block I to a locked transistor of another block II, nonequilibrium charge carriers form along the particle’s track, which diffuse to the transistors, where the locked transistors are output as photocurrents through the stock electrodes and recharge the capacitance of these nodes, causing interference voltage pulses that can cause the trigger to fail if the switching threshold is exceeded.

Critical to assessing the durability of a trigger is a failed state in storage mode. The failure of the logical state of the trigger can occur when the particle simultaneously affects two MOSFETs of the trigger transistors that are in the locked state, excluding the effects on the following pairs of transistors 11 and 15, 13 and 17, 19 and 23, 21 and 25 in their locked state, in which opening feedback in the trigger, which preserves the initial logical state of the trigger.

The failure of the initial state of the trigger is possible only when a single particle is exposed to a pair of locked transistors, one of which belongs to block I of transistors, and the second to block II of transistors. In one of the two logical states of the trigger (see figure 1 and figure 2) these are pairs of transistors - 11 and 19, 11 and 23, 15 and 19, 15 and 23, and for the other logical state of the trigger the following pairs: 17 and 25 , 17 and 21, 13 and 25, 13 and 21.

An example implementation of the invention

The invention can be implemented in clocked one- and two-stage triggers used in the control unit of the CMOS register file of a microprocessor system with a design norm of 65 nm. A sketch of the design of the trigger is shown in figure 2.

In one logical state of the trigger in FIG. 2, transistors 11, 15 of block I and transistors 19, 23 of block II are locked, located in the upper halves of blocks I and II in FIG. 2. In another logical state, transistors 13, 17 of block 1 and transistors 21 are locked 25 of block II of the trigger located in the lower halves of blocks I and II of FIG. 2. FIG. 2 shows the distances between two groups of locked transistors for one logical state of the trigger L _1,2 and for the other L ′ _1,2 . These distances for the given arrangement of transistors are the same L _1,2 = L ′ _1,2 and determine the fault tolerance of the trigger in its two logical states.

To achieve a technical result - to increase the fault tolerance of the trigger when exposed to single nuclear particles, the blocks I and II of the trigger transistors (see figure 2) are spaced at a distance of L _1.2 = 2.5 μm.

The stability of the trigger when exposed to single nuclear particles is due to the proposed separation of the trigger transistors into two blocks and their separation on the chip chip at a distance equal to or greater than the threshold distance, excluding the simultaneous exposure of a single nuclear particle to both blocks of transistors I and II with a level higher than the threshold.

A trigger condition can fail when a particle simultaneously impacts two reverse biased transistors from different trigger units I and II, for example, transistors 11 and 23, it is possible when charges on each of these transistors exceed a threshold value for each transistor Q _POR , resulting in an amplitude the interference pulse at the corresponding node exceeds the switching threshold, for example, U _PER = 0.25-0.5 V for triggers according to the CMOS design norm of 65 nm and U _PER = 0.1-0.15 V for triggers according to the design CMOS norm of 28 nm. If, by a locked transistor of block II, a charge Q _SB less than the switching threshold charge Q _SB <Q _POR is output to the node capacitance from the photocurrent pulse, then regardless of the value of the charge collected by the other locked transistor in block I, the trigger does not fail, because the interference pulse in the block II has an amplitude less than the switching threshold voltage. Critical when assessing the failure stability of a trigger are the effects of a particle when its track passes in the direction from one block I to another block II (see Fig. 2) and at a small angle to the surface of the semiconductor chip chip, which corresponds to the angle of inclination of the particle track relative to the normal to the surface θ≥60 ° crystal, and the particle track passes through the region of the reverse biased pn junction of the drain-substrate of the locked transistor in block I, for example, transistor 11 (see Fig. 2), directly acting on this transistor, and on the second pair of transistors are trapped, which relates to the block II and simultaneously exposed to particles, such as transistor 23, operates the charge of minority carriers which diffuse to it from the nearest thereto particle track area. To exclude a trigger failure, the distance L _1,2 = L ′ _1,2 between pairs of sensitive MOS transistors from two blocks I and II should be equal to or greater than the threshold value L _POR .

Table 1 shows the results of modeling the threshold distances L _POR depending on the parameters of the acting particle for the trigger according to the CMOS design norm of 65 nm, which provide resistance to the effects of single nuclear particles with linear losses of 40 and 60 MeV · cm ² / mg for angles of incidence of a single particle θ = 60 ° and 75 ° depending on the parameters of the transistors: I _{C. NAS} = 67-107 μA, R _OUT . OPEN = 4.1-7.3 kΩ at C _NODE = 4 fF.

Table 1 Threshold distance L _POR between locked transistors of two blocks of trigger transistors I and II Example No. one 2 3 four 5 6 θ, degree 60 60 60 60 75 75 LET, MeV · cm ² / mg 40 60 40 60 40 40 Δl _TP , μm 0.6 0.6 0.6 0.6 0.6 0.6 D _{n, p} , cm ² / s 10 10 10 10 10 10 S _SB2 , μm ² 0.2 0.2 0.2 0.2 0.2 0.2 I _{C. NASA} , μA 107 ∗ 107 ∗ 67 ∗∗ 67 ∗∗ 107 ∗ 67 ∗∗ R _{OUT OPEN} , kOhm 4.1 4.1 7.3 7.3 4.1 7.3 U _PER , FC 0.3 0.3 0.3 0.3 0.3 0.3 U _POR , μm 1.19 1.38 1.37 1.57 2.56 2.97 Note: ∗ parameters of one logical state of the trigger; ∗∗ the parameters of the second logical state of the trigger

Modeling showed that the described trigger according to the CMOS design norm of 65 nm ensures trouble-free operation when exposed to single particles with track tilt angles of 60 ° and linear energy losses of LET = 60 MeV × cm ² / mg with a distance between blocks of L _1.2 ≥L _POR = 1.57 μm and with angles of 75 ° with linear energy losses LET = 40 MeV × cm ² / mg while ensuring the distance between the blocks L _1.2 ≥L _POR = 2.97 μm.

Claims (1)

The trigger of a complementary metal-oxide-semiconductor structure of the microcircuit, consisting of pairs of NMOS and RMOS transistors interconnected with a power supply bus, control lines and output lines and placed on an integrated circuit chip, characterized in that the transistors are combined in two blocks, each of which contains two groups of two NMOS transistors and two RMOS transistors, the drains of the RMOS transistors in each group are connected to the gate of the first NMOS transistor in the group, the drain of which is connected to the gate of the first RMOS transistor, and the source with the drain of the second NMOS transistor in this group, the drain of the first RMOS transistor of the first group of the block is connected to the drain of the first NMOS transistor of the second group of this block, and two blocks of transistors are placed on the chip of the integrated circuit one from another at a distance equal or greater than the threshold distance, to exclude the simultaneous impact of a single nuclear particle on both transistor blocks with a level greater than the threshold.

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