RU2530285C1 - Active hardware stack of the processor - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: hardware stack of the processor with the stack pointer and stack control logic comprises a program counter with tri-state output cascades, which includes additionally at least N of program counters with tri-state output cascades, at that inputs for parallel loading of all program counters are interconnected bit-by-bit, outputs of all program counters are interconnected bit-by-bit, increment inputs of all program counters are interconnected so that at each certain moment of time only one program counter selected by the stack pointer is in active state and may perform its functions independently from other counters.

EFFECT: increasing operational speed of the processor, its efficiency, simplifying its design due to manufacturing of a program counter unit operating as per the stack principle and allowing operations of subroutine jump or interrupt service procedure.

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Description

The invention relates to the field of electronics and microprocessor technology and can be used in the construction of modern, high-performance RISC microprocessors and microcontrollers to improve performance and simplify their design.

In the general case, a stack (from the English stack - stack) is a data structure that is a list of elements organized according to the LIFO principle (Last In - First Out, “last come, first go”).

In the framework of the proposed technical solution, the term stack is used in relation to the processor’s memory area organized according to the “store” principle (similar to a store in firearms - firing will start from the cartridge loaded into the store last) and ensure that return addresses are saved when calling subroutines and serving interrupts for the subsequent transfer of control to the call point of the subprogram or to the address before which the transition to the interrupt service procedure was performed.

We also note that the architecture of RISC (Reduced Instruction Set Computer - a computer with a reduced set of instructions) is the basis of modern high-performance microprocessors and microcontrollers.

The main requirements of the RISC architecture are:

1. Any operation should be performed in one step.

2. The command system must contain a minimum number of the most frequently used commands of the same length.

3. Data processing operations are implemented only in the register-register format. The exchange between registers and memory is performed only by load-write commands.

In the future, these requirements were somewhat relaxed, and at present, only the requirement remains unshakable: data processing is carried out only by commands in the register-register format. And the requirement to perform any operation in a single cycle began to be interpreted as the execution of any operation for the same time interval - a machine cycle, or as loading a command pipeline at a pace of "command per cycle".

But, nevertheless, compliance with this requirement makes it possible to simplify the logic of decoding instructions by using fixed-length and fixed-format instructions, the ability to execute which for a fixed time interval allows using fairly simple circuitry solutions to realize not only high speed of performing elementary operations while maintaining the simplicity of the control device and processor synchronization, but also organize both pipelining and spatial parallelism computation nings.

It should also be noted that today the best features of RISC architecture are widely borrowed in the development of modern high-performance microprocessors and microcontrollers, in connection with which the technical task of the claimed technical solution is to create a specific design of the processor hardware stack that allows performing complex machine operations in one clock cycle.

Such complex operations include subprogram calls and interrupt service, because when they are executed, they involve switching to the specified address, that is, writing the value of the transition address to the processor program counter (PC) register of the processor, while simultaneously saving the return address from the subprogram, that is, with saving the current PC value, which is quite difficult to implement for the same time interval with all other commands.

Consider how this operation is implemented in the design of the characteristic representatives of the families of microprocessors and microcontrollers.

Known microcontroller family TMS 1000 (pat. US 3988604, pat. US 4024386). A simplified block diagram of this microcontroller is presented in its technical description (TMS 1000 Series Data Manual, The Engineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Group).

In microcontrollers of this family, the effective address when accessing the read-only memory (ROM) of the program (ROM) is formed by feeding the current contents of the program counter (PROGRAM COUNTER) and the contents of the page address register (PAGE ADDRESS REGISTER) to its address inputs. This separation is due to the limited hardware resources of the microcontroller.

When the subroutine call operation (CALL) is performed, the current state of the program counter is stored in the subroutine return register (SUBROUTINE RETURN REGISTER), and the contents of the page address register are written to the page buffer register (PAGE BUFFER REGISTER). After that, the effective address of the transition to the called subprogram from the program ROM is recorded in the program counter and page address register, and operations continue from the address contained in the program counter and page address register.

When performing a return operation from a subroutine (RETN) to the address from where this subroutine was called, the contents of the page buffer register are written to the page address register, and the program counter is loaded with the value of the return register from the subroutine. After that, operations continue from the effective address contained in the program counter and page address register, that is, from the address from where the subroutine was called.

This solution is the simplest peer-to-peer stack that provides the ability to save only one return address from a subroutine or interrupt service routine.

The disadvantage of this solution is the small depth of nesting of subprogram calls, since the page buffer register and the return register from the subprogram can save only one effective return address from the subprogram, as well as the inability to execute the subprogram call operation in one clock cycle, since writing the address of the transition to the subprogram in the program counter does not can be performed while maintaining its current value.

Known processor family of computers PDP (Programmed Data Processor) of the American corporation Digital Equipment Corporation (DEC). An elegant, albeit somewhat unusual, solution was found in the PDP-8 design: the return address from the subprogram was stored in the subprogram itself at the address of its call, and the execution of the subprogram began with the following address.

When performing a PDP-8 operation of calling a subprogram at address Y (JMS Y), the current state of the processor’s software counter is stored at this address — Y, and the value Y + 1 is entered in the program counter, after which the execution of subprogram operations continues from address Y + 1 contained in the program counter before the subroutine return instruction (JMPIY). Performing this operation involves loading the PC with a value from the memory location with address Y, and, consequently, returning control to the place of the subprogram call (PROGRAMMED DATA PROCESSOR-8 USERS HANDBOOK. DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS, p.23).

According to the PDP-8 flowchart in the technical description (PDP-8 A HIGH SPEED DIGITAL COMPUTER. DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS, p.8), during the operation of calling the subprogram at address Y in the memory address register (MEMORY ADDRESS REGISTER) records the transition address Y from the memory buffer register (MEMORY BUFFER REGISTER) according to the signals of the basic state generator (MAJOR STATE GENERATOR) controlled by the instruction code JMS Y from the instruction register (INSTRUCTION REGISTER).

After that, the contents of the program counter (PROGRAM COUNTER) through the buffer memory register (MEMORY BUFFER REGISTER) is recorded in RAM (4096-WORD CORE MEMORY) at address Y in the memory address register, and the contents of the memory address register containing the value of jump address Y are overwritten into the software counter and incremented. Thus, the execution of subroutine operations begins with the address Y + 1 contained in the program counter.

The role of the subroutine return instruction in PDP-8 is played by the jump instruction based on the value contained in the memory cell. At the same time, in the JMPIY command, the transition is pre-programmed according to the value contained in the first cell of the subprogram. As a result of executing the JMPIY instruction, the contents of the RAM cell at address Y are entered into the program counter via the memory buffer register, which actually transfers control of the program to the return address.

Such a hardware implementation of the mechanism for returning from subroutines and interrupt service routines essentially provides its own separate peer-to-peer stack in memory for each subprogram call or interrupt service routine.

The disadvantage of this solution, despite the fact that it significantly increases the nesting depth of subprogram calls, is the inability to execute the subprogram call operation in one clock cycle, since writing the address of the transition to the subprogram in the program counter here also cannot be performed simultaneously with saving its current value in the operational memory. In addition, the operations of accessing RAM are much slower than the operations of writing and reading registers of the processor itself, and a similar principle of saving the return address from the subroutine does not allow recursive calls of the subroutine from itself or the interrupt service routine, since the new return address in this case will be entered in storage cell, but the previous return address stored in it will certainly be lost. In addition, this mechanism for storing the return address is not operational if subroutines are placed in the memory of a read-only memory device, recording into which is physically impossible.

The closest in technical essence to the claimed invention, adopted as a prototype, is a Microchip PIC18 series microcontroller, which contains a 31-level (in general case, N-level) hardware stack (31-Level Stack), presented in the form of a block diagram in Proprietary Datasheet (Microchip PIC18 (L) F1XK22 Data Sheet, 20-Pin Flash Microcontrollers with nanoWatt XLP Technology. © 2009-2011 Microchip Technology Incorporated. DS41365E - page 10).

In the specific hardware version of the Microchip PIC18 (L) F1XK22 microcontroller, the Return Address Stack is a separate additional memory area containing 31 registers (31-Level Stack) and organized by store type, with the register (stack cell) in which is being written, or from which reading is being made, is determined by a special stack pointer (Stack Pointer - STKPTR) with stack control logic.

The stack area of the PIC18 (L) F1XK224 microcontroller belongs neither to the software area nor to the data area. The current value of the program counter (Program Counter - PC) is sent to the stack when a subroutine call command (CALL) is executed or interrupt processing is performed, while the stack pointer is incremented by one and points to the stack cell into which the contents of the PC are pushed. In the program counter, the starting address of the interrupt processing routine or subroutine that is being executed is entered. During the return procedure from the subprogram (RETLW, RETFIE, or RETURN commands), the contents of the current stack cell are loaded into the program counter, and the stack pointer is reduced by one.

The thirty-level hardware stack of the Microchip PIC18 (L) F1XK224 microcontroller provides a sub-routine call attachment depth of up to 31, followed by a correct return. When the limited hardware stack overflows, the stack pointer again points to the original cell, and the microcontroller starts writing to the stack “in a ring”, erasing the previous contents of the stack. When retrieving, a similar process can be observed: the contents of the "bottom" of the stack are read, and the pointer jumps to the very top.

As a pointer to the hardware stack, a binary counter of the corresponding bit capacity is usually used with the installation input in the initial state by a reset signal, capable of performing increment and decrement operations. The stack control logic is usually implemented by means of a code-position decoder that activates one of the stack registers according to the number (code) in the stack pointer. To connect only one of the stack registers to the program counter, registers with a tristable output stage that can disconnect from the bus are used, or the output code of one of the registers is selected using a switch (multiplexer).

The disadvantage of the design chosen as a prototype, despite the fact that it provides an acceptable depth of nesting of subprogram calls, is the impossibility of performing a subprogram call operation in one clock cycle, since recording the address of the transition to the subprogram in the program counter here also cannot be performed while saving it current value in stack registers.

The objective of the proposed technical solution is to create a design of the software counter assembly working on the stack principle (or on the store principle), but allowing, unlike the prototype, to perform operations of switching to a subroutine or to an interrupt service procedure, as well as returning from them in one clock cycle, compliance with the circuit simplicity of the processor.

The technical result consists in increasing the speed of the processor, and, as a consequence, performance, while simplifying its design.

This technical result is achieved in that the processor hardware stack with a stack pointer and stack control logic, including a software counter with tristable output stages, according to the solution additionally contains at least N program counters with tristable output stages, while the parallel load inputs of all program counters are connected bitwise together, the outputs of all software counters are connected bitwise together, the increment inputs of all software counters are connected together, input Allows the parallel loading of all program counters to be connected together, the sampling inputs of each of the individual program counters are connected to the control outputs of the stack control logic of the same name, so that at any given moment only one of the program counters selected by the stack pointer can be in an active state and execute their functions independently of the rest.

In the design of the processor (microprocessor, microcontroller) containing the software counter and the characteristic nodes of the hardware stack implementation, such as the stack pointer with the stack control logic and stack registers, according to the technical solution, in general, N identical program counters are actually introduced, which actually replace the registers in the design the stack, which are excluded from the design, and the stack pointer with the stack control logic is connected to the N + 1 block of software counters for fetching the currently active software counter

The outputs of the program counters with tristable output stages are connected bitwise together, so that at each separate moment of time the outputs are active only from one of the counters selected by the stack pointer through the stack control logic. The inputs for parallel loading of program counters are also connected bitwise together, which allows parallel loading of only one of the counters selected by the stack pointer using the stack control logic at the same time. The counting inputs of software counters are also combined, which allows you to apply increment pulses to all counters, but only that counter that is currently selected by the stack pointer through the stack control logic is incremented. As a result, during the transition to the subroutine or to the interrupt service procedure, the currently active program counter will contain the return address from the subprogram, which will not be saved anywhere, since the starting address of the subprogram or interrupt service procedure will be written to the next program counter activated by logic stack control as a result of incrementing the stack pointer. The current operation codes of the subprogram are selected from the memory by the active program counter, while inactive - it contains and stores the return address from the subprogram. To return from a subroutine or an interrupt service routine, it is sufficient to decrement the stack pointer, which, by means of the stack control logic, will switch the program counter, which stores the return address from the subroutine, to the active state, and the current counter will become inactive.

If, in the process of executing the subprogram, another subprogram is called, the current active counter will store the return address from it, and the starting address of the nested subprogram will be written to the next program counter, which will be activated by the stack control logic as a result of the increment of the stack pointer.

The depth of nesting of subprograms is determined by the number of available software counters, and situations with overflow are handled similarly to situations with overflow of the prototype stack.

Thus, the stage of saving the contents of the program counter in the stack register is excluded from the algorithm for performing the operation of moving to the subroutine or to the procedure for servicing the interrupt, while the return algorithm from these procedures is completely simplified to the operation of decrementing the stack pointer, since there is no need to write to the program counter from the stack return address. And the increment of the stack pointer and the entry of the starting address of the subprogram into the next program counter, activated by the stack control logic, as well as the decrement of the stack pointer in the return procedure can be performed in one clock cycle, which allows to increase the processor speed by 30-50% when implemented operations of calling subprograms or servicing an interrupt, as well as returning from them, due to a decrease in the number of clock cycles required to perform such operations. The result also simplifies the design of the control unit and decryption of the instruction code, since the claimed technical solution involves the execution of all operation codes in a fixed time in one machine cycle.

There is a functional analogy between the principle of operation of the proposed solution and the principle of operation of a typical processor hardware stack (microprocessor, microcontroller), as well as its design. But program counters organized by the store principle in the proposed solution not only perform a passive function of storing the return address from the subprogram, but also play the role of the active current instruction pointer in memory. This allows us to name the claimed technical solution - the active hardware stack of the processor.

The claimed technical solution differs from the prototype in the presence of new blocks - N identical software counters, their relationships with other elements of the circuit. These differences allow us to conclude that the proposed solution meets the criterion of "novelty."

The desired result is achieved by the entire newly introduced set of essential features that are not found in the well-known patent and scientific literature at the filing date. Therefore, the technical solution meets the criterion of "inventive step".

The claimed solution is illustrated by drawings, where Fig. 1 shows a block diagram of the proposed device, and Fig. 2 is a waveform diagram illustrating the principle of operation of the device tactically.

In the drawing, the following notation:

- IDCU - Instruction Decode and Control Unit - a control and synchronization device, usually performed in hardware based on a programmable logic matrix (PLM);

- SP - Stack Pointer - a stack pointer, a hardware counter representing a binary counter (CT) with the installation input in the initial state (R) by a reset signal, capable of performing increment (+1) and decrement (-1) operations, with stack control logic, hardware representing a positional type decoder (DC);

- PC FILE - Program Counter File - a store-organized file of N + 1 software counters (PC 0, PC 1, ... PC N + 1); hardware representing binary counters (CT) with parallel loading by the control signal for enabling parallel recording (PE), having and capable of performing increment operations (+1), and the counter PC 0 also has a setup input to the initial state (R) by a reset signal;

- IR - Instruction Register - a register of commands (instructions), hardware-based on the basis of the register (RG) with parallel loading by the gating signal (C);

- ADDR BUFF - Address Buffer - the address buffer hardware-based on the register (RG) with parallel loading by the gating signal (C) and a tristable output stage controlled by the output signal resolution (OE) input;

- MEMORY - memory, or storage device with a tristable bi-directional data output cascade (DATA), in the general case - MEM, since it can be performed both on the basis of random access integrated circuits (RAM) and read-only (ROM);

- ADDR - address lines;

- BADDR - buffered address lines;

- DATA BUS - data bus, tristable and bidirectional;

- INSTRUCTION CODE - operation code (instruction);

- ALU - Arithmetic-Logical Unit - Arithmetic Logic Unit (ALU);

Control and synchronization device - IDCU generates control signals according to the operating code (INSTRUCTION CODE) for all internal nodes of the processor, but the figure (Fig. 1) shows only those signals that relate to the operation of the active hardware stack of the processor and the main nodes interacting with it:

- RES IN - Reset Input - input of an external signal of initial initialization of the processor;

- CLK IN - Clock Input - input of an external clock signal;

- RES PC - Reset Program Counter - signal to set the software counter to its initial state;

- INC PC - Increment Program Counter - signal to increase the program counter by one;

- LD ADDR - Load Address - signal for parallel loading of the transition address to the program counter;

- STB ADDR - Strobe Address - signal (strobe) for writing the effective address to the address buffer;

- EN ADDR - Enable Address - permission signal for issuing an effective address to the address inputs of a storage device (memory);

- MEM WR - Memory Write - enable signal write to memory;

- MEM RD - Memory Read - permission signal to read from memory;

- INC SP - Increment Stack Pointer - signal to increase the stack pointer by one;

- DEC SP - Decrement Stack Pointer - signal to reduce the stack pointer by one;

- RES SP - Reset Stack Pointer - signal to set the stack pointer to its original state;

- STB INSTR - Strobe Instruction - signal (strobe) of writing the operation code (instructions) in the command register;

- INT IN - Interrupt Input - interrupt signal input from an external interrupt source.

According to the diagram shown in FIG. 1, the stack pointer SP is connected to the IDCU control and synchronization device via the control lines RES SP, INC SP and DEC SP with their inputs of the initial installation R, increment +1, and decrement -1. The outputs of the stack control logic 0 ÷ N of the SP stack pointer, which selects the active program counter, are connected to the activation inputs CS (Cheap Select) of the program counters PC 0, PC 1, ... PC N (total N + 1). The inputs of the same name increment +1, as well as the inputs for allowing parallel loading of PE (Parallel Enable) software counters are combined and connected respectively to the control outputs INC PC and LD ADDR control and synchronization devices IDCU. At each separate moment in time, these signals can be active only for one of the program counters selected at that moment in time by the stack stack pointer control logic SP. The program counter PC 0 is connected by its initial setup input R to the control output RES PC of the IDCU control and synchronization device, which allows it to be initialized with the start address value when the processor is turned on or by a RESET hardware reset signal. The outputs of the software counters PC 0, PC 1, ... PC N with tristable output stages are connected bitwise together and connected to the ADDR address inputs of the ADDR BUFF address buffer, and at each separate moment of time, only one of the counters selected by the stack pointer SP is active at the outputs stack control logic. The ADDR BUFF address buffer is connected at the input of the gate signal C and the output resolution enable signal OE with the IDCU control and synchronization device, whose control lines STB ADDR and EN ADDR respectively write to the effective address buffer from the output of the active program counter and enable the output of this address from the outputs BADDR buffers to the ADDR address inputs of the MEMORY, to which the output lines of the address buffer are connected. The entries of the write enable permission WE (Write Enable) and output enable data OE (Output Enable) of the MEMORY memory device are connected to the MEM WR and MEM RD outputs of the IDCU control and synchronization device, which allows the latter to allow the data from the MEMORY memory to be sent to the bi-directional and tri-stable bus DATA BUS data on the DATA outputs, or write to the memory the value from the bus through the same outputs, but which already perform the function of inputs.

Through the bi-directional and tristable data bus DATA BUS, the INSTRIN inputs of the IR command register are connected to the DATA pins of the MEMORY memory device, in which the operation code received from the memory is recorded on the gate signal C connected to the control output STB INSTR of the IDCU control and synchronization device . From the INSTR outputs of the register of IR commands connected to the IDCU control and synchronization device, the last one is the current operation code (INSTRUCTION CODE), according to which IDCU generates control signals for all internal nodes of the processor.

The ADDR inputs of the program counters PC 0, PC 1, ... PC N are connected to the bidirectional and tristable DATA BUS data bus. They are connected bitwise together, which allows the IDCU control and synchronization device to record the control transfer address in case of an unconditional transition using the LD ADDR control signal , calling a subroutine, or causing an interrupt from the data bus to the program counter selected by the CS input as the currently active stack control logic of the stack pointer SP.

The arithmetic logic unit ALU and other processor nodes not shown in the diagram of Fig. 1 are also connected to the bidirectional and tristable data bus DATA BUS, since they are not in direct interaction with the active hardware stack.

The inputs of the IDCU control and synchronization device, RES IN, INT IN, and CLK IN, respectively receive external signals of initial initialization (reset) of the RESET processor, hardware interrupt INT, and a clock sequence CLK that synchronizes the entire processor device.

The active hardware stack of the processor works as follows.

When the supply voltage is turned on or the processor is forced to initialize, the RES IN input of the IDCU control and synchronization device receives the active level of the external RESET initialization signal, and the clock input CLK receives the IN-sequence of external clock pulses CLK. During the operation of the RESET signal, synchronously with the CLK clock pulses, the SP stack pointer is set to the initial state by the active RES SP signal at the initial setup input R, as a result of which the active level appears at the output 0 of the stack control logic, which in turn transfers the CS to the active state is program counter PC 0. At the same time, the IDCU control and synchronization device, with the active signal RES PC, initializes the program counter PC 0 with the initial value of the address of the instruction for its input initial Settings R.

Upon completion of the RESET signal, the processor synchronously with the CLK clock pulses proceeds to the procedure of selecting the operation code (FETCH) from the memory. In this case, the starting address set in the active program counter PC 0 (usually 0) is copied via the ADDR address inputs to the ADDR BUFF address buffer synchronously with the active STB ADDR signal supplied by IDCU to the C address of the address buffer, while at the control input EN ADDR of the last the control and synchronization device sets the resolution level, as a result of which the address value from the BADDR outputs of the buffer goes to the ADDR address inputs of the MEMORY memory.

According to the INC PC signal supplied by the control and synchronization device to the inputs of the increment of +1 program counters, the output of the active counter PC 0 will set the following address value - one more, which will be transmitted to the ADDR address inputs of the MEMORY memory device during the subsequent FETCH procedure.

According to the MEM RD signal from the IDCU control and synchronization device, which is input to the OE data output enable input of the storage device, the contents of the cell at address 0 are sent to the DATA BUS and recorded in the IR command register by the active STB INSTR signal supplied by IDCU to the gate input C register .

This completes the procedure for fetching the operation code from the memory, and the current operation code (INSTRUCTION CODE), filed from the INSTR outputs of the IR command register to the inputs of the IDCU control and synchronization device, determines the sequence of IDCU control signals that organize coordinated joint work of internal processor nodes synchronously with CLK clocks in the next phase of instruction execution.

Suppose, for definiteness, that the instruction for incrementing a program counter is currently executable, since the absence of other processor nodes in the diagram of FIG. 1 that are not directly interacting with the active hardware stack does not allow us to consider other operations in detail. In this case, in the execution phase of the instruction for the increment inputs of +1 program counters, the IDCU control and synchronization device will send an active INC PC signal, as a result of which the output of the active counter PC 0 will be set to a value one more greater than its current value. After that, the execution phase of the instruction will be completed, the processor will proceed to the procedure of retrieving the following operation code from the memory using the algorithm described above, and such a sequential reading of instructions from the memory with their subsequent execution will occur until a hardware interrupt occurs, or in the program stored in memory, there will not be instructions for unconditional jump or subroutine call.

Consider the operation of the active hardware stack of the processor in the event of a subroutine call or interruption, as well as return from these procedures. To demonstrate the effectiveness of the proposed technical solution, we will consider the implementation algorithm of these procedures at the level of microoperations in relation to the sequence of input clock pulses CLK, shown in figure 2.

The CLK clock pulse period determines the duration of the internal clock of the Ti processor - the minimum time interval for which the IDCU control and synchronization device needs to organize both the selection of the instruction code from the memory and its execution through a sequence of microoperations, expressed in the supply of control signals to the corresponding processor nodes.

Since the processor is a synchronous system that executes its internal microoperations in relation to synchronization pulses, it becomes obvious that the characteristic time bindings on the Ti interval of the CLK signal — the pulse front and the pulse drop — are clearly insufficient to organize even the minimum number of microoperations in the selection and execution of the current instructions. Therefore, in the circuit of the control and synchronization device, two sequences of internal clock pulses are usually formed at the edges and at the edges of the CLK signal — C1 and C2. These two sequences over the duration of the Ti interval provide four time references — along the edges and decays of the clock pulses.

In the case of executing the subroutine call instruction on the pulse edge C1, the IDCU control and synchronization device sends an active signal STB ADDR to the input C of the address buffer, which captures the current instruction address from the outputs of the active program counter in it. At the same time, IDCU puts its control lines EN ADDR and MEM RD into active state, which allow the ADDR BUFF address buffer to send the instruction address to the ADDR inputs of the MEMORY memory device, and to the memory device to send the contents of the cell at the specified address to the DATA BUS data bus. By the end of pulse C1, the value of the operation code on the data bus lines can be considered steady, therefore, on the decline of C1, the control and synchronization device sends an active signal STB INSTR to the gate input C of the IR command register, thereby “latching” the current instruction (INSTRUCTION CODE) into it, whose code on the INSTR register output lines will be held at the IDCU inputs in the execution phase of the instruction. At the same time, the control and synchronization device supplies an active INC PC signal to the inputs of the increment + 1 program counters, as a result of which the address of the next program instruction appears at the output of the currently active program counter activated by CS input by the stack control logic.

Thus, in the first half of clock cycle 77 of the CLK signal, the control and synchronization device completes the procedure of retrieving the subroutine call operation code from the memory.

At the stage of performing this operation, as well as at the stage of transition to the interrupt service procedure, almost the same micro operations are performed, the contents of which are reduced to storing the return address and loading the program counter from the DATA BUS data address of the corresponding subprogram, but when the interrupt is serviced, this address is issued to the data bus an external device that caused the interrupt or a special internal device, in the event that the transition to the procedure for servicing the interrupt is fixed address.

So, in both cases under consideration, at the time of the pulse edge C2, which determines the beginning of the second half of clock cycle 77 of the CLK signal, a steady-state value of the subroutine address is present on the DATA BUS. On the front C2, the IDCU control and synchronization device sends the active signal INC SP to the increment input +1 of the SP stack pointer, as a result of which its content increases by one, and the stack control logic with its output i + 1 activates the next program counter PC i + at CS input 1, and the current program counter PC i goes into an inactive state, while retaining its value, which is the return address from the called routine. According to the decay of pulse C2, the value of the address of the subprogram from the DATA BUS data bus is written to the active program counter PC i + 1 by the LDADDR control signal supplied by the control and synchronization device to the parallel load resolution enable inputs of the PE program counters. Thus, the next operation of retrieving the operation code from the memory will be performed from the memory cell with the address recorded in the active program counter PC i + 1, which, in fact, is a transfer of control to the address of the subprogram or interrupt service routine. As can be seen from the above algorithm, these operations are performed by a processor that incorporates the claimed active hardware stack, strictly in one clock cycle.

To assess the factor of increasing the speed of the processor, which includes the claimed active hardware stack, we consider the sequence of microoperations performed by the processor with the usual stack of return addresses when servicing an interrupt or calling a subprogram.

In this case, the procedure for extracting the operation code from the memory has no specific features compared to the algorithm described above, and at the stage of transition to the called procedure, the sequence of microoperations will be different. On the edge of pulse C2, the IDCU control and synchronization device will send an active signal INC SP to the increment input +1 of the SP stack pointer, as a result of which its contents are incremented by one, and the stack control logic with its output i + 1 activates the next stack register at CS input. Upon the decline of C2, the contents of the program counter will be written into this register with an active signal from the control and synchronization device. To write to the program counter the address of the transition to the subprogram from the DATA BUS data bus, the next pulse C1 is required, by which the procedure for selecting the next operation code from the memory should already begin. Therefore, the control and synchronization device must block this sequence of microcommands for the next clock cycle, which complicates its structure for performing operations for a different number of clock cycles.

Considering that in order to execute a subroutine call operation or interrupt service, a processor that has the claimed active hardware stack incorporates enough states provided by pulses C1 and C2 for the duration of the clock cycle Ti of the CLK signal, a processor with a traditional stack also needs the next pulse C1, it is obvious that, strictly speaking, these operations are performed by the processor with the claimed solution, 33% faster. But taking into account the fact that the operation cannot be completed in the middle of the clock pulse, the processor with the traditional stack performs the operation of calling the subroutine or interrupt service in two clock cycles Ti and Ti + 1 of the CLK signal. Therefore, increasing the speed of the processor with the claimed solution when performing such operations reaches 50%, since it performs them in one cycle, which simplifies the circuit design of the control and synchronization device.

Let us evaluate the advantage that a processor possesses, which incorporates the claimed active hardware stack, compared to a processor with a traditional stack when performing a return operation from a subprogram or interrupt service routine.

The procedure for extracting the operation code from the memory in this case also has no features compared to the algorithm described above, and at the stage of returning from the called procedure, the sequence of microoperations performed by the processor with the claimed solution will be as follows. On the edge of pulse C2, the IDCU control and synchronization device will send an active signal DEC SP to the decrement -1 input of the stack pointer SP. As a result, its contents will decrease by one, and if before that the program counter PC i + 1 was active, then the stack control logic activates the program counter PC i at its CS input i and retains its state until that moment, which is the return address from the called routine. Thus, in fact, control is returned from the subroutine or interrupt service routine to the point of their call, and this operation is performed by the processor, which includes the claimed active hardware stack, in exactly one clock cycle.

For comparison, the processor with the traditional stack performs the operation of calling a subroutine or interrupt service as follows: along the edge of pulse C2, the IDCU control and synchronization device will send an active output enable signal to the stack register selected by the stack pointer SP, as a result of which its contents, the value of the return address, are the time equal to the pulse width C2 will take a steady value at the inputs of the software counter, and after the fall of C2, the active control signal LD ADDR supplied by the control device and synchronization to the inputs of the parallel load resolution PE of the software counter will be written to the last. On the edge C1 of the next clock, the control and synchronization device must remove the active enable register output enable signal from the stack register and apply the active signal DEC SP to the decrement -1 input of the stack pointer SP.

Obviously, a processor with a traditional stack performs a return operation from a subroutine or interrupt service routine for two clock cycles Ti and Ti + 1 of the CLK signal, and a processor with the claimed solution performs one clock cycle. Therefore, its speed when performing such operations is 50% higher than the processor with the traditional stack, while maintaining the circuit simplicity of the control and synchronization device.

Thus, a comparison of the operating algorithms of a processor, which includes an active hardware stack, with a processor having a traditional stack, allows us to consider the goal of the claimed technical solution to be achieved - creating a design of a software counter assembly working on the stack principle (or on the store principle), and allowing perform operations of switching to a subroutine or to an interrupt service procedure, as well as returning from them in one clock cycle, subject to the circuit simplicity of the processor.

The claimed solution - an active hardware stack - allows you to increase processor speed by 30-50% when performing subroutine call operations or interrupt service operations, as well as returning from them, due to the reduction in the number of clock cycles required for the hardware implementation of such operations.

Claims (1)

A processor hardware stack with a stack pointer and a stack control logic, including a software counter with tristable output stages, characterized in that the processor hardware stack additionally contains at least N software counters with tristable output stages, while the parallel load inputs of all software counters are connected bitwise together , the outputs of all program counters are connected bitwise together, the increment inputs of all program counters are connected together, the parallel enable inputs To download all program counters, they are connected together, the sampling inputs of each of the individual program counters are connected to the control outputs of the stack control logic of the same name, so that at any single moment in time, only one of the program counters selected by the stack pointer can be in an active state and perform its functions independently of the rest.

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