RU2523939C1 - Method and apparatus for error-compensation two-step integration - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device includes two identical integration sections which perform integration on two consecutive time sections, and an adder, wherein each integration section comprises an integrator, two closing switches, a commutator switch, two analogue memory units and an adder.

EFFECT: high accuracy of calculating an integral function.

2 cl, 3 dwg

Description

The field of technology.

The invention relates to automation and analog computing, and is intended to create precision integrators of analog signals of inertial devices of navigation systems and automatic control in space rocket systems.

The level of technology.

Known methods for reducing errors from input currents and bias voltage, used to reduce the error of integrators based on operational amplifiers (J. Rutkovsky. Integrated operational amplifiers. M: "Mir", 1978, p. 71-82), in which compensation measures by introducing additional resistors in the circuit of the operational amplifier. The disadvantage of this method is the need for individual selection of resistors for each operational amplifier and consideration in the design process of the influence of additional elements on the functioning of the device.

A known method of selective interval voltage integration (see patent 2218599, Russia), in which the reduction of errors from the integration of input currents and bias voltage of the active element without increasing the methodological error of voltage integration is achieved by the fact that the integration process is divided into cycles consisting of intervals, during one of which integrates the input voltage, and the remaining intervals make up a pause in which the structure of the active integrator changes for Integration of input currents and bias voltage, after the integration process is completed, the result is multiplied by the number of intervals. Reasons that impede the achievement of the technical result indicated below include integration over a number of cycles, which significantly reduces the device’s speed, limiting the waveform to only periodic functions, completely eliminating the possibility of obtaining continuous values of the integration function, and the hardware implementation of the method is complicated.

Closest to the proposed method is the integration of periodic voltage (see patent 2247428, Russia), in which the reduction of errors from the integration of input currents and bias voltage of the active element is achieved by the fact that the integration process is divided into N clock cycles, including working clocks and clocks of zero offset correction level, and an additional splitting of the integration process into two equal cycle times that are multiples of the input voltage period so that the number of cycles in each cycle is N / 2, at ohm during the first cycle of the odd cycles are operating, and strokes correction - even in the second working cycle are even strokes and strokes correction - odd. The reasons that impede the achievement of the technical result indicated below when using the prototype include limiting the waveform only to periodic functions, integrating for two periods of the periodic signal, which doubles the integration time, the inability to obtain continuous values of the integration function, the need to introduce additional measures that are not built into the method for measuring and correcting errors.

A known current integrator (see patent 2442177, Russia), in which the reduction of integration errors is achieved due to the fact that the device contains the main and auxiliary current integrators, each of which contains a source follower on a field-effect transistor with an insulated gate, the output of which is connected to an inverting input operational amplifier, and a capacitor is connected between the output of the operational amplifier and the gate of the transistor, the input of the first integrator through a key and a resistor connected to ground, and the output through a friend The key is connected to the input of the second integrator. The output of the latter through a resistor is connected to that balancing contact of the first amplifier, the connection to which provides negative feedback when the other key is closed. The disadvantage of this device is the need for preliminary (prior to integration) balancing of the integrator and limiting the use of the device to low currents.

Closest to the proposed one is an integration device (see patent 2222827, Russia), in which an increase in integration accuracy is provided by applying a circuit comprising two integration units, a reference voltage source, a pulse shaper, a model time interval shaper, and a pulse duration comparison unit. The output signal of the unit is supplied to the second information input of the integration unit, which compensates for the influence of destabilizing factors on the output signal of the integrating device. The influence of destabilizing factors on the output signal of the integrating device is reduced by supplying a voltage compensating for errors to the inverse input of the second integration unit.

The reasons that impede the achievement of the technical result indicated below include a limitation on applicability only for integrating constant voltages, the need to measure error values using additional units, the influence of stability and accuracy of additional units on the correction of integration errors, the latter greatly complicates the achievement of the required technical result.

The technical result consists in increasing the accuracy of calculating the integral function of converting the output signals of sensors of navigation systems without preliminary error measurements and selection of integrator elements.

The goal in the method is achieved by the fact that two signals are generated at the input of the integrating device, the voltage value of the first signal is equal to the input voltage in the first half-cycle and zero in the second, the voltage value of the second signal is equal to the input voltage in the second half-cycle and zero in the first, the output signal is the sum of the four voltage components obtained by the simultaneous integration of the signals generated at the input by two symmetric integrators, the first component is obtained by integration the first integrator of the first input signal in the first half-cycle, the second as the difference between the first component and the voltage obtained by integrating the first input signal by the first integrator for the full integration period, the third component is obtained by integrating the second integrator of the second input signal in the second half-cycle, the fourth component is obtained by integrating the second integrator of the second input signal in the first half-cycle and is fed to the input of the adder with the opposite sign.

The task is achieved in that the device consists of two identical integration sections on operational amplifiers, the device adder, the information inputs of both integration sections are connected to the information input of the device, the sections zeroing inputs are connected to the first control input of the device, the input of the rectangular pulse supply of the device integration period is connected to the fourth control input of the first integration section and to the third control input of the second integration section, an input under If a rectangular pulse of the first half-cycle of the device is connected to the second and third control inputs of the first integration section and to the fourth control input of the second integration section, the rectangular pulse feed of the second half-period is connected to the second control input of the second section, the first output of the first section is connected to the first input of the device adder , the second output of the first section is connected to the second input of the adder, the second output of the second section is connected to the third input of the adder of the device, third the output of the second section is connected to the inverse input of the adder of the device, the output of the adder is the output of the device, the integration section contains an integrator, three closing keys, one opening key, two analog memory blocks, a subtraction circuit on the adder, the information input of the integrator is connected to the first contact of the first closing key , the second contact of the first locking key is connected to the information input of the integrator and to the first contact of the disconnecting key, the second contact of the breaking key is connected to the zero potential, the first control input is connected to the control contacts of the first make-up key and the disconnect key, the second control input is connected to the control contact of the second make-up key, the third control input is connected to the control contact of the third make-up key, the zeroing input is connected to the reset input of the integrator, the integrator output is connected to the input contacts of the second and third locking keys, the output of the second locking key is connected to the input of the first block of analog memory, the output of the third locking the key is connected to the input of the second block of analog memory, the output of the first block of analog memory is connected to the first input of the adder of the integration section and to the first output of the integration section, the output of the second block of analog memory is connected to the inverse input of the adder and to the third output of the integration section, the output of the adder of the integration section is connected to the second output of the integration section.

These distinctive features of the claimed inventions can improve the accuracy of the device integrating input voltages by compensating for the effects of stray currents and voltages at the input of the integrator for one period without resorting to re-calculations.

The proposed technical solutions are new, since the proposed method and device for interval integration are not known from publicly available information.

The proposed technical solutions have an inventive step, since it does not explicitly follow from published scientific data and known technical solutions that the claimed sequence of operations of the method and the construction of the device lead to an increase in the accuracy of the integration method and device.

The proposed technical solutions are industrially applicable, as they are based on circuitry solutions and element base, widely used in analog and digital devices.

The push-pull integration method with error compensation is as follows.

Two voltages integrated simultaneously

$$u_{\mathrm{at}x\mathrm{one}}(t)=\{\frac{u(t),t=0\tau }{0t=\tau \mathrm{,\; 2}\tau }\text{(one)}$$

, $$u_{\mathrm{at}x2}(t)=\{\frac{0t=0\tau }{u(t),t=\tau \mathrm{,\; 2}\tau }\text{(2)}$$

,

where u (t) is the integrable voltage at the input of the device, u _in1 (t) is the voltage supplied to the input of the first integrator, u _in2 (t) is the voltage at the input of the second integrator, 2τ is the integration period. At the output of the device, 4 voltage functions are summed.

$$U_{\Sigma }(t_{\mathrm{and}})=U_{\mathrm{one}}^{\mathrm{one}}(t_{\mathrm{and}})+\Delta U_{\mathrm{one}}^3(t_{\mathrm{and}})+{\mathrm{<figure-callout\; id="2"\; label="U"\; filenames="00000026.png"\; state="\{\{state\}\}">U</figure-callout>}}_2^{\mathrm{one}}(t_{\mathrm{and}})-{\mathrm{<figure-callout\; id="2"\; label="U"\; filenames="00000026.png"\; state="\{\{state\}\}">U</figure-callout>}}_2^2(t_{\mathrm{and}}),\text{(3)}$$

which are obtained by integrating the input signal and spurious components introduced by integrating the input bias currents and shear stresses at the input of the integrators, t _and is the time since the start of integration.

получается интегрированием входного сигнала u_вх1(t) первым интегратором на первом полупериоде интегрирования:Voltage $$U_{\mathrm{one}}^{\mathrm{one}}(t_{\mathrm{and}})$$

obtained by integrating the input signal u _in1 (t) by the first integrator on the first half-cycle of integration:

$$U_{\mathrm{one}}^{\mathrm{one}}(t_{\mathrm{and}})={\displaystyle \underset{0}{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+u_{\mathrm{from}d\mathrm{at}\mathrm{one}}\cdot }{t}_{\mathrm{and}}+R\cdot i_{\mathrm{from}m\mathrm{one}}\cdot t_{\mathrm{and}}{\text{at t}}_{\text{and}}=\text{0}...\tau \text{(four)}$$

In the second half-cycle, this voltage remains unchanged:

$$U_{\mathrm{one}}^{\mathrm{one}}(t_{\mathrm{and}})={\displaystyle \underset{0}{\overset{\tau }{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+u_{\mathrm{from}d\mathrm{at}\mathrm{one}}\cdot }{\tau }_{\mathrm{and}}+R\cdot i_{\mathrm{from}m\mathrm{one}}\cdot \tau PR\mathrm{and}{t}_{\mathrm{and}}=\tau ...2\tau \text{(5)}$$

получается, как разность двух составляющих $$\Delta U{}_1{}^1(t_{и})$$

и $$\Delta U{}_1{}^2(t_{и})$$

:Voltage $$\Delta U_{\mathrm{one}}^3(t_{\mathrm{one}})$$

it turns out, as the difference of two components $$\Delta U{}_{\mathrm{one}}{}^{\mathrm{one}}(t_{\mathrm{and}})$$

and $$\Delta U{}_{\mathrm{one}}{}^2(t_{\mathrm{and}})$$

:

, $$\Delta U_{\mathrm{one}}^3(t_{\mathrm{and}})=U_{\mathrm{one}}^{\mathrm{one}}(t_{\mathrm{and}})-U_{\mathrm{one}}^2(t_{\mathrm{and}})\text{(6)}$$

,

- напряжение, полученное интегрированием u_вх1(t) на интервале 2τ:Where $$\Delta U{}_{\mathrm{one}}{}^2(t_{\mathrm{and}})$$

is the voltage obtained by integrating u _in1 (t) in the interval 2τ:

$$U_{\mathrm{one}}^2(t_{\mathrm{and}})={\displaystyle \underset{0}{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}}+R\cdot i_{\mathrm{from}m\mathrm{one}})\cdot t_{\mathrm{and}}{\text{at t}}_{\text{and}}=0...\tau \text{(7)}$$

$$U_{\mathrm{one}}^2(t_{\mathrm{and}})=U_{\mathrm{one}}^2(\tau )+(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})\cdot (t_{\mathrm{and}}-\tau ){\text{at t}}_{\text{and}}=\tau ...2\tau \text{(8)}$$

Subtracting from (4) - (7) and from (5) - (8), we isolate the error value of the first integrator on the second half-cycle:

$$\Delta U_{\mathrm{one}}^3(t_{\mathrm{and}})=0PR\mathrm{and}{t}_{\mathrm{and}}=0...\tau (9)$$

$$\Delta U_{\mathrm{one}}^3(t_{\mathrm{and}})=-(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})\cdot (t_{\mathrm{and}}-\tau ){\text{at t}}_{\text{and}}=\tau ...2\tau \text{(10)}$$

The third term of formula (3) is obtained by integrating the input signal u _in2 (t) by the second integrator on the second integration half-period:

$$\mathrm{<figure-callout\; id="2"\; label="\Delta \; U"\; filenames="00000026.png"\; state="\{\{state\}\}">\Delta \; </figure-callout>}{U}_{}^{}{}_2^{\mathrm{one}}(t_{\mathrm{one}})=0{\text{at t}}_{\text{and}}=0...\tau \text{(eleven)}$$

$${\mathrm{<figure-callout\; id="2"\; label="U"\; filenames="00000026.png"\; state="\{\{state\}\}">U</figure-callout>}}_2^{\mathrm{one}}(t_{\mathrm{and}})=(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot (t_{\mathrm{and}}-\tau )+{\displaystyle \underset{\tau }{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x2}(t)dt}{\text{at t}}_{\text{and}}=\tau ...2\tau \text{(12)}$$

The fourth term of formula (3) is obtained by integrating the second integrator on the first half-cycle of the input signal u _in2 (t):

$${\mathrm{<figure-callout\; id="2"\; label="U"\; filenames="00000026.png"\; state="\{\{state\}\}">U</figure-callout>}}_2^2(t_{\mathrm{and}})=(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot t_{\mathrm{and}}{\text{at t}}_{\text{and}}=0...\tau \text{(13)}$$

$${\mathrm{<figure-callout\; id="2"\; label="U"\; filenames="00000026.png"\; state="\{\{state\}\}">U</figure-callout>}}_2^2(t_{\mathrm{and}})=(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot \tau {\text{at t}}_{\text{and}}=\tau ...2\tau \text{(fourteen)}$$

Substituting formulas (4), (5), (9), (10), (11) - (14) in (3), we obtain:

$$U_{\Sigma }(t_{\mathrm{and}})={\displaystyle \underset{0}{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})}\cdot t_{\mathrm{and}}-(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot t_{\mathrm{and}}{\text{at t}}_{\text{and}}=0...\tau \text{(fifteen)}$$

$$\begin{array}{l}{U}_{\Sigma }(t_{\mathrm{and}})={\displaystyle \underset{0}{\overset{\tau }{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})}\cdot \tau -\\ -(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})\cdot (t_{\mathrm{and}}-\tau )+\\ +(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot (t_{\mathrm{and}}-\tau )+{\displaystyle \underset{\tau }{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x2}(t)dt-}\\ -(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot \tau =PR\mathrm{and}{t}_{\mathrm{and}}=\tau ...2\tau (\mathrm{one}6)\\ ={\displaystyle \underset{0}{\overset{\tau }{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+{\displaystyle \underset{\tau }{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x2}(t)dt}}+\\ +(u_{\mathrm{from}d\mathrm{at}\mathrm{one}}+R\cdot i_{\mathrm{from}m\mathrm{one}})\cdot (2\tau -t_{\mathrm{and}})-(u_{\mathrm{from}d\mathrm{at}2}+R\cdot i_{\mathrm{from}m2})\cdot (2\tau -t_{\mathrm{and}})\end{array}$$

As follows from formulas (15) and (16), if the characteristics of the two integrators are _close, u _sdv1 ≈u _sdv2 and i _cm1 ≈i _cm2 ,

при t_и=0…τ $$U_{\Sigma }(t_{\mathrm{and}})\approx {\displaystyle \underset{0}{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt}$$

for t _and = 0 ... τ

при t_и=τ…2τ $$U_{\Sigma }(t_{\mathrm{and}})\approx {\displaystyle \underset{0}{\overset{\tau }{\int }}{u}_{\mathrm{at}x\mathrm{one}}(t)dt+{\displaystyle \underset{\tau }{\overset{t_{\mathrm{and}}}{\int }}{u}_{\mathrm{at}x2}(t)dt}}$$

for t _and = τ ... 2τ

, приближающуюся к идеальной.Therefore, in this case, the effect of bias currents and shear stress is compensated, and the presented integration method allows us to obtain an integral function at the output of the device $$U_{\Sigma }(t_{\mathrm{and}})\approx {\displaystyle \underset{0}{\overset{t_{\mathrm{and}}}{\int }}u(t)dt}$$

approaching the ideal.

, так как в устройстве, реализующем представленный способ интегрирования, полностью компенсируются погрешности двух интеграторов, вносимые интегрированием входных токов смещения и напряжений сдвига.It follows from formulas (15) and (16) that for t _and = 2τ the result of integration exactly coincides with the mathematical value of the integral: $$U_{\Sigma }(2\tau )={\displaystyle \underset{0}{\overset{2\tau }{\int }}u(t)dt}$$

, since in a device that implements the presented integration method, the errors of two integrators introduced by integrating the input bias currents and shear stresses are fully compensated.

Figure 1 presents the structural diagram of a push-pull integration device with error compensation that implements the patented method, and figure 2 - section integration. The device consists of two identical integration sections 1 and the device adder 2, the information inputs 3 of both integration sections are connected to the information input of the device 4, the zeroing inputs of 5 sections are connected to the first control input 6 of the device, the input of the rectangular pulse supply of the integration period 7 of the device is connected to the fourth control the input 8 of the first integration section and to the third control input 9 of the second integration section, the input of the rectangular pulse of the first half-cycle 10 of the device the two is connected to the second 11 and third 9 control inputs of the first integration section and to the fourth control input 8 of the second integration section, the rectangular pulse input of the second half-cycle 12 is connected to the second 11 control input of the second section, the first output 13 of the first section is connected to the first input of the adder 2 devices, the second output 14 of the first section is connected to the second input of the adder 2, the second output 14 of the second section is connected to the third input of the adder 2 of the device, the third output 15 of the second section is connected to sleep adder input device 2, the output of the adder device is an output device. Each integration section (Fig. 2) contains an integrator 16, two locking keys 17, 18, a switch 19, two analog memory blocks 20, 21, a subtraction circuit on the adder 22, the information input 3 of the integration section is connected to the first contact of the switch 19, the second contact the switch is connected to the information input of the integrator 16, the third contact of the switch is connected to the zero potential, the second control input of the section 11 is connected to the control contact of the switch 19, the third control input of the section 9 is connected to the control contact of the first of the first closing key 17, the fourth control input 8 is connected to the control pin of the second closing key 18, the first control input of zeroing 5 is connected to the reset input of the integrator 16, the output of the integrator is connected to the input contacts of the first and second closing keys, the output of the first locking key is connected to the input of the first block of analog memory 20, the output of the second locking key is connected to the input of the second block of analog memory 21, the output of the first block of analog memory is connected to the first input of the adder 22 of the integrations section Nia and to the first output of the integration section 13, the output of the second analog memory unit is connected to the inverse input of the adder 22 and to third output of the integration section 15, integrating section output of the adder is connected to the second output of the integration section 14.

Figure 3 presents the voltage diagrams of a push-pull integration device with error compensation.

Consider the operation of the device for the case when the input signal u _in (t) has the form of rectangular pulses of duration 2τ. The input signal through the input 4 of the device is fed to the information inputs 3 of the first and second integration sections. Integration of the input signal begins with the termination of supply of the reset voltage U ₂ to input 6. A rectangular pulse of the integration period U _{3 of} duration 2τ is fed to input 7 of the device, and a rectangular pulse of the first integration half-cycle of U _{4 of} duration τ is fed to input 10, connecting the information input 4 of the device through the switch 19 to the input of the integrator 16 of the first section. At input time 12 at time t ₂ after the completion of the first half-cycle, a rectangular pulse of the second integration half-cycle U _{5 of} duration τ is supplied, connecting the information input 4 of the device through the switch 19 to the input of the integrator 16 of the second section.

In the first integral section in the first half-cycle, the pulse of the first integration half-wave U _{4 of} duration τ is supplied to the control contacts of the switch 19 and key 17, and the pulse of the integration period U _{3 of} 2τ duration is supplied to the control contact of the key 18, while the keys 17 and 18 are closed, information input 3 section through the switch 19 is connected to the information input of the integrator 16, and the voltage of the input signal voltage u _in (t) is supplied to the input of the integrator, the signal of the integral function of the input voltage is generated at the output of the integrator voltage for the first half-cycle containing the error induced by the bias current and shear stress. This signal through the key 17 enters the analog memory block 20 of the first integration section and from it is fed to the section 13 output and the first adder input of the section 22 U _in1Σ , through the closed key 18 the integrator signal enters the analog memory block 21, in which the voltage U _n2 , repeating in the first half-cycle U _in1Σ , and then the voltage U _n2 is applied to the inverse input of the adder 22 of the section. Thus, at the output 15 of the adder 22 of the first integration section and at the second input of the adder 2 of the device in the first half-cycle, the voltage U _in2Σ will be zero.

In the second integral section in the first half-cycle, the second contact and the third contacts of the switch 19 are closed, the keys 17 and 18 are closed, the input of the integrator 16 is at zero potential, a signal is generated at the output of the integrator that contains only the integral error function induced by the bias current and the shear stress for the first half-cycle of integration, which is recorded through closed keys 17 and 18 into analog memory blocks 20 U _n3 and 21 U _n4 . The voltage difference U _n3 -U _n4 from the adder of section 22 is supplied to the output 14 of the second section, setting the zero potential at the third input of the adder 2 of the device U _in3Σ in the first half-cycle. At the inverse input of the adder 2 of the device in the first half-cycle from the output 15 of the second section, a signal U _{input4Σ is} integrated signal of the integration error function of the integrator of the section U _n4 for the first half-cycle.

At time t ₂ , after a period of time τ after the start of integration, the pulse of the first half-cycle of integration U ₄ ends, while the key 17 is opened in the first integration section and the information input of the integrator is closed through the switch to ground, the potential is supplied to the input of the integrator of the first section, and only the induced error continues to be integrated, which, together with the accumulated integral component of the first half-cycle, is transmitted through the closed key 18 to the second block of analog memory 21. In the first the memory block 20 of the first section, the entire second half-cycle stores the voltage U _in1Σ (t ₂ ) accumulated over the interval τ, equal to the integral of the input voltage plus the integration error for the first half-period. It is fed to the first input of the adder 22 of the section and to the first input of the adder 2 of the device. During the integration process, a signal U _n2 is generated in the second memory block of the first section, which accumulates the integration error for the entire period and sums it with the integral function of the input voltage of the first integration half-period. This signal is fed to the inverted input of the adder of section 22, is subtracted from the voltage U _in1Σ , forming an error signal of the integrator of the first section for a half period U _in2ΣΣ .

In the second half-cycle in the second section, the key 17 is closed, the key 18 is open, the information input of the integrator through the switch is connected to the input of 3 sections. The voltage U _n4 at the output of the analog memory block 21 remains unchanged, equal to the integration error for the interval τ. The input of the integrator through the switch receives the voltage U _in (t), from the output of the integrator in the memory unit 20 receives the signal U _{n3 of the} integral function of the input voltage U _in (t) for the second half-cycle, containing the error induced by the bias current and the shear stress for the first half-cycle, plus the error accumulated from time t ₂ . The voltage U _n3 from the memory unit 20 is supplied to the first input of the adder of the section 22, and the voltage U _n4 from the memory unit 21 is supplied to the inverse input of the adder of the section 22 and to the third output 15 of the second integration section. At the output 14 of the second section, a signal U _{input 3Σ} (t) is formed, containing the integral function of the input voltage and the error signal for a period of time t ₂ -t ₃ . The output of the second section 15 is fed with the error signal of the integrator U _BX4Σ- with the opposite sign formed in the first half-cycle of integration.

At time t _{3, the} voltages U ₃ , U ₄ , U _{5 are} reset, the keys 17 and 18 in both sections open, the voltage values U _in1Σ (t ₃ ), U _n2 (t ₃ ), U _n3 are fixed in the memory blocks of the two integration sections (t ₃ ), U _n4 (t ₃ ). In the memory block 20 of the first section, the value of the integral function is fixed together with the integration error for the first half-period U _in1Σ (t ₃ ), which is stored until the next integration cycle, in the memory block 21 of the first section, the value U _n2 (t ₃ ) is fixed, which is equal to the sum of the integral function for the first half-cycle plus the value of the integration error accumulated by the integrator of the first section in two half-periods. U _in1Σ is fed to the first input of the adder 22 of the first section, and U _n2 is fed to its inverse input. Thus, at the second output 14 of the first integral section, the difference U _Bx2Σ (t ₃ ) = U _Bx1Σ (t ₃ ) -U _n2 (t ₃ ) is obtained, which is the error in integrating the integrator of the first section with the opposite sign, highlighted in the second half-period. By _feeding U _in1Σ (t ₃ ) and U _in2Σ (t ₃ ) to the adder of device 2, at time t ₃ we get a sum component that sets the exact value of the integral of the function U _in (t) for half a period t = 0 ... τ. In the memory block 20 of the second section, the value of the integral function is fixed together with the integration error U _n3 (t ₃ ) for the period, in the memory block 21 of the second section, the value U _n4 (t ₃ ) is fixed, which is equal to the allocated error of the integration of the second integrator over the half period from the output of the adder section at the time t _{3 the} voltage U _in3Σ = U _n3 (t ₃ ) -U _n4 (t ₃ ) equal to the value of the integral of the input function U _in (t) with the integration error for the second half-cycle is applied to the third input of the adder 2 of the device, it is subtracted from it _vh4Σ- voltage U (t ₃₎ = U _n4 (t ₃₎ supplied to the inverse in od adder 2, equal error integrator for integrating the second half, which is the output of the adder 2 of the apparatus fully compensates the accumulated error integrator for integrating the second half.

With balanced spurious components of the output voltages of the integrators of the two integration sections, the voltage U _Σ (t) at the output of the device approaches the ideal integral function of the input voltage over the entire integration interval, since in the adder 2 of the device in the first half-cycle, the integration function of the first integral section U _{in1Σ1 is corrected} ( t) the error voltage U _in4Σ- (t) of the second integral section, and in the second half-cycle, the integration function of the second integral section U _in3ΣΣ (t) is _corrected error voltage U _x2Σ (t) of the first integral section.

Similarly, the device will function with other forms of input signals.

The use of compensation for integration errors in the method and device of push-pull integration does not require alignment of integrators on operational amplifiers, additional procedures and schemes for measuring spurious components of integration can completely compensate for the influence of shear stresses and bias currents for one integration time interval, which distinguishes the proposed technical solution from prototypes.

Claims (2)

1. A push-pull integration method with error compensation, characterized in that during the integration process two signals are generated at the input of the integrating device, the voltage value of the first signal is equal to the input voltage in the first half-cycle and zero in the second, the voltage value of the second signal is equal to the input voltage in the second half-cycle and zero in the first, the output signal is found as the sum of the four components of the voltages obtained by simultaneously integrating the two symmetrical signals formed at the input and by tegrarators, the first component is obtained by integrating the first integrator of the first input signal in the first half-cycle, the second is obtained as the difference between the first component and the voltage obtained by integrating the first input signal by the first integrator for the full integration period, the third component is obtained by integrating the second integrator of the second input signal in the second half-cycle, the fourth the component is obtained by integrating the second integrator of the second input signal in the first half-cycle and fed to the input with mmatora with the opposite sign. 2. Push-pull integration device with error compensation, characterized in that it consists of two identical integration sections, the device adder, the information inputs of both integration sections are connected to the device information input, the sections zeroing inputs are connected to the device’s first control input, the input signal is a rectangular pulse of the integration period the device is connected to the fourth control input of the first integration section and to the third control input of the second integration section input, the input of the rectangular pulse of the first half-cycle of the device is connected to the second and third control inputs of the first integration section and the fourth control input of the second integration section, the input of the rectangular pulse of the second half-period is connected to the second control input of the second section, the first output of the first section is connected to the first the input of the adder of the device, the second output of the first section is connected to the second input of the adder, the second output of the second section is connected to the third input of the adder device, the third output of the second section is connected to the inverse input of the adder of the device, the integration section contains an integrator, two closing keys, a switch, two analog memory blocks, a subtraction circuit on the adder, the information input of the integration section is connected to the first contact of the switch, the second contact of the switch is connected to the information integrator input, the third contact of the switch is connected to zero potential, the second control input of the section is connected to the control contact of the switch, the third control the first input of the section is connected to the control pin of the first make-up key, the fourth control input of the section is connected to the control pin of the second make-up key, the first control input of the section is connected to the reset input of the integrator, the output of the integrator is connected to the input contacts of the first and second make-up keys, the output of the first make-up key is connected to the input of the first block of analog memory, the output of the second locking key is connected to the input of the second block of analog memory, the output of the first block of analog memory is connected to the first input of the adder of the integration section and to the first output of the integration section, the output of the second analog memory block is connected to the inverse input of the adder and to the third output of the integration section, the output of the adder of the integration section is connected to the second output of the integration section.

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