RU1795479C - Analog signal divider - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in measuring and computing systems for processing analog information. The purpose of the invention is to improve accuracy. This goal is achieved due to the fact that it is proposed to use a circuit implementation of a unit for generating the difference and sum of input signals that is different from the prototype, which includes five scale resistors, two switches and two operational amplifiers with corresponding connections, 2 or. vw fc

Description

The invention relates to electrical computing devices and can be used in measuring and computing systems for processing analog information,

Time-pulse devices are known that implement the division of analog signals based on their integration, comprising two integrators, a comparison unit, a reference voltage source, and analog switches. Their common drawback is that the result of the division substantially depends on the time constants of the integrators and, accordingly, has significant sensitivity to the drift of the resistances and capacitances of passive components.

Closest to the technical nature and purpose of the invention

is a device for dividing analog signals, in which the sensitivity to changing parameter values of passive components is reduced by introducing into the device a block for generating the difference and sum of the input signals as part of the adder and a single inverter. In the prototype, the formation of a periodic pulse sequence is performed by the same integrator, the parameters of the passive components of which do not, therefore, affect the value of the output voltage. In this case, the second integrator is designed as an averager and allows to obtain the quotient of the division of the input analog signals in the form of a constant voltage.

The disadvantage of the prototype is its low accuracy due to non-linearity,

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ABOUT

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Юь Yu

associated with the non-identity of the inversion coefficients of the dividend signal and the result of the summation of the dividend and divider signals, with significant hardware redundancy of the device. The non-linearity of the prototype is manifested in the inconstancy of its proportionality coefficient in the transfer characteristic. The coefficient a in the prototype depends on the input signals in accordance with the expression

(5as (5R (),

where yes is the relative deviation of the coefficient

6R - relative deviation of the resistors of the used resistors from the nominal, .-.

Y

Xl

X2

The aim of the invention is to remedy this drawback, i.e. to improve accuracy.

This goal is achieved in that the unit for generating the difference and the sum of the input signals contains the first and second scale resistors, the first conclusions of which are connected to the first and second information inputs of the block, and the second conclusions, respectively, through the first key and directly connected to the inverting input of the first operational amplifier connected through the third scale resistor with its output and the first output of the fourth scale resistor connected to the inverting input of the second operational gain l connected through the second key to the second output of the first scale resistor and connected through the fifth scale resistor to the output of the second operational amplifier connected to the output of the unit whose operation mode input is connected to the control inputs of the first and second keys.

The essence of the present invention consists in using the method of alternating formation on the basis of the same elements at the required time intervals of series-connected summing and inverting structures with simultaneous alternating changes in the sequence of their connection by alternately connecting a resistor to the inverting inputs of the first and second operational amplifiers.

In FIG. 1 is a diagram of an apparatus for dividing analog signals; in FIG. 2 - time diagrams of his work.

A device for dividing analog signals contains a first integrator 1, connected by an output to the first input of comparator 2, the second input of which is connected to the output of switch 3, and the output is connected to the information input of the second

integrator 4, the output of which is the output 5 of the device, and is also connected to the control input of switch 3, connected by the first and second information inputs to the source output

5 of the reference voltage and the bus of zero potential 7, block 8 forming the difference and the sum of the input signals, the first and second information inputs of which are respectively inputs 9 and 10

0 of the task of the divider and the divisible device, the output of block 8 is connected to the information input of the first integrator 1, the input of the task of the operation mode is connected to the output of the comparison unit. In this case, the block 8 of forming the difference and the sum of the input signals contains the first 11 and second 12 scale resistors, the first conclusions of which are connected to the first and second information inputs of block 8, and the second conclusions

0, respectively, through the first switch 13 and are directly connected to the inverting input of the first operational amplifier 14 connected through the third scale resistor 15 to its output and

5 by the first output of the fourth large-scale resistor 16 connected to the inverting input of the second operational amplifier 17 connected through the second key 18 to the second4 output of the first large-scale

0 resistor 11 and connected through the fifth

1.9 large-scale resistor to the output of the second

 operational amplifier 17 connected

with the output of block 8, the input mode reference

whose work is connected to the managers

5 inputs of the first 13 and second 18 keys ..

The device operates as follows. Let at the initial time t 0 integrator 1 and integrator-averager 4

0 are reset to zero. At the first input 9 of the device, the signal X2 proportional to the divider acts, and at the second input 10, the signal XL is proportional to the dividend.

In the time interval O.ti keys 3.1, 18

5 are closed, keys 3.2, 13 are open by the control signal + U from the output of comparator 2 (Fig. 26). The operational amplifier 14 together with the large-scale resistors 12, 15 form an inverter at this time interval, the input of which is connected

input 10 of the device. The operational amplifier 17 in conjunction with the scale resistors 16, 19 and with the scale resistor 11 connected to the inverting input of the operational amplifier 17 through the closed key 18, form an inverting adder at this time interval. The inverted voltage XL is supplied to the first input of the adder along the scale resistor 16 circuit and the voltage X2 to the second input via the scale resistor 11 circuit. The inverted difference of the input signals of the device is fed to the input of the integrator 1, at the output of which a ramp voltage Zi is generated (Fig. 2a). When the voltage Zi reaches the reference voltage E0 of the source 6 (time ti in Fig. 2a), the voltage at the output of the comparison unit 2 becomes equal to (-U) (Fig. 26).

In the time interval ti.ta, the keys 3.2,13 are closed, the keys 3.1, 18 are open by the control signal (-U) from the output of the comparison unit 2 (Fig. 26). The operational amplifier 14, together with the scale resistors 12, 15 and with the scale resistor 11 connected to the inverting input of the operational amplifier .14 through a closed key 13, form an inverting adder at this time interval, the inputs of which are inputs 9 and 10 of the device. An inverter formed on a given time interval by an operational amplifier 17 and scale resistors 16 and 19 is connected to the output of the specified adder. The voltages XT and / 2 are applied to the inputs of the adder. The inverted sum of the input signals through the inverter is transmitted to the input of the integrator 1. Thus, the sum of the voltages Xi and acts on the input of the integrator 1. X2, and a linearly decreasing voltage is generated at the output of the integrator 1 (Fig. 2a). When the input voltage 2.2 reaches the zero level (time t2 in Fig. 2a), the voltage at the output of the comparison unit 2 becomes + U (Fig. 26), as a result of which the keys 3.1, 18 are closed, and the keys 3.2, 13 open. Next, the voltage at the output of the integ

The leg 1 expands and the cycle repeats.

Thus, a periodic pulse train is generated at the output of Comparison Unit 2, which is averaged (W) using the averaging integrator 4 (Fig. 26). The result of the averaging generated at the output 5 of the device in the steady state is proportional to the desired quotient.

The device is based on the principle of analog compensation of the influence of the parameters of the passive components of the device on the result of dividing analog signals during push-pull generation of a periodic pulse sequence based on integration in one of them. the difference clocks, and in the other, the sum of the dividend and divider signals with an unchanged transmission coefficient of the dividend signal, which is achieved by performing the summation and inversion of the same elements in turn.

The average value W of the voltage of the pulse sequence W (t) from the output of the comparison unit 2, formed by the integrator-averager 4 at the output 5 of the device, is characterized as follows:

  §1 + Rn (Ris + Ri6) X2

f CPI

R15-R16

Ris + ri6

where Kf is the transfer coefficient of the integrator-averager 4;

Rn, Ria, Ris, Rie-values of the resistances of the resistors 11. 12, 15, 16.

From the above expression it is seen that

the coefficient of - does not depend on the quantities Xi and X2 themselves.

This determines the positive quality that is new in the invention with respect to the prototype — improving accuracy by eliminating the non-linearity of the transfer characteristic for any tolerance of the resistors.

Claims (1)

The claims Analog Divider signals containing the first integrator, connected by an output to the first input a comparison unit, the second input of which is connected to the output of the switch, and the output is connected to the information input of the second integrator, the output of which is the output of the device, and is also connected to the control input of the switch connected by the first and second information inputs to the output of the reference voltage source and the bus zero potential, the unit for generating the difference and the sum of the input signals, the first and second information inputs of which are respectively the inputs of the divider and the divisible device, the output is bl the eye is connected to the information input of the first integrator, the input of the operation mode setting is connected to the output of the comparison unit, characterized in that, in order to increase the accuracy, the difference and sum signal input unit contains the first and second scale resistors, the first conclusions of which are connected to the first and second information input0 5 I’ll give a block, and the second conclusions, respectively, through the first key and are directly connected to the inverting input of the first operational amplifier, connected through the third scale resistor to its output and the first output of the fourth scale resistor, connected to the inverting input of the second operational amplifier, connected through the second key to the second output the first scale resistor and connected through the fifth scale resistor to the output of the second operational amplifier connected to the output of the unit, the input no operating mode of which is connected to the control inputs of the first and second keys.