RU2513679C1 - Digital interpolator - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: digital interpolator includes an adder, a register, first and second binary counters, first and second AND element units, OR element units, first and second flip-flops, first and second delay lines, first, second, third and fourth AND elements, first and second digital inverters. The digital interpolator further includes a third binary counter with an input for setting the counter to its initial value, the inverting input for the second least significant bit of which is connected to the output X of the interpolator, and the output is connected through a second unit of AND elements to the input of the OR element unit.

EFFECT: enabling digital interpolation of a logarithmic curve.

2 dwg, 1 tbl

Description

The invention relates to digital computing and information technology and can be used in machine tools with programmed control and for preliminary processing of input information in automated research systems.

Known interpolator for software control of machines [A.S. 253896 USSR Interpolator for software control of machines, 1969], as well as a digital linear interpolator [SU 1629897 A1, 09.26.88] for straight lines on the display screen by piecewise linear approximation. The disadvantages of the known digital interpolators is the impossibility of digital interpolation of lines other than straight lines, for example, logarithmic.

The closest in technical essence is a linear interpolator in the evaluation function with a simultaneous step [Koshkin V.L. Hardware systems of numerical control. - M .: Engineering, 1989, p. 61, Fig. 3.14]. It consists of an adder, two registers with an input for presetting their contents, a block of OR elements and two blocks of AND elements, two counters with inputs for presetting an initial value, two triggers, two delay lines, four AND elements, two NOT elements. Moreover, the adder input through the block of OR elements is connected through the first and second blocks of AND elements to the first and second registers, and the control inputs of the blocks of AND elements through the delay lines are connected to the outputs of the first and second AND elements, the first inputs of which are connected through the logical element NOT to the sign output discharge of the adder, and the second inputs of the same elements And are connected with the output of the fourth element And, the input of which receives clock pulses. The outputs X and Y are connected with the outputs of the fourth and second elements I. The disadvantage of this interpolator is the impossibility of interpolating the logarithmic curve by it and the large absolute error equal to the interpolation step.

The objective of the present invention is to expand the functionality of a digital interpolator in terms of digital interpolation of a logarithmic curve.

The technical result of the present invention is the possibility of digital interpolation of the logarithmic curve and halving the maximum absolute error.

The problem is solved by the proposed digital interpolator, which contains an adder, a register, first and second binary counters (all with inputs for setting initial values), the first and second blocks of AND elements, the block of OR elements, the first and second triggers, the first and second delay lines, the first , the second, third and fourth elements AND, the first and second elements are NOT, moreover, the register is m-bit buses through the second block of AND elements and the block of OR elements is connected to the adder, the sign bit of which is connected with the second AND element and through the first the element is NOT connected to the input of the first element And, and the outputs of the first and second elements And through the first and second delay lines are connected to the enabling inputs of the second and first blocks of elements And, respectively, while the output of the second element And is the output Y of the interpolator and connected to the counting input of the second binary counter, the output of which is connected to the reset input in "0" of the first trigger, the direct output of which is connected to the input of the first element And, and the inverse output of which is connected to the input of the third element And, like the inverse output of the second rigger, but the reset input to "0" which is connected with the output of the first binary counter, the counting input of which is connected by the output X of the interpolator and with the output of the fourth element And, the output of which is also connected with the inputs of the first and second elements AND, in addition, the output of the third element And connected to the output "end of mining" and through the second element is NOT connected to the input of the fourth element And, the input of which is connected to the input of the clock pulses, and the input of the second element And is connected to the direct output of the second trigger, the input of the installation in "1" which, like the first trigger input is connected to the Start input, and finally, the interpolator preset input is connected to the reset inputs of the first and second triggers at “0”, and the direct output of the second trigger is connected to the input of the second element I. In addition, the digital interpolator a third binary counter is introduced with an input for setting its initial value, the counting input of the second least significant bit of which is connected to the output X of the interpolator, and the output is connected through the second block of AND elements to the input of the block of OR elements.

Replacing the first register with a binary counter with a preset input of its initial value is a new technical solution in the digital interpolation technique, since the results of the analysis of the analogues and prototype by the applicant did not allow identifying signs that are identical to all the essential features of this invention.

The proposed device has an inventive step, since it does not explicitly follow from published scientific data and existing technical solutions that the claimed combination of blocks, nodes and elements allows digital interpolation of a logarithmic curve.

The proposed digital interpolator is industrially applicable, since its technical implementation is possible using typical elements of microelectronic technology (integrated logic circuits).

Figure 1 shows the functional diagram of a digital interpolator, and figure 2 is a graph of the interpolation of a logarithmic curve.

The claimed device contains (Fig. 1) an adder 1 with an input 2 of a preset value, a register 3 with an input 4 of a preset value, an OR block 5, a first 6 and a second 7 blocks of AND elements, the first 28, the second 9 and the third 8 binary counters with inputs 29, 11, 10 preset their initial value, the first 12 and second 13 triggers, the first 14 and second 15 delay lines, the first 16, second 17, third 18 and fourth 19 elements AND and the first 20 and second 21 elements NOT. Adder 1, register 3, block of elements OR 5, blocks of elements AND 6, 7, counters 8, 9 and 28 have m bits, where m is the maximum bit depth of the input data, including the sign. Triggers 12, 13 have direct and inverse outputs, as well as inputs of setting "1" and reset to "0". Two elements And 18, 19 have two inputs, and two elements And 16, 17 - three inputs. Input 22 - the signal of the preset is designated PU. Input 23 - clock pulses - marked ƒ. Input 24 is designated Start. Outputs 25, 26 are designated X, Y, respectively. Output 27 is labeled "end of mining." Register 3 and the third binary counter with 28 m-bit buses through blocks of elements AND 6 and 7, respectively, are connected to the adder 1 through the block of elements OR 5, realizing communication with the adder actually through a multiplexer for two inputs. The sign bit Зн of adder 1 is connected to the element And 17 and through the element NOT 20 to the first element And 16. Their outputs through the delay lines 14 and 15 are connected to the enabling inputs of the blocks of elements And 7 and 6, respectively. In addition, the output of the second element And 17 is the output Y 26 of the interpolator. The input of the control panel 22 is connected to the reset inputs of the triggers 12 and 13 of the “0” input. The input Start is connected to the inputs of the same triggers. The direct output of the first trigger 12 is connected to the first element And 16, and the inverse to the third element And 18 The reset inputs to triggers 12 and 13 are connected to the zeroing outputs of the first 9 and second 28 counters, respectively. The direct output of trigger 13 is connected to the second element And 17, and the inverse to the third element And 18. The output of the element And 18 is connected to output 27 "end of mining" and through the second element NOT 21 with the input of the fourth element And 19, on the other whose input receives clock pulses ƒ (input 23). The output of the fourth element And 19 is connected to the inputs of the elements And 16 and 17, as well as to the counting inputs of the counters 8 and 9 and, in addition, with the output X 25 of the interpolator. And 17 is connected with the counting input of the binary counter 28 and with the interpolator output Y. The outputs of the first 16 and second 17 elements of And through the first 14 and second 15 of the delay line are connected to the inputs of the second 7 and first 6 blocks of And elements, respectively.

, где А, В - масштабы по осям Y и X соответственно. А, В - целые числа {В≥A). Тогда достаточно применить к известному (аналогу) линейному интерполятору с постоянными параметрами ΔU=ΔX-ΔY=const и ΔY=const переменные (меняющиеся вместе с номером i тактового импульса), то при замене регистра (с номером Рг 1 у прототипа) на третий двоичный счетчик 8 получим новое техническое решение, которое и составляет суть заявляемого патента.The reliability of achieving the goal of the invention — the implementation of digital interpolation of a logarithmic curve — is confirmed by the mathematical justification set forth in [Digital interpolators of curved paths - journal “Izvestiya Vuzov. North Caucasus region. ” Engineering, 2011, No. 2, p.16-18]. Logarithmic equation $$y=A\ln \left(\mathrm{one}+\frac{x}{\mathrm{at}}\right)$$

, where A, B are the scales along the Y and X axes, respectively. A, B are integers {B≥A). Then it’s enough to apply the variables (changing along with the clock pulse number i) to the well-known (analog) linear interpolator with constant parameters ΔU = ΔX-ΔY = const and ΔY = const, then when replacing the register (with the number Рг 1 in the prototype) with the third binary counter 8 we get a new technical solution, which is the essence of the claimed patent.

For this, ΔY = 2A-2 = const, and ΔU = 2B-2A + 2 + 2i ≠ const. To ensure the minimum error for digital interpolation (no more than 0.5 interpolation steps), it is necessary to take the initial value of the adder-subtractor 1 not equal to zero, as in the prototype [3], but equal to B-2A.

In the initial state of the interpolator by applying a pulse to the input of the control unit 22, the triggers 12 and 13 are reset to "0". At the Start signal (input 24), triggers 12 and 13 are set to “1”, in addition, at input 2, a constant (2B-2A) is entered at adder 1, at input 10, a constant (2B-2A) is entered at counter 8, at the input 4, constant 3 is entered into register 3 - (2A-1) in the additional code and, upon input 11, into counter 9, the value "-ΔX _max " in the additional code. Next, two signals "0" from the triggers 12 and 13 through the element And 18 and the element NOT 21 will open the element And 19, and the next positive pulse with a frequency of ƒ (input 23) will follow the input of the elements And 16 and 17, as well as the output X 25 of the interpolator . It will follow the output Y 26 of the interpolator if the sign of adder 1 is "-" (unit in the sign digit Зн). At the same time, a positive impulse from the output of the And 19 element arrives at the counting input with the weight "+2" of the binary counter 8, increasing its value by two.

If the sign Зн of the adder 1 is "+" (zero in the sign digit), then the signal will not pass to the output Y 26 (AND element 17 will be closed). After some time (the delay time is less than a quarter of the period of frequency ƒ), a positive pulse arises at the output of the first delay line Zd 14 or the second delay line Zd 15 (only one), each of which either adds up the contents of register Pr 3 (through the block of elements And 7 and the block elements OR 5) to the adder cm 1, or - the contents of the binary counter SC 8 (through the block of elements AND 6 and the block of elements OR 5) to the adder cm 1. At this, one clock cycle of the input pulses will end. The new value of the sign Зн adder Сm 1 will control the operation of the interpolator in the next step. Each worked cycle ƒ at the input 23 is calculated by the signal from the output X 25 counter MF 9, working as a subtractor. When exactly X _max pulses are received, the binary counter Сч 9 will give a signal to reset to “0” triggers 12 and 13. The signals “1” from their inverse outputs through the third element And 18 and the third element NOT 21 will close the fourth element And 19, interrupting thereby pulses from input ƒ 23.

The interpolator is over. A high level of "1" from the output of the third element And 18 gives a signal "finished mining." As a result of mining, a digital interpolation of the logarithmic curve will be performed with a maximum absolute error equal to 0.5 interpolation steps.

The reliability of the operation of the claimed digital interpolator is confirmed by a simple example with A = 7 and B = 11 (see table 1 and figure 2). Small values of A and B are taken for reasons of reducing the size of table 1.

Table 1 The results of the digital interpolator (with A = 7, B = 11, X _max = 12) i Cm 1 Mid 8 Wg 3

$${\displaystyle \sum x_i}$$

$${\displaystyle \sum {\mathrm{<figure-callout\; id="7"\; label="y\; i"\; filenames="00000006.png"\; state="\{\{state\}\}">y\; </figure-callout>}}_i}$$

$$7\cdot \ln \left(\raisebox{1ex}{$\mathrm{one}+x$}\!\left/ \!\raisebox{-1ex}{$\mathrm{eleven}$}\right.\right)$$

0 -3 10 -13 0 0 0 one 7 12 -13 one one 0.609 2 -6 fourteen -13 2 one 1,169 3 8 16 -13 3 2 1,688 four -5 eighteen -13 four 2 2,171 5 13 twenty -13 5 3 2,623 6 0 22 -13 6 3 3,047 7 -13 24 -13 7 3 3,447 8 eleven 26 -13 8 four 3,826 9 -2 28 -13 9 four 4,185 10 26 thirty -13 10 5 4,526 eleven 13 32 -13 eleven 5 4,852 12 0 34 -13 12 5 5,163

Claims (1)

 A digital interpolator containing an adder, a register, first and second binary counters (all with initial value inputs), the first and second blocks of AND elements, the block of OR elements, the first and second triggers, the first and second delay lines, the first, second, third and the fourth AND element, the first and second elements are NOT, and the register is m-bit buses through the second block of AND elements and the block of OR elements is connected to the adder, the sign bit of which is connected to the second AND element and through the first element is NOT connected to the input of the first AND element, and at the outputs of the first and second elements And through the first and second delay lines are connected to the enable inputs of the second and first blocks of elements And, respectively, while the output of the second element And is the output Y of the interpolator and is connected to the counting input of the second binary counter, the output of which is connected to the reset input in "0" of the first trigger, the direct output of which is connected to the input of the first element And, and the inverse output of which is connected to the input of the third element And, like the inverse output of the second trigger, but the reset input to "0" of which is connected to the output the house of the first binary counter, the counting input of which is connected with the output X of the interpolator and with the output of the fourth element And, the output of which is also connected with the inputs of the first and second elements And, in addition, the output of the third element And is connected with the output "end of mining" and through the second element NOT connected to the input of the fourth AND element, whose input is connected to the input of clock pulses, and the input of the second AND element is connected to the direct output of the second trigger, the input of which is set to “1”, which, like the analogous input of the first trigger, is connected to the Start input, and, finally, the preset interpolator input is connected to the reset inputs “0” of the first and second triggers, and the direct output of the second trigger is connected to the input of the second element And, characterized in that a third binary counter is additionally introduced with the input of setting its initial value, counting the input of the second low order bit is connected to the output X of the interpolator, and the output is connected through the second block of AND elements to the input of the block of OR elements.

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