RU2504865C1 - Cmos-transistor with vertical channels and common gate - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: two complementary transistors are combined in CMOS-transistor into a compact structure with vertical channels of p- and n-junctions which are located in parallel to each other and have common gate. The gate is isolated from channels by dielectric and shaped in non-conductive area in-between transistors. Sinks of CMOS-transistor channels are interconnected by ohmic conductors at the lower side of structure while sources of transistors have separate outputs at the upper side.

EFFECT: invention allows simplification of structure, decreasing its sizes and increasing operating speed of CMOS-transistor.

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Description

The invention relates to semiconductor devices, namely to complementary MOS transistors and can be used in digital inverter circuits and memory devices.

Known vertical field-effect transistor (PT) containing a semiconductor substrate, drain (source) with n ⁺ -type of conductivity, vertical conductive channels with n-type of conductivity, a gate made in the form of a metal tape perforated within the semiconductor structure, dielectric layers on the bottom and the upper surfaces of the tape, which are adjacent to the lateral surfaces of the vertical channels, and the source (drain) with n ⁺ type conductivity [1]. Schottky barriers form between the gate and the channels. The transistor is made of gallium arsenide (GaAs).

However, this device uses vertical channels with only n-type conductivity.

A known vertical PT [2] containing a substrate with an n ⁺ -type of conductivity, which is the source (drain) of channels with an n-type of conductivity, metal gates placed on non-conductive areas of the device structure and forming Schottky barriers with channels, as well as drains with n ⁺ -type of conductivity. Between the substrate and the channels are two additional layers. The first epitaxial layer with n ⁺ -type conductivity is a buffer between the substrate and channels, the second layer is made of AlGaAs. All other areas of the device are made of GaAs. In addition, a Schottky diode (DS) is additionally formed on the same crystal. A vertical focal point with a longitudinal beam forms a composite device.

However, this device also uses vertical channels with only n-type conductivity.

Known vertical PT [3], containing the metal output of the source, ohmic contact to the source, the source made of an n ⁺ -type semiconductor, vertical conductive channels with n-type conductivity, the shutter made in the form of a metal tape perforated within the semiconductor structure , dielectric layers on the lower and upper surfaces of the tape, which are adjacent to the lateral surfaces of the vertical channels, and a drain with an n ⁺ type of conductivity. Schottky barriers form between the gate and the channels. To increase the output power of the device, the gallium arsenide substrate was replaced by a dielectric substrate with higher thermal conductivity. A damping layer of ductile metal was also introduced between the semiconductor structure and the dielectric substrate in order to increase the reliability and durability of the device by reducing mechanical stresses in it.

This device also uses vertical channels with only n-type conductivity.

The closest to the claimed device, selected as a prototype, is a CMOS inverter [4], consisting of two field-effect transistors with channels p- and n-types of conductivity (complementary transistors), connected in series and having a metal-oxide-semiconductor structure [MOS ], which is called a CMOS transistor.

The manufacturing technology of CMOS transistors (CMOS technology) is constantly being improved and is the basis of modern micro- and nanoelectronics [5]. When using bulk CMOS technology, transistors are placed in the bulk of the substrate, and an additional pocket is created to form a MOS transistor with a channel having the same type of conductivity with the substrate. The areas in which the transistors are located are isolated from each other using a closed p-n junction. To suppress the snapping-in effect, guard rings or dielectric are used to isolate complementary transistors.

CMOS transistors made using the silicon-on-insulator (SOI) technology are placed on an insulator (oxide), which isolates the active region of the device from the substrate, and there is also vertical isolation, so the transistors are isolated on all sides by oxide layers, so the thyristor effect between complementary transistors is eliminated. Using SOI technology allows you to reduce the distance between MOS transistors, which leads to an increase in integration density [5].

However, various designs of known CMOS transistors have a distinctive feature. In each transistor, the source, channel and drain are located in a horizontal plane (planar structure), which leads to an increase in the size of the device and when using volume CMOS technology, it is necessary to apply special measures to eliminate the “snap” effect.

The technical result of the invention is to reduce the size and simplify the design of a CMOS transistor.

The inventive device containing complementary MOS transistors uses a compact structure with parallel vertical channels with p- and n-types of conductivity. Between the transistors there is a non-conductive region (dielectric), on which there is a common gate isolated from the channels by dielectric oxide. The gate thickness should correspond to the lengths of the transistor channels and may have submicron dimensions. To reduce the resistance of the gate, its thickness in the middle part may be greater than at the edges of the gate in contact with the insulating channel oxide.

The drains of the transistor channels are interconnected by ohmic contacts located on the lower side of the vertical structure, and the sources of the transistors have separate terminals on the upper side of the structure.

The vertical structure makes it possible to reduce the length of the channels, which will increase the speed of the device, in addition, complementary transistors are isolated from each other by a non-conductive region (dielectric), therefore parasitic bipolar n-p-n and p-n-p transistors are not formed and the “snap” effect is eliminated. The proposed device combines two complementary MOS transistors with vertical channels and a common gate in a single compact structure, thereby achieving the claimed technical result.

Figure 1 shows a possible variant of the device in plan and its cross section, where 1 is the substrate, 2 and 3 are regions with n- and p-types of conductivity, respectively, 4 and 5 are drains of transistors with p ⁺ and n ⁺ types conductivity, 6 and 7 are the sources of transistors with p ⁺ and n ⁺ types of conductivity. The drains of the transistors are interconnected using an electrode 8. The sources of the transistors have separate terminals 9 and 10, respectively. Gate 11 is common to complementary transistors. The shutter is aligned with regions 2 and 3 using a non-conducting region 12. The shutter is isolated from regions 2 and 3 by oxide 13 and 14, respectively.

The device operates as follows. The source 9 of the first MOSFET with the p-type channel is supplied with a positive voltage U ₀ relative to the source 10 of the second MOSFET with the n-type channel. The input signal U _{in is} applied to the common gate 11. The output voltage U _{out is} removed from the drains of the MOS transistors 8. When U _in ≈ 0 (logical “0” at the input) and the input voltage is less than the threshold voltage of the second transistor, then the n-channel is not induced and the second transistor is closed. Moreover, at U _I <U ₀ , the gate-source voltage of the first transistor is negative and may be sufficient to turn on the first transistor. In this case, U _{o out} <U ₀ (ie logical “1”). If Uin ≅ U ₀ (logical “1” at the input) and U _{in is} greater than the threshold voltage of the second transistor, then an n-type channel is induced in region 3 and the second transistor opens and the first transistor closes, so U _output ≈0 (i.e. logical “0”).

In the stationary state, one of the transistors is closed, so the current through the device is determined only by leakage currents through the junctions. At the time of switching, a short current pulse passes through the device. Low power consumption in stationary mode is the advantage of CMOS transistors.

The device can be made of silicon or from semiconductor materials of group A ^III B ^V with higher electron mobility.

Compared with the prototype, the proposed CMOS transistor with a common gate and a vertical structure will allow:

- reduce the size and simplify the design of the device;

- increase the performance of the device by reducing the length of the channels.

Information sources

1. Hollis M.A., Bozler C. O., Nichols K.B., Bergeron N.J. Vertical transistor device fabricated with semiconductor regrowth. Patent No.US4903089 (A), IPC: H01L 29/80, claimed 02/02/1988, publ. 02/20/1990

2. Brar B.P.S., On W. Vertical field-effect transistor and method of forming the same. Patent No. US7663183, pending. 06/19/2007, publ. 02.16.2010

3. Semenov A.V., Khan A.V., Khan V.A. Vertical field effect transistor. Patent No. RU2402105, IPC: H01L 29/772, claimed 08/03/2009, publ. 10.20.2010 g.

4.Maller R., Keymins T. Elements of integrated circuits. Per. from English - M .: Mir, 1989, - p. 543-551.

5. Zebrov G.I. Physical foundations of silicon nanoelectronics. - Binom. Laboratory of Knowledge, 2011 - p. 34-35, 159-161.

Claims (1)

A CMOS transistor with vertical channels and a common gate, containing two complementary MOS transistors connected in series, characterized in that the device uses parallel vertical channels with p- and n-types of conductivity and a common gate located on the non-conducting region between the transistors and isolated from the channels by oxide, while the drains of the transistor channels are interconnected by ohmic contacts on the lower side of the vertical structure, and the sources have separate leads on the upper Oron structure.