RU2475929C2 - Frequency multiplier by even factor n - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: frequency multiplier contains a converter of three-phase voltage into a system of N-phase output voltage with N magnetic circuits, each having three input windings, an output windings and a control winding positioned thereon, an external source of three-phase sine voltage and an external load connected to the output clamps, N controllable keys based on diodes and transistors, N straight-line capacitors.

EFFECT: reducing power losses.

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Description

The invention relates to the field of electrical engineering and can be used as a power source of increased industrial and higher frequencies.

Known frequency multiplier an even number N times [1], containing an external sinusoidal three-phase voltage source, N magnetic circuits, on which the windings of the three-phase voltage to N-phase converter are located, windings of a DC bias circuit, windings of a self-biasing circuit with an intermediate frequency and output windings, connected to a longitudinal compensation capacitor in a series circuit, two output terminals to which an external load is connected.

A disadvantage of the known technical solution is the large power loss, due to the following reasons.

The magnetic cores operate in a deep saturation mode, in which the area of the hysteresis loop of the ferromagnet reaches its largest size, so the power loss in the magnetic cores is of maximum importance. In addition, in this mode, the inductance of the windings sharply decreases due to which large input currents flow in them, which also leads to an increase in power loss.

When multiplying an even number of times, it is necessary to introduce DC magnetization circuits, since the characteristics of a ferromagnet are an odd function. To increase the efficiency of multiplication, self-magnetization circuits with an intermediate frequency are introduced. The presence of these circuits leads to an additional increase in power loss.

The aim of the invention is to reduce power losses.

This is achieved by the fact that the frequency multiplier is an even number of times N, containing a three-phase voltage converter into a symmetric system N of phase voltage from N magnetic circuits with one output winding (BO) and three input windings (BXO) located on each of them, connected in series and connected to the outputs of an external source of three-phase sinusoidal voltage, as well as the first and second output terminals to which an external load is connected, while the first terminals of each VO are interconnected and connected to In the output terminal, N controlled keys (CC), N control windings (CC), located one on each of N magnetic cores, and N capacitors (K) are introduced, while the first power terminals (CB) of each CC are connected to the second terminal BO , the control terminals of each UK are connected to the corresponding ends of each UO, the second CBs of each UK are connected to the first terminals of each K, and the second terminals of each K are connected to each other and connected to the second output terminal.

Figure 1, as one of the variants of a harmonic frequency multiplier an even number of times, shows a frequency quadrupler circuit (N = 4).

The harmonic frequency multiplier contains a three-phase voltage converter 1 into a symmetrical four-phase voltage system, containing the first 2, second 3, third 4 and fourth 5 magnetic cores, with one output winding located on each of them: first BO 6, second BO 7, third BO 8 , the fourth BO 9 and three BXO, connected in series and forming the first phase chain, consisting of the first BXO 10, the second BXO 11, the third BXO 12 and the fourth BXO 13, the second phase chain, consisting of the fifth BXO 14, the sixth BXO 15, the seventh BXO 16 and eighth BXO 17, a phase circuit consisting of the ninth ВОО 18, the tenth ВХО 19, the eleventh ВХО 20, and the twelfth ВхО 21, and connected to the outputs of an external source of a three-phase sinusoidal voltage 22, as well as the first 23 and second output terminals 24, to which an external load 25 is connected, the first UK 26, the second UK 27, the third UK 28 and the fourth UK 29, the first UO 30, the second UO 31, the third UO 32 and the fourth UO 33 located on the first 2, second 3, third 4 and fourth 5 magnetic cores, respectively, and the first K 34, the second K 35, the third K 36 and the fourth K 37, while the first CB 38 p the first CC 26 is connected to the second terminal of the first BO 6, the first CB 39 of the second CC 27 is connected to the second terminal of the second BO 7, the first CB 40 of the third CC 28 is connected to the second terminal of the third BO 8 and the first CB 41 of the fourth CC 29 is connected to the second terminal of the fourth VO 9, the first HC 42 of the first UK 26 is connected to the end of the first UO 30, the first HC 43 of the second UK 27 is connected to the end of the second UO 31, the first HC 44 of the third UK 28 is connected to the end of the third UO 32 and the first HC 45 of the fourth UK 29 is connected to the end of the fourth UO 33, and the second HC 50 of the first UK 26 is connected to the initial output per howling MA 30, the second HC 51 of the second UK 27 is connected to the initial output of the second UO 31, the second HC 52 of the third UK 28 is connected to the initial output of the third MA 32 and the second HC 53 of the fourth UK 29 is connected to the initial output of the quad UO 33, while the second CB 46 of the first Criminal Code 26 is connected to the first terminal of the first K 34, the second CB 47 of the second Criminal Code 27 is connected to the first terminal of the second K 35, the second CB 48 of the third Criminal Code 28 is connected to the first terminal of the third K 36 and the second CB 49 of the fourth Criminal Code 29 is connected to the first terminal fourth K 37, while the second conclusions of the first K 34, the second K 35, the third K 36 and Th solid K 37 are interconnected and connected to the second output terminal 24.

Figure 2 shows, as an example, two options for circuit solutions of a controlled key built on a bipolar transistor and semiconductor diodes, as well as circuits connected to them. All managed keys are identical, therefore, to explain their features, consider the first managed key 26.

In the circuit of FIG. 2, the controlled key is a bridge made on the first semiconductor diode (PD) 54, the second PD 55, the third PD 56, the fourth PD 57 and the transistor 58 included in one of the diagonals of the bridge. Another diagonal of the bridge is formed by the power terminals 38 and 46. The control terminals 42 and 50 are connected to the base and emitter of the transistor 58, respectively.

In the circuit of FIG. 2, b, the controlled key 26 consists of a transistor 59 and a PD 60, while the emitter of the transistor 59 and the anode of the PD 60 are connected to the first CB 38, and the collector of the transistor 59 and the cathode of the PD 60 to the second CB 46. The first HC 42 and the second HC 50 are connected to the base and emitter of the transistor 58.

Consider the operation of the multiplier under the assumption that the load resistance 25 is close to zero.

An input voltage with a frequency f generated by a sinosuidal three-phase voltage source 22 is transmitted to the inputs of the number of phases 1 input voltage converter and converted into a symmetrical four-phase voltage system containing the first 2, second 3, third 4 and fourth 5 magnetic circuits with each three input conversion windings forming the first phase circuit (windings 10, 11, 12 and 13), the second phase circuit (windings 14, 15, 16 and 17) and the third phase circuit (windings 18, 19, 20 and 21) connected in series . As a result, on the first VO 6, the second VO 7, the third VO 8 and the fourth VO 9, a symmetric four-phase system of voltages u ₁ , u ₂ , u ₃ and u _{4 is created} (Fig. 3). Further, the voltage u _{1 is} supplied to the first serial circuit formed by the first UK 26 and the first K 34, the voltage u _{2 is} supplied to the second serial circuit formed by the second UK 27 and the second K 35, voltage u _{3 is} supplied to the second serial circuit formed by the third UK 28 and the third K 36, and the voltage u _{4 is} supplied to the fourth serial circuit formed by the fourth UK 29 and the fourth K 37.

As a result, at the first UO 30, the second UO 31, the third UO 32 and the fourth UO 33, magnetically coupled to the first VO 6, the second VO 7, the third VO 8 and the fourth VO 9, respectively, antiphase control voltages are formed. Therefore, at time intervals T / 2 (T is the period of the input frequency), when u ₁ , u ₂ , u ₃ and u _{4 are} greater than zero, the control voltages at the first UO 30, the second UO 31, the third UO 32 and the fourth UO 33 are also greater zero, power terminals 38 and 46 of the first Criminal Code 26, power terminals 39 and 47 of the second Criminal Code 27, power terminals 40 and 48 of the third Criminal Code 28, power terminals 41 and 49 of the fourth Criminal Code 29 are closed. As a result, the first K 34, the second K 35, the third K 36, the fourth K 37 are connected to the first VO 6, the second VO 7, the third VO 8, and the fourth VO 9, respectively. Moreover, during the positive half-wave of these voltages, the charge q _{1 of the} first K 34, the charge q _{2 of the} second K 35, the charge q _{3 of the} third K 36, the charge q _{4 of the} fourth K 37 repeat the form of the output voltages u ₁ , u ₂ , u ₃ and u ₄ respectively (figure 3, b). Therefore, the current i ₁ = dq ₁ / dt flows through the first serial circuit, consisting of the first CC 26 and the first K 34 (Fig. 3, b), the current i ₂ = dq ₂ / dt flows through the second serial circuit (Fig. 3, b), the current i ₃ = dq ₃ / dt flows along the third serial circuit (Fig. 3, b) and the current i ₄ = dq ₄ / dt flows along the fourth serial circuit (Fig. 3, b). Since the currents i ₁ , i ₂ , i ₃ , i ₄ are derived from the charge, then in the first quarter of the period T they flow in one direction (marked with a + sign in Fig. 2 and hatching), and in the second quarter of the period T in the opposite direction.

In the circuit implementation of the controlled keys 26, 27, 28 and 29 in the form of diode-transistor circuits (Fig. 2), the control terminals 42 and 50, 43 and 51, 44 and 52, 45 and 53 are the terminals of the base emitter of transistors, and the power terminals of these keys 38 and 46, 39 and 47, 40 and 48, 41 and 49 are the collector-emitter terminals of these transistors.

The current i _n flowing through the external load 25 is equal to the sum i _n = i ₁ + i ₂ + i ₃ + i ₄ . Figure 3, in it is highlighted in bold and represents an oscillation whose frequency is four times the frequency f of the input voltage. Therefore, the device is a frequency quadrupler.

As can be seen from figure 3, in the currents i ₁ , i ₂ , i ₃ and i ₄ flow in two directions: positive and negative. Moreover, the average value of each of these currents for the period T is zero, i.e. there is no DC component. Therefore, there are no DC losses in these circuits and, therefore, the frequency conversion proceeds with high efficiency, limited only by ohmic losses in the keys, output and control windings, and losses in the material of the cores and capacitors. Using a modern elemental base, these losses amount to several percent in the range of sufficiently high frequencies (up to MHz and higher).

When the resistance R _{n of the} external load 25, other than zero, the operation of the device varies slightly. This is due to the fact that, according to the laws of switching, the current flowing through the output windings having inductive resistance cannot instantly change. As a result, due to the finite resistance R _{n, the} process of increasing currents i ₁ , i ₂ , i ₃ and i ₄ will occur not instantly, but more smoothly, which leads to a smooth increase in current i _n . Therefore, the shape of the output current will approach a sinusoidal frequency of 4f.

The device works in a similar way for other multiplications of N.

The implementation of the claimed device is as follows. The phase number converter 1 performs the following functions [2]: converts a small output impedance of a three-phase sinusoidal voltage source 22 into a small output impedance of a phase converter 1, at which its maximum transfer coefficient is achieved; creates relative phase shifts Φ _N = 2π / N of the voltages on the output windings 6, 7, 8 and 9 (Fig. 3, a).

The first function is realized by well-known methods of circuit theory and is interconnected with the second, which is reduced to determining the number of turns of the windings of the phase number converter [2].

This problem was solved in [3] for any N. Moreover, for N = 4, the relative number of turns of the input windings is: the first winding 10 w ₁ = (W ₁ / W ₀ ) = 0.118, the second winding 11 w ₂ = (W ₂ / W ₀ ) = - 0.118, third winding 12 w ₃ = (W ₃ / W ₀ ) = - 0.118, fourth winding 13 w ₄ = (W ₄ / W ₀ ) = 0.118, fifth winding 14 w ₅ = (W ₅ / W ₀ ) = 0.043, sixth winding 15 w ₆ = (W ₆ / W ₀ ) = 0.161, seventh winding 16 w ₇ = (W ₇ / W ₀ ) = - 0.043, eighth winding 17 w ₈ = (W ₈ / W ₀ ) = - 0.161, ninth winding 18 w ₉ = (W ₉ / W ₀ ) = 0.161, tenth winding 19 w ₁₀ = (W ₁₀ / W ₀ ) = - 0.143, eleventh winding 20 w ₁₁ = (W ₁₁ / W ₀ ) = 0.161 and the twelfth winding 21 w ₁₂ = (W ₁₂ / W ₀ ) = - 0.143, where W _n is the number of turns of the corresponding input winding p phase number converter, n = 1, 2, 3 ... 12 - winding number, W ₀ - number of turns specified based on the structural and overall dimensions of the magnetic circuits. The minus sign in front of the normalized value of the number of turns means counter inclusion. Similarly, using [3], the number of turns of the input windings is determined for other multiplicities of multiplication N.

To implement the phase number converter 1, standard and non-standard magnitude wires of various designs are used: rod, armor, twisted, toroidal and others. The advantages of cores of various designs are described in [4]. At each of these magnetic cores, both input windings and output and control windings are located.

The material of the magnetic cores is selected in such a way as to ensure minimal losses both at the input frequency f and the output frequency Nf. In the case of using frequency multipliers in power industrial plants, various electrical steel steels at frequencies up to two kilohertz can be used as a material. At higher frequencies, it is advisable to use ferrite magnetic cores. In this case, the losses in the magnetic circuits of the claimed device are significantly less, since they operate in a linear mode.

When the magnetic circuit operates in linear mode, the range of operating frequencies significantly increases. Therefore, using the inventive device, you can multiply both industrial frequencies and higher frequencies. At the same time, at higher frequencies, the dimensions of the cores are small, since the converted power is directly proportional to the frequency.

For the operation of the inventive device, it is necessary to select the optimal parameters of capacitors, transistors and semiconductor diodes.

The capacitance of the capacitors is selected by the reactive power accumulated in these elements and is determined by the ratio

where C is the capacitor rating; U is the amplitude of the voltage on its plates.

For optimal operation of the device, it is necessary that the reactive power (1) is several times higher than the active power released in the external load 25.

The parameters of the transistors used are selected according to the permissible collector currents I _{to additional} , collector-emitter voltages U _{to-additional} . In this case, the maximum current should not exceed I _{to extra} . The amplitude of the voltages at the transistors in the operating mode is approximately equal to the amplitude U and should be half as much as U _to-ext . In this case, it is necessary to choose a transistor with a minimum saturation resistance, which is given in the manuals, or is determined by the output static characteristics. The cutoff frequency of the transistors is selected from the condition to ensure low switching losses and should be an order of magnitude higher than the output frequency Nf.

The voltage amplitude between the control inputs of the transistors should be 1.5-2.5 V.

Semiconductor diodes are also selected for permissible forward current and reverse voltage.

When operating in the frequency range up to several megahertz and higher, there is a fairly large range of transistors and semiconductor diodes that provide conversion efficiency close to 100%.

The reduction in power loss in the inventive device is due to the following factors:

1) to multiply the frequency, circuits made up of a controlled key and a capacitor are used, which potentially have no losses;

2) only the function of converting the number of phases is entrusted to the magnetic circuits, due to which the ferromagnet operates without saturation (in linear mode) and, therefore, has small losses. In addition, the need for DC bias and self-biasing circuits with an intermediate frequency current has disappeared, which also accompanies a significant reduction in power losses.

The advantage of the claimed device should also include the fact that the capacitors used for multiplication also perform the functions of longitudinal compensation of the inductive resistance of the phase number converter, increasing the cos φ of the frequency multiplier.

One of the most promising fields of application of the proposed technical solution is oscillation sources with a frequency of 400 Hz, for which frequency multipliers of 50 Hz with a multiplicity of N = 8 can be used.

The inventive device can be used for multiplication and higher frequencies. For this purpose, there is a large range of cores [5], which in the linear mode have significantly lower losses compared to the known devices [1, 4], in which the cores of the magnetic cores operate in a nonlinear mode.

Thus, the inventive device has significant advantages compared with the known and meets the requirements of industrial feasibility.

INFORMATION SOURCES

1. A.S. 665378 (USSR). Ferromagnetic frequency multiplier an even number of times. / Yu.A. Aleksandrov, A.N. Bogachenkov, O.P. Novozhilov - Publ. 05/30/79. Bull. No. 20.

2. Novozhilov O.P. Ferromagnetic converters of the number of phases and frequencies. // Electricity. - 1985, No. 12, S. 49-51.

3. Novozhilov O.P. To the calculation of turns of ferromagnetic converters of the number of phases and frequency. // Electricity. - 1987, No. 1, P.57-59.

4. Ferromagnetic frequency multipliers. / A.M. Bamdas, I.V. Blinov, N.V. Zakharov and others; - M .: Energy. - 1968. from 147-148.

5. Sidorov I.N., Khristinin A.A., Skornyakov S.V. Small-sized magnetic cores and cores. - M .: Radio and communication. - 1989. - 384 p.

Claims (1)

The frequency multiplier is an even number of times N, containing a three-phase voltage converter into a symmetric system N of a phase voltage of N magnetic circuits with one output winding (BO) located on each of them and three input windings connected in series and connected to the outputs of an external three-phase sinusoidal voltage source, as well as the first and second output terminals, to which an external load is connected, while the first terminals of each VO are interconnected and connected to the first output terminal, The fact is that N controlled keys (CC), N control windings (CC), located one on each of N magnetic cores, and N capacitors (K) are introduced, while the first power terminals (CB) of each CC are connected to the second terminal , the control terminals of each UK are connected to the corresponding ends of each UO, the second CBs of each UK are connected to the first terminals of each K, and the second terminals of each K are connected to each other and connected to the second output terminal.

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