RU2469472C1 - Device for recovery of signal level in circuits with programmable switching - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: device includes pull-up P-channel transistors, inverter, 2AND-NOR logic element and inverting delay line. Inverter includes P-channel transistor and N-channel transistor. 2AND-NOR element includes P-channel transistors and N-channel transistors. Inverting delay line includes odd number of in-series connected inverters each of which consists of P-channel transistor and N-channel transistor.

EFFECT: reduction of switching delay time and increase in curvature of front edge of signal, enlargement of range of supply voltages, increase in limit frequency of circuit operability and increase in noise threshold.

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Description

The present invention relates to integrated electronic technology and can be used as part of programmable logic integrated circuits (FPGAs).

One of the features of FPGAs is the presence of several levels of interconnects that vary in length. Connections between conductors of different levels are made using programmable keys, the state of each of which (closed / open) is determined by the contents of the corresponding cell in the configuration memory. Thus, the contents of the FPGA configuration memory determines a specific connection between all the conductors, that is, the interconnect trace.

Potentially possible connections between the conductors of one level and the selected conductor of the other form a tree structure (multiplexer tree), in each branch of which there is a key, conductors of one level are connected to the inputs, and a conductor of another level is connected to the only output. After passing through a chain of keys (tree branches), the input signal is weakened, and therefore, buffering is required at the output, restoring the signal level. Thus, two related problems arise - the implementation of keys and signal level recovery devices (UVUS).

Previously, for the implementation of the keys, pairs of parallel-connected P- and N-channel transistors were used, at the sources of which an input signal was supplied, and the output was removed from the drains. At the same time, a conventional inverter was used as a UVUS, consisting of pull-up P-channel and pull-down N-channel transistors, the combined gates of which are the input of the inverter, and the combined drains are its output. Such a circuit, along with an obvious advantage - the multiplexer tree of this circuit conducts a signal without loss of potential, also has a number of drawbacks noted earlier. Firstly, it has twice the number of transistors compared to the number of keys, which leads to a corresponding increase in the area of the crystal, as well as stray capacitances and, as a consequence, to a deterioration of the time characteristics. Secondly, each of the control signals supplied to the gates of the key transistors should be represented as a pair of direct and inverted signals, which requires additional signal inversion and also leads to an increase in area.

In a well-known manner ([1] Jean M. Rabai, Ananta Chandrakasan, Borivrozh Nikolic. Digital integrated circuits. Design methodology. - M .: - Williams. - 2007. - P.338; [2] US patent No. US 2008/0265937 A1 "Level-restoring buffers for programmable interconnect circuits and method for building the same"; [3] US patent No. 5894227 "Level restoration circuit for pass logic devices") the solutions to these problems, shown in Fig.1, is to use a tree as keys multiplexers of pass-through N-channel transistors, which immediately halves the number of transistors in the tree and eliminates the need for inverting control ignalov. In addition, since the switching speed of N-channel transistors is higher than that of P-channel transistors, one should expect more high-speed FPGAs with such switching interconnects. However, the use of N-channel transistors leads to the fact that the output level of the logic "1" after passing through the chain of N-channel transistors of the multiplexer tree decreases compared to the supply voltage by the threshold voltage of these transistors. As a result, if a conventional inverter is used as the output buffer, the P-channel transistor of this inverter is not completely closed, that is, it is in a subthreshold state, which leads to a significant increase in the through current through the inverter. In addition, the noise threshold is significantly reduced.

Several methods are known for solving these problems.

1. The first, most widely used in FPGA, is that a feedback circuit is introduced for the output inverter, consisting of a pull-up P-channel transistor, the drain of which is connected to the inverter input, and the output voltage is applied to the gate ([1] - p. 345; [2, 3]). Such a circuit is shown in figure 2. This solution reduces static power consumption and is good for static and low-frequency modes. However, with increasing frequency, a problem arises related to the choice of the ratio between the length and width of the pull-up channel of a P-channel transistor. When switching the input signal from a logical zero state to a logical unit (leading edge), for a sufficiently fast switching, it is necessary that this transistor has a short channel with a relatively large width. To quickly switch the input signal from the state of a logical unit to a logical zero (trailing edge) pull-up, the P-channel transistor should have the inverse proportions - a long channel of small width. Therefore, it is necessary to choose one or another compromise in the proportions of the pull-up of the P-channel transistor, as a result of which the leading edge of the input signal is “overwhelmed”, that is, the voltage at the input of the UVUS increases at a low speed, striving for the supply voltage only to the limit. For this reason, the UVUS in FIG. 2 has a relatively small working area in terms of supply voltage, since with a decrease in the supply voltage, the inverter switching moment, determined by the achievement of the input voltage of the threshold voltage value, is more and more delayed. This, firstly, limits the bottom of the range of supply voltages, and secondly, limits the top maximum frequency of the circuit to work. These factors turn out to be very important, since it is the area of operability of the UVUS that most often limits the area of operability of FPGAs in general. In addition, during a period of slow increase in the input voltage of the UVUS, the noise threshold is significantly reduced.

2. You can also specify a group of methods that require a second voltage source for the implementation of the UVS: [4] US patent No. 4486670 "Monolitic CMOS low power digital level shifter"; [5] US patent No. 4958091 "CMOS voltage converter"; [6] US patent No. 5136190 "CMOS voltage level translator circuit". However, such approaches are technically complex, increase the area of the crystal, and contradict the general tendency to reduce energy consumption.

3. In [2], there are 12 options for the UVUS (one of the options is shown in Fig. 3), common to which is that between the output of the UVUS and the ground bus a set of N-channel transistors is included, which opens when the front edge of the input signal passes and attracts this output to ground level, after which a pull-up P-channel feedback transistor opens. Since the voltage that opens the N-channel transistors is supplied to the gates ahead of the corresponding switching at the input of the UVUS, this accelerates the switching of the input from the logical “0” state to the logical “1” state. When passing the trailing edge of the input signal, the output advances is disconnected from the ground level, and therefore, switching from a logical unit to a logical zero occurs in the usual manner, as for the circuit depicted in figure 2. However, the number of additional N-channel transistors of the circuit in Fig. 3 is proportional to the number of inputs of the multiplexer tree (or the number of its midpoints), which can be quite large (20 or more), so the additional area is significant. Real-life FPGAs do not always have intermediate buffers (Line Driver 171 in Fig. 3), therefore, on all top-level buses, even disabled by the corresponding SEL key, an additional load appears (transistor gates 238 in Fig. 3), which causes an increase in size drivers of these tires. Even if intermediate buffers (Line Driver 171 in FIG. 3) are present, their sizes must be increased to switch the additional load mentioned above. In both cases, the crystal area and dynamic power consumption increase. Finally, the additional load in the form of gates of transistors 232, 233 in FIG. 3 appears on the SEL signal drivers, necessitating an increase in the area and power consumption of these drivers. Thus, in general, the circuit in Fig. 3 is very expensive in area and with increased power consumption, since the decrease in power consumption of the output UVUS inverter is excessively compensated by the increased power consumption of the drivers.

4. Figure 4 shows the UVUS circuit from the patent [3], the feature of which is the series connection between the power and ground buses of the pull-up of the P-channel transistor 100 and the pull-down of the P-channel transistor 90. However, the input signal level In is in a state logical “1” due to the passage of the chain of N-channel transistors of the tree of multiplexers decreases compared with the supply voltage by the threshold voltage of these transistors. As a result, the pull-down P-channel transistor 90 may not be completely closed, that is, in a subthreshold state, while the pull-up of the P-channel transistor 100 connected in series with it at that time is completely open. This leads to a significant increase in the through current through these transistors and increasing energy consumption. In addition, the noise threshold is significantly reduced.

The prototype of the present invention is a standard UVUS, a diagram of which is depicted in figure 2.

The inventive UVUS, the circuit of which is shown in Fig. 5, contains the full set of components available in the standard UVUS in Fig. 2: pull-up P-channel transistor 10, the drain of which is connected to the In input of the UVUS, and the output signal Out is supplied to the gate. The input In of the UVUS is also connected to the input of the inverter 20, consisting of a pull-up of the P-channel transistor 21 and a pull-down of the N-channel transistor 22, the combined gates of which are the input of the inverter, and the combined drains are its output, which is also the output Out of the UVUS. Additionally, the claimed UVUS contains a P-channel transistor 30 connected in parallel with the pull-up transistor 10, the drain of which is also connected to the UVS input In, and the gate is controlled by the output signal of the 2I-NOT 40 logic element formed by pull-up by the P-channel transistors 41 and 42, pull-down by an N-channel transistor 44 and an N-channel transistor 43, the source of which is connected to the drain of the N-channel transistor 44. The combined drains of the transistors 41, 42 and 43 are the output of the 2I-NOT 40 element, the gates of the transistors 41 and 43 are combined and form first input element 2I-N E 50, which is connected to the input In of the UVUS, the gates of the transistors 42 and 44 are also combined and form the second input of the element 2I-NOT 40, which is connected to the input In of the UVUS through an inverting delay line (ILS) 50, consisting of an odd number of inverters connected in series. Each of these inverters consists of a pull-up of the P-channel transistor 51 and a pull-down of the N-channel transistor 52, the combined gates of which are the input of the inverter, and the combined drains are its output. The input of the first inverter, which is the input of ILZ 50, is connected to the input In of UVUS, the output of the last inverter, which is the output of ILZ 50, is connected to the second input of element 2I-NOT 40.

The main objective of this invention is to expand the field of health of the UVUS on the supply voltage and frequency.

The technical result when using the present invention is to reduce the switching delay time and increase the steepness of the leading edge of the signal, reduce the lower limit of the allowable range of supply voltages, increase the maximum maximum frequency of the circuit's operation and increase the noise threshold.

The invention is illustrated by the following graphic materials.

Figure 1. The output stage of the tree of multiplexers with keys on the pass-through N-channel transistors and the output inverter.

Figure 2. Scheme of a standard UVUS with a pull-up P-channel transistor.

Figure 3. Scheme of one of the twelve UVUS patent [2].

Figure 4. Scheme UVUS patent [3].

Figure 5. Scheme of the proposed UVUS.

6. A chain of open N-channel transistors for simulating the passage of a signal through open branches of a tree of multiplexers.

7. The graph of the input voltage at the input of the Input circuit of Fig.6 from time to time.

Fig. 8. Graphs of the voltage at the input In of the UVUS from time to time at a supply voltage of 1.8 V, where Vin1 is for the inventive UVUS, Vin2 is for the UVUS in Fig.2.

Fig.9. The graph of the voltage at the output of the 2I-NOT 50 element versus time with a supply voltage of 1.8 V.

Figure 10. Graphs of the dependence of the voltage at the output Out of the UVUS from time to time at a supply voltage of 1.8 V, where Vout1 is for the inventive UVUS, Vout2 is for the UVUS in Fig.2.

11. Graphs of the voltage at the input In of the UVUS from time to time at a supply voltage of 1.44 V, where Vin3 is for the inventive UVUS, Vin4 is for the UVUS in Fig.2.

Fig. 12. Graphs of the dependence of the voltage at the output Out of UVUS from time to time at a supply voltage of 1.44 V, where Vout3 is for the inventive UVUS, Vout4 is for UVUS in Fig.2.

The invention is carried out as follows.

In a stationary state, when a logic level signal “0” or logic “1” is applied to the In input, the input signal is supplied to the first input of the 2I-NOT 40 element, and the inverse signal to the second through an odd number of inverters ILZ 50, resulting in the output of the 2I-NOT 40 element in the stationary state is always in the state of the logical 1 level. Since the signal from the output of the 2I-NOT 40 element is supplied to the pull-up gate of the P-channel transistor 30 (see Fig. 5), this transistor is closed and does not affect the state of the input and output of the circuit. Thus, in a stationary state, the claimed invention works in fact as a standard circuit in figure 2. When the input In is in the ground level state, the output voltage is inverted to the output Out through the inverter 20, and the voltage level signal is inverse to it, which locks the transistor 10 through the feedback circuit, thereby disconnecting the input In from the power bus. When the input In is in the state of a logical unit, the input In actually, after passing through the chain of N-channel transistors of the multiplexer tree, receives a voltage that is reduced compared to the supply voltage by the threshold voltage of these transistors. However, the output Out through the inverter 20 receives a ground level signal, which through the feedback circuit opens the transistor 10 and restores the level of the input signal In to the level of the supply voltage.

Consider now the operation of the circuit in dynamic mode. When the input In is in the logical “0” state, the first and second inputs of the 2I-NOT 40 element are in the logical “0” and “1” states, respectively, and its output is in the logical “1” state, holding the P-channel pull-up transistor 30 is locked. When the input In of the UVUS is switched from the logical “0” state to the logical “1” state, that is, when the leading edge of the input signal passes, this signal immediately arrives at the first input of 2I-NOT 40 element. Since the signal from the input goes to the second input of this element In comes through ILZ 50, consisting of an odd number of inverters, then for a certain period of time at this input the previous state of logical “1” is maintained. Thus, during the delay time of the ILZ 50 after passing the leading edge at both inputs of the 2I-NOT 40 element, logical 1 states are established, thereby forming an earth level signal at its output, which is fed to the pull-up gate of the P-channel transistor 30 and opens this transistor. As a result, the potential of the power bus through this open transistor is fed to the In input of the UVUS and restores it to the level of the power bus. This process is much faster than for the circuit in figure 2, since the transistor 30 is connected in parallel with the transistor 10 and there are no restrictions on the dimensions of the P-channel transistor 30, i.e. its channel can be selected short and wide, so that the transistor 30 switches very quickly. After the inverted signal from the input In through ILS 50 reaches the second input of the 2I-NOT 40 element, the logical level “0” will be established at this input, which will lead to the logical “1” state at the output of this element, which will again close the P-channel transistor 30. In the future, the supply voltage level at the input In is supported by the P-channel transistor 10, which has opened up to this point. Thus, the steepness of the leading edge of the signal increases when using this DCS, and the switching delay time decreases.

Just before the trailing edge passes through the In input, the latter is in the logical 1 state, the first and second inputs of the 2I-NOT 40 element are in the logical 1 and 0 states, respectively, and its output is in the logical 1 state, holding the pull-up P-channel transistor 30 in a locked state. When the input In of the UVUS is switched from the logical “1” state to the logical “0” state, that is, when the trailing edge of the input signal passes, this logical “0” signal immediately arrives at the first input of the 2I-NOT 40 element and continues to hold it at the element output 2I-NOT 40 state of logical "1" even after receipt through ILZ 50 to the second input of element 2I-NOT 40 of the logical "1" signal. Thus, when passing a trailing edge at the output of the 2I-NOT 40 element, the logical “1” state and, therefore, the closed pull-up state of the P-channel transistor 30 is saved. Pull-up P-channel transistor 10, the gate of which is connected to the input In through the inverter 20, it is also locked, thereby disconnecting the In input from the power bus, after which the logical state “1” is set to In, and the logical “0” state is set to Out.

Thus, the additional transistor 30 is open only when the input In UVS is switched from the logical “0” state to the logical “1” state for a period of time determined by the signal delay in the ILS 50. The speed of this switching (slope) is determined mainly by pull-up parameters P-channel transistor 30, the channel of which can be selected short and wide to ensure maximum slope. Since the pull-up P-channel transistor 10 plays an auxiliary role, the need for the above compromise in choosing the proportions of its channel disappears, and the pull-up dimensions of the P-channel transistor 10 should be chosen so as to ensure the maximum slope of the trailing edge determined by this transistor , that is, choose the maximum length of the channel with its minimum width.

When passing the leading edge of the input signal, the switching moment of the UVUS inverter in figure 2 is determined by the achievement of the voltage at the input of the threshold voltage of this inverter. Since with a decrease in the supply voltage, the voltage rise rate at the input of the UVUS decreases, the switching of the UVUS in Fig. 2 will be more and more delayed until the loss of operability at a certain minimum supply voltage. Since the inventive UVUS switches much faster, this means that it will maintain its operability at substantially lower voltages, that is, it has a wider range of operability in terms of supply voltage compared to UVUS in figure 2. In addition, since the claimed UVUS has a higher slew rate of the input voltage, it has a higher noise threshold.

Since the claimed invention provides a significantly higher slope and a smaller delay of switching the leading edge while maintaining the steepness and a slight increase in the delay of the trailing edge, this leads to an increase in the maximum maximum frequency of the circuit.

The possibility of carrying out the invention is also confirmed by the simulation results of this UVUS performed in the Cadence Specter Simulator for 180 nm CMOS technology, a nominal supply voltage of 1.8 V, a temperature of 25 ° C and an inverting delay line containing three inverters. The results were compared with the corresponding data for UVUS, a diagram of which is shown in figure 2. The sequence of open branches of the multiplexer tree was modeled by a chain consisting of four series-connected open N-channel transistors, shown in Fig.6. The output O of this chain was connected to the In input of the inventive UVUS during its modeling or to the In input of the UVUS in Fig. 2 when modeling the latter, the signal generated by the preliminary buffers was fed to the input of the chain, the form of which is shown in Fig. 7. After passing through the chain, the voltage at the input of the UVUS has the form shown in Fig. 8, where Vin1 is the dependence of the input voltage on time for the inventive UVUS, Vin2 is for the UVUS in Fig.2. As can be seen from Fig. 8, when switching from a logical “0” state to a logical “1” state, the voltage Vin2 at the UVUS input in FIG. 2 recovers very slowly and does not reach the supply voltage level until the input switches to the logical “0” state, that is, throughout this entire period of time, a current flows through the pull-up P-channel transistor, and the circuit has a significantly reduced noise threshold. The voltage Vin1 at the input of the inventive UVUS at the initial interval for about 0.2 ns after the start of switching behaves like Vin2, that is, it increases very slowly. However, after the output of the 2I-NOT 40 element for a short period of time, the logic state voltage “0” is set (see Fig. 9), which enters the pull-up gate of the P-channel transistor 30 and opens this transistor, voltage Vin1 quickly increases and restores its level to the level of supply voltage. The characteristic point in time at which the transistor 30 opens is determined by the inflection point on the curve Vin1.

Figure 10 shows graphs of the voltage at the output Out of UVUS from time: Vout1 - for the inventive UVUS, Vout2 - for UVUS in figure 2. As can be seen from Fig. 10, due to the faster restoration of the level of Vin1 compared to Vin2, the leading edge of Vout1 has a significantly greater slope compared to Vout2, the leading and trailing edges of Vout1 are almost symmetrical, while Vout2 is significantly asymmetric. This provides an increase in the maximum maximum frequency of the circuit.

In Fig.11 and Fig.12 shows the simulation results of the UVUS for the supply voltage, reduced relative to the nominal by 20% (1.44 V) while maintaining the remaining parameters. As expected, the voltage at the input of the inventive UVUS (Vin3) grows much faster than the voltage at the input of the UVUS in Fig. 2 (Vin4), which leads to a steeper leading edge of the output voltage (Vout3) compared to the “lit up” leading edge of Vout4 and less switching delay. However, the UVUS in figure 2 remains operational, although the duty cycle of the signal has deteriorated significantly. The simulation showed that a further decrease in the supply voltage to a value of 70% relative to the nominal (1.26 V) leads to the fact that the UVUS in figure 2 does not have time to switch, that is, it loses its functionality, while the claimed UVUS retains its efficiency while maintaining the steepness of the fronts output signal but increased switching delay.

The energy level of the claimed UVUS is generally comparable with the energy consumption of the prototype, since the gain due to an increase in the steepness of the signals is compensated by the loss due to switching of additional circuit elements - 2I-NOT 40 and ILZ 50.

Claims (3)

1. A signal level recovery device having one input and one output, containing a P-channel transistor connected by a source to the power bus, the drain of which is connected to the device input, and the gate to the device output, and connected to the device input and output to the device output an inverter, consisting of a P-channel transistor connected by a source to a power bus and an N-channel transistor connected by a source to a ground bus, whose connected gates are the inverter input, the connected drains are the inverter output, different characterized in that the device further comprises a P-channel transistor connected by a source to the power bus, the drain of which is connected to the device input, a 2I-NOT logic element having two inputs and one output, and an inverting delay line having one input and one output, output logic element 2AND is NOT connected to the gate of an additional P-channel transistor, the first input of logic gate 2AND is NOT connected to the input of the device, the second input of logic gate 2AND is NOT connected to the output of the inverting delay line, the input is inverting second delay line connected to the input device. 2. The device according to claim 1, the logical element 2 AND NOT which has two inputs and one output and contains the first and second P-channel transistors, the sources of which are connected to the power bus, the first N-channel transistor, the source of which is connected to the ground bus, and a second N-channel transistor, the source of which is connected to the drain of the first N-channel transistor, the connected drains of both P-channel transistors and the second N-channel transistor are the output of the 2I-NOT element, the gates of the first P-channel transistor and the second N-channel transistor conjunction veins and form the first input of the 2I-NOT element, the gates of the second P-channel transistor and the first N-channel transistor are connected and form the second input of the 2I-NOT element. 3. The device according to claim 1, the inverting delay line of which has one input and one output and contains an odd number of series-connected inverters, each of which consists of a P-channel transistor connected by a source to the power bus and an N-channel transistor connected by a source to the earth bus whose connected gates are the input of the inverter, the connected drains - the output of the inverter, the input of the first inverter is the input of the inverting delay line, the output of the last inverter is the output of the inverting delay line ki.

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