RU2469289C1 - Aircraft wing strength control device - Google Patents

Abstract

FIELD: transport.

SUBSTANCE: proposed device comprises three vibration transducers located at center of gravity and left and right outer wings, analog signal switch, ADC, three parallel registers, two adders, two operating memories, address modification counter and control unit. In compliance with this invention, added are address modification counter control device, microcomputer, unit of buffer registers and onboard flight parameters recorder. Note here that outputs of memories are connected to microcomputer 1^st and 2^nd inputs. Microcomputer 3^rd input made a data input of "start" signal while 2^nd input is connected to second input of address modification counter control device first input of which makes data input of signal "Manual reset". Said 3^rd input is connected with third inputs of memories fourth inputs of which are connected to first input of address modification counter control device with its 2^nd input connected to address modification counter.

EFFECT: higher validity of control.

11 dwg

Description

The invention relates to devices for studying the strength properties of structures, in particular, aircraft wings, and can be used to control its strength by measuring the vibration of the wing console directly in flight.

Known vibration meter IV-200, which provides continuous monitoring of the vibration speed of the engine and gives signals of increased and dangerous vibration in cases when its value is exceeded above the established norm [Vorobev V.G. etc. Aviation devices, information-measuring systems and complexes. Textbook for high schools / V.G. Vorobyov. - M .: Transport, 1992. - P.104-108] [1].

The main disadvantage of its application is that, depending on the modification, the IV-200 measures either the level of vibration or the vibration speed of the bearings of the rotor machine. A change in these indicators is a sign of aircraft engine failure and precedes its destruction.

The strength of the wing cannot be estimated through an indicator of the speed of vibration, since even when the stiffness of the wing decreases to a critical value, the speed of vibration depends only on external disturbing factors. In addition, the IV-200 solves the problem of controlling an aircraft engine in flight, while based on the assessment of wing stiffness, the problem of the possibility of allowing the aircraft to enter the next flight should be solved. Thus, the operation algorithm on which the IV-200 is based does not allow solving the problem of assessing wing stiffness.

The closest solution to the proposed is a control system of the strength properties of the wing of the aircraft, designed to measure vibrations at the ends of the left and right wings [Control system of the strength properties of the wing of the aircraft. Kashkovsky V.V., Ustinov V.V. Poluektov S.P. Zheltukhin S.N. RF patent No. 2348916, dated 10.03.2009] [2].

For this, it was proposed to install two additional accelerometers that allow recording on the flight site from t ₁ to t ₁ + T _sc , for subsequent processing on the ground of two acceleration signals, respectively, of the left and right wing:

и

,

and

,

where T is the sampling period; T _sc - the duration of the recording device;

- число точек измерения.

- the number of measurement points.

с сумматора 9 и

с сумматора 10,

в запоминающие устройства 11 и 12; на фиг.2 - схема устройства управления.Figure 1 presents a block diagram of a prototype signal recording system

from adder 9 and

from adder 10,

to storage devices 11 and 12; figure 2 is a diagram of a control device.

The system includes three vibration sensors 1, 2 and 3, an analog signal switch 4 for connecting sensors to an analog-to-digital converter, an analog-to-digital converter 5, three parallel registers 6, 7 and 8, two adders 9 and 10, two random access memory devices 11 and 12, a control device 13, and an address modification counter 14.

Vibration sensors 1, 2, and 3 are standard aviation accelerometers of the MP-95 type used in on-board flight parameter recorders of the Tester U-3 type and are described in the technical description of this system and in the literature [1, 3].

An analog-to-digital converter 4, information reception and transmission registers 6, 7, 8, adders 9 and 10, storage devices 11 and 12 are serial devices and are described in the literature [4].

The control device 13 is shown in FIG. 2 and consists of a rectangular pulse generator 18, a two-bit counter 16 with a control circuit 15, and a decoder 17.

The analog signal switch 4 and the rectangular pulse generator 18 are typical devices used in microprocessor technology and, in particular, in on-board recording devices of the Tester U-3 type [4, 5]. The rectangular pulses of the generator 18 are continuously supplied to the counter 16 from the moment of supplying power to the device. The control circuit 15 is implemented on typical logical elements AND NOT [4]. As pulses arrive, the counter 16 cyclically generates a repeating sequence of code combinations: 00, 01, 10 and 11 from the moment the device is put into operation by a combination of signals “Chassis removed” and “Flaps removed” or a signal “Manual start”. The counter 16 is stopped by the overflow signal of the address modification counter - the “Stop” signal. Depending on the current value of the code combination at the output of the counter 16 from the output of the decoder 17 in the ADC 5 receives one of the control signals S1-S4. A counter and a decoder are also typical products used in electronic technology [4, 5].

Counter modification address 14 is similar to the counter 16 of the control device and differs only in the number of bits. The number of bits of the counter modification address 14 is equal to the number of bits of the bus address of the storage devices 11 and 12.

The system for recording onboard readings of vibration sensors 1, 2, 3 only works when climbing and is started up with constant logic signals: “Chassis removed”, “Flaps removed”. The system solves the algorithm in a cycle and writes the results to the memory 11 and 12 in a discrete form with a period T. After filling the memory 11, 12, the signal "Address Modification Counter Overflow" passes and the system stops. On the ground, the calculation is carried out according to the algorithms given in the prototype and the estimate of Ω and _1l and Ω and _{1p is determined} . Evaluation results are accumulated in a multitude in the service group of objective control tools for a statistical assessment of the decrease in the bending stiffness of the wing during operation. Before the flight, the system is alerted by the "Manual reset" signal. To test the operability on the ground, the system can be forced to start working with the signal "Manual start".

The prototype assumes that after the flight, the data of the storage devices 11 and 12 are overwritten for subsequent processing in a ground computer. Modern passenger and transport aircraft carry out permanent or charter flights with numerous landings at intermediate airfields. When landing at intermediate aerodromes, it is impossible to rewrite information about wing stiffness of the database of the airfield. Therefore, the disadvantage of the invention is the inability to control the stiffness of the wing outside the base airfield.

The technical result of the proposed device is to increase the reliability of the control of the strength properties of the wing of the aircraft outside the base airfield to prevent the destruction of the wing in flight. This is achieved using standard aircraft equipment. In flight, the first wing tone is measured to assess bending stiffness and, when critical wear of the wing structure is achieved, the aircraft is prevented from flying.

The technical result is achieved by the fact that in the device for controlling the strength of an aircraft wing, which contains three vibration sensors, an analog signal switch, an analog-to-digital converter, three parallel registers, two adders, two random access memory devices, an address modification counter and a control device, and vibration sensors through a switch connected to the first input of an analog-to-digital converter, the output of which is directly connected to the first inputs of the registers, the output of the first register is connected to the input of the first adder, the output of the third register with the first input of the second adder, and the output of the second register with the second inputs of the adders, the outputs of which are connected to the first inputs of the storage devices, the second inputs of which are connected to the counter of the address modification, and the output is turned on to their third inputs a control device that is simultaneously connected to the second inputs of the registers and the analog-to-digital converter, as well as to the fourth input of the switch, while the three information inputs of the control device are connected to by the logic elements “Chassis removed”, “Flaps removed” and the “Manual start” signal, and the fourth input of the control device is connected to the output of the address modification counter, an additional control device for the address modification counter, a microcomputer, a block of buffer registers and an on-board device for recording flight parameters are additionally introduced moreover, the outputs of the storage devices are included on the first and second inputs of the microcomputer, its third input serves as the information input of the Start command, and the second output is connected to the second input of the device controlling the address modification counter, the first input of which serves as the information input of the Manual Reset command, and the third input is connected to the third inputs of the storage devices, whose fourth inputs are connected to the first output of the address modification counter control device, the second output of which is connected to the address modification counter.

The essence of the invention is illustrated by the drawings presented in figure 3 and figure 2, showing the structure of the control device 13. In the drawings, the following notation:

1, 2, 3 - vibration sensors;

4 - switch analog signals;

5 - analog-to-digital Converter;

6, 7, 8 - three parallel registers;

9, 10 - two adders;

11, 12 - two random access memory devices;

13 - control device;

14 - counter modification address;

15 is a control diagram;

16 - two-digit counter;

17 - decoder;

18 - generator of rectangular pulses;

19 is a control device counter address modification;

20 - microcomputer;

21 - block buffer registers;

22 - on-board device for recording flight parameters.

The operation of the inventive device in flight does not differ from the operation of the prototype device.

On the ground, on the basis of the “Start” command, a program is launched in a specialized microcomputer 20.

After the start of operation, the microcomputer 20 programmatically sends a signal "Reset" to the control device counter address modification 19. This signal is reset counter modification address 19 to the initial value k = 0.

и

.At the start address of the counter modification address 19, the storage device 11 and 12 select the first value of the measured signals

and

.

и

одно за другим считываются в микроЭВМ 20 для обработки по алгоритмам, приведенным в формулах 1-13.Software Measured Signals

and

one after another are read in the microcomputer 20 for processing according to the algorithms given in formulas 1-13.

A signal S1 is supplied from the microcomputer 20 programmatically, along the trailing edge of which the address is modified in counter 14 (the address code increases k = k + 1).

и

по адресу k=1.Storage devices 11 and 12 select the values of the measured signals

and

at k = 1.

и

одно за другим считываются в микроЭВМ 20 для обработки по заданным алгоритмам (формулы 1-13).Software Measured Signals

and

one after the other are read in the microcomputer 20 for processing according to the specified algorithms (formulas 1-13).

After this, the reading cycle is repeated until the processing of information at k = N is completed.

The values of the frequency of natural vibrations Ω and _1l and Ω and _1n , calculated in the microcomputer 20, are recorded in the block buffer registers 21.

From the block of buffer registers 21, the values of Ω and _1l and Ω and _{1p are} recorded in the on-board recorder 22 for accumulation.

On the ground, the accumulated values of Ω _u1l and Ω _u1p from the on-board recorder 22 are _transferred to the aircraft database, which can be implemented on ground-based flight information processing devices of the “Topaz” type.

Microcomputer 20 can be implemented on various components. As an example, consider a microcomputer based on a microprocessor-based integrated circuit kit series KR580. This microcomputer is built on a modular basis. A typical circuit diagram of a microprocessor system based on microchips of this series is shown in [5]. Since the microcomputer 20 is designed to execute only one specialized calculation program, its design can be simplified by eliminating direct memory access nodes and interrupts. The structural diagram of the microcomputer is shown in figure 4.

The composition of the set of modules necessary for building a microcomputer includes [6]:

- central processor module;

- a memory module designed to store data and programs;

- an input-output module for interfacing a microcomputer with external devices.

All modules are connected using a single bus system: data bus (ШД), address bus (ША) and control bus (ШУ).

The data bus is a bi-directional bus through which data is exchanged.

The address bus is a unidirectional bus and is used to transmit addresses.

The control bus, combining a certain number of control signal transmission lines, is a bus whose signals determine the operating modes of the memory and external device. Additionally, the control bus can perform the functions of issuing interrupt enable signals and receiving interrupt requests, receiving a bus capture signal and issuing a bus capture confirmation signal for direct memory access, etc.

The central processor module is based on a microprocessor. For its operation, it is necessary to additionally connect external circuits for generating synchronization signals and control signals for interfacing with system buses.

The synchronization circuit (clock generator) provides the formation of two sequences of clock pulses with the necessary time and amplitude parameters, which are fed to the inputs F1 and Ф2 of the microprocessor, and are also used for gating external circuits;

generating a RESET signal, synchronization of ready signals, etc. As a clock generator, a special microcircuit is used, which is part of the microprocessor set of integrated circuits.

Coordination of the internal tires of the microprocessor with the system buses of the microcomputer is provided by the bus driver, which is part of the microprocessor kit (MPC). This is necessary for the stable operation of the entire system, since the connection of memory modules and external devices increases the load on the internal buses and can reduce the signal levels necessary for operation.

The formation of control signals is provided by a special system controller, which is part of the IPC (KR580VK28 [5]). The system controller generates control signals based on the status byte issued by the microprocessor to the data bus in the first cycle of machine cycles, and the RF and CT microprocessor signals. The scheme for generating control signals by the system controller is shown in FIG. 5.

According to the RPR signal, the status byte from the data bus is recorded in the status register of the system controller. The code at the output of the status register is decrypted and used to generate control signals (Table 1).

,

,

и

, как видно из схемы, формируются на основе сигналов с микропроцессора и схемы синхронизации. В формировании этих сигналов используются также значения таких разрядов байта состояния как «ВВОД», «ВЫВОД», «ППР», «ЧТП» и «

» (см. табл.1). Сигнал ППР предназначен для разрешения ввода команды прерывания RSTn с шины данных, поступающий с модуля ввода-вывода.Inverse signals

,

,

and

, as can be seen from the circuit, are formed on the basis of signals from the microprocessor and the synchronization circuit. In the formation of these signals, the values of such bits of the status byte as “INPUT”, “OUTPUT”, “PPR”, “NTP”, and “

"(See table 1). The PPR signal is intended to allow the input of the RSTn interrupt command from the data bus coming from the input-output module.

The memory module consists of read-only memory devices (ROM) and random access memory (RAM), for which the microcomputer uses a single address space, divided into the address area of access to the ROM and the address area of access to RAM.

To build a memory module, microcircuits are used that are not part of the microprocessor set of integrated circuits, but have common input and output parameters with it.

The input-output module includes a group of input-output ports, which are either registers with control logic circuits or special input-output interface devices in the form of LSIs containing internal input-output ports. Each external device is connected to one or more ports, and the external device is selected by selecting the corresponding ports.

From the point of view of the central processor, memory and input-output ports can be considered as a collection of random access memory cells. The microprocessor provides the address of the memory and input-output (BB) port on the shared address bus. Separation of memory addresses and input-output ports in a microcomputer can be done in two ways.

Table 1 Status Byte Structure Data Bus Level Status signal Description D0 PPR interrupt confirmation PPR = 1 indicates the readiness of the processor to process the interrupt request D1

Record - Output

= 0 indicates that the Write to Memory or Output

= 1 indicates the execution of the READ MEMORY or ENTER cycles D2 STACK STACK = 1 indicates that the contents of the stack pointer are on the address bus D3 Post Stop Confirmation POST = 1 indicates that the processor is in the STOP state (HLT command is running)

D4 OUTPUT OUTPUT = 1 indicates that the address bus is the address of an external device to which information is output (OUTPUT cycle) D5 M1 M1 = 1 indicates that the first command cycle is running (SELECTION cycle) D6 Enter ENTER = 1 indicates that on the address bus is the address of the external device from which information is input (ENTER cycle) D7 Read ChTP memory NTP = 1 indicates that the data bus will be used to read data from memory

The first way is to separately address memory and ports. The area of memory addresses in this case is maximum and is determined by the length of the address word. With an address word equal to two bytes (16 bits), the addressable memory is 64 kbytes. In case of separate addressing, the address word in I / O commands is one byte (8 bits). In this case, the number of addressable I / O ports is 256. Using the first method, you can save a total memory capacity of 64 kbytes, but to access external devices, you only need to use the I / O commands IN port and OUT port. A complete system of instructions for microcomputers is given in [6].

The second way is to use a common field for addressing memory and BB ports. This allows you to increase the flexibility and performance of the system, but it reduces the addressable memory space.

Separation of addresses to the memory and to the explosive ports is carried out by setting to 0 or 1 bit A15 on the address bus and is carried out by read and write signals. In addition, separate read and write signals are generated for the contents of the memory cells of the I / O ports. In this case, the explosive ports are considered as memory cells in the general address field. If the address category A15 = 0, then the memory is addressed, if A15 = 1, then the external device is addressed. With this method of addressing with a common address field, the amount of addressable memory and explosive ports is 32 kbytes each. The address area 0000-7FFF is used for addressing to memory, and 1000-FFFF is used for addressing to ports. A feature of this method is the ability to use all memory access commands to work with external devices.

For example, using the MOV r, M command, you can enter the contents of a port indirectly addressed by a register pair HL into any microprocessor register. If the IN port command is used, then the contents of the port can only be entered into the accumulator register A, followed by the transfer by the MOV r1, r2 command from register A to any other register.

Using the MVI M command, data8, you can directly write data to any indirectly addressed port.

For a number of reasons, the second method is preferable. So, for example, with general addressing, it is possible to perform arithmetic and logical operations on the contents of the BB and battery ports, if commands with indirect addressing to memory are used. For example, in case of separate addressing, to add the contents of the port and the battery, it is first necessary to save the contents of the battery in some register (command MOA g, A), then enter the contents of the port into the battery (IN port) and execute the ADD addition command. When using the common field addressing this operation can be performed with the command ADD M.

The I / O module also includes:

- various interface schemes for interfacing with external devices, the exchange of information with which is carried out in parallel or serial code; in IPC for these purposes special LSIs are used for programmable parallel and serial interfaces;

- LSI programmable interrupt controller for receiving and processing interrupt requests from external devices and generating a priority request signal (ZPR), received at the input of the microprocessor;

- LSI programmable timer for time interruptions;

- LSI programmable controller of direct access to memory for organizing the exchange of data between RAM and an external device.

The microcomputer of the proposed device should include two modules of programmable parallel interfaces КР580ВВ55А [6]. One for connecting storage devices 11 and 12, the second for connecting a block of buffer registers 21.

The connection structure of the programmable parallel interface with the storage devices 11 and 12 is shown in Fig.6.

The connection structure of the programmable parallel interface with the block of buffer registers 21 is shown in Fig.7.

The programmable parallel interface is a multifunctional device and is used for bi-directional transmission of data and control signals between the central processor and external devices. Information about the readiness of external devices for data exchange enters the processor, usually by interrupt signals. When exchanging data, the processor can access external devices as memory cells or as input-output devices (I / O).

The programmable parallel interface consists of three communication channels A, B, and C, which are 8-bit BB ports with different characteristics. The direction of exchange and the operation mode of each channel are set programmatically. Channels are used to transmit data and control signals. Simplified device diagram can be considered as a combination of registers: a control register and three registers designed for input-output data.

The circuit in FIGS. 6 and 7 includes the following functional units:

- data bus buffer (BFD);

- read-write control node;

- ports B-B A, B and C.

The bus, data buffer (BFD) is designed to connect the internal data bus to the system bus. Connection is made using the terminals D7, D6, D5, D4, D3, D2, D1, D0. Information is transmitted through the BFD by microprocessor commands. In this case, three types of information can be transmitted: data bytes, control words and status information.

The read-write control circuit manages all internal and external transfers of data, control words, and status words. The control occurs under the influence of signals that arrive at the control pins and the addressing circuit:

- вход, на который поступает сигнал низкого уровня выборки устройства; формируется на выходе системного дешифратора, при дешифрации разрядов А15-А2 адреса;

- the input to which a signal of a low level sampling of the device; it is formed at the output of the system decoder, when deciphering bits A15-A2 addresses;

- вход сигнала низкого уровня, разрешающего передачу данных или слова состояния на системную шину данных;

- input signal low level, allowing the transfer of data or status word to the system data bus;

- вход сигнала записи низкого уровня, разрешающего прием данных или управляющего слова с системной шины данных;

- input signal recording low level, allowing the reception of data or control words from the system data bus;

A0, A1 - the input signals of the selection of one of the ports BB (A, B or C) or the control word register and is connected to the least significant bits of the address bus;

SET - the input of the reset signal, which sets all internal registers to zero; all ports go into input mode.

и

подключаются к линиям

и

системной шины управления. При обращении к портам как ячейкам памяти входы должны соответственно быть подключены к линиям

и

системной шины управления микроЭВМ.If the processor accesses the BB ports as external devices, the inputs

and

connect to lines

and

system bus control. When accessing ports as memory cells, the inputs must be connected to the lines accordingly.

and

microcomputer system control bus.

The type of information exchange between the data bus and BB ports, depending on the values of the indicated signals, is given in Table 2.

The control circuits of bus groups A and B are intended for receiving and storing a control word and setting the operating mode of ports of the BB device.

The control circuit of group A sets the operating mode of port A and the high bits of port C, and the control circuit of group B determines the operating mode of port B and the low bits of port C. The control word register is used to receive and store the control word received through the buffer data buses and internal bus.

table 2 Type of information exchange between data bus and BB ports

A0 A1 Direction of exchange and type of operation 0 one 0 0 0 Writing Data to Port A 0 one 0 0 one Writing data to port B 0 one 0 one 0 Writing data to port C 0 one 0 one one Control word record 0 0 one 0 0 Reading Port A 0 0 one 0 one Reading Port B 0 0 one one 0 Reading Port C one x x x x Shutdown

The BB ports are for connecting external BB devices. Connection is carried out using the conclusions of the corresponding channels: for channel A, the conclusions of KA7 ... KA0 are used; for channel B - conclusions КВ7 ... КВ0; for channel C - conclusions KS7 ... KS0.

Port A includes 8-bit input and output registers for input and output data in all operating modes of the circuit.

Port B consists of a single 8-bit register used to input and output data in two of the three possible modes of operation of the circuit.

Port C consists of two 4-bit registers that can be used to input and output 4-bit data or to receive and issue control exchange signals. In register C, a status word of the circuit is formed.

The port operating modes are set during initial installation by writing a control word to the control word register. At the same time, ports A, B and C are installed in one of three operating modes: mode 0, mode 1 and mode 2.

Operating modes can be set anywhere in the program execution, which allows serving various external devices with one interface in any order.

In mode 0, asynchronous data is exchanged over two 8-bit channels A and B and two 4-bit subchannels C without control signals that external devices are ready for operation and without confirmation of the possibility of exchange. This means that the data output from the microprocessor by the output commands are recorded in the respective channel registers, and then transmitted via communication lines to external devices.

Data is stored in registers until the end of the output command, after which the information in the ports is updated. When entering data is read from the ports and entered into the register - the microprocessor battery by input commands. Mode 0 is typically used to enter slowly changing data. When outputting in this mode, it is possible to programmatically generate control signals (control bytes) by external devices.

In mode 1, an asynchronous data exchange is carried out on channels A and B using control signals transmitted on channel C. In this mode, asynchronous data exchange with gating and acknowledgment can be arranged. Gating provides synchronization of transmitted data and increasing the reliability of the installation of signals on communication lines.

Acknowledgment allows the coordination of the operation of external devices and the microprocessor. When acknowledging, the next byte of data is transmitted only when confirmation of reading the previous one is received.

от внешнего устройства. Канал в свою очередь формирует сигнал ВВБФ, который поддерживается в течение всего интервала времени от записи данных до их чтения микропроцессором. Для информирования микропроцессора о готовности данных для ввода используется выходной сигнал

.Information is entered into the channel data buffer when a gating signal is received

from an external device. The channel, in turn, generates a VVBF signal, which is maintained for the entire time interval from data recording to reading by the microprocessor. An output signal is used to inform the microprocessor about the readiness of data for input.

.

. В момент окончания записи данных формируется выходной управляющий сигнал

, который указывает на готовность данных для выдачи в ВУ.Data is written to the channel using a write pulse from the system bus supplied to the input

. At the end of data recording, an output control signal is generated

, which indicates the readiness of the data for issuance to the WU.

используется для информирования микропроцессора о готовности канала к выводу новых данных (табл.3).The output of information from the channel buffer and its entry into the control unit takes place according to the “RECEPTION” signal issued from an external device, and the signal

used to inform the microprocessor about the readiness of the channel to output new data (table 3).

Mode 2 is used only for the organization of bidirectional data transmission in channel A. At the same time, the bits of register C (C3, C4, C5, C6 and C7) are still designed to generate and receive control signals similar to signals of mode 1 (see Table 3 ) Channel B can only work in modes 0 and 1 (C0, C1 and C2).

Combinations of modes for channels are set programmatically during initial installation. Programming consists in tuning to the required exchange mode and direct data exchange using the two input and output commands of the microprocessor IN and OUT. When programming in the control register (address A1A0 = 11), the OUT command records the control word US, the bits of which determine the operating mode for each channel (0, 1 or 2) and the direction of exchange.

The control word is formed in the microprocessor as an 8-bit word and is contained in the battery. The format of the control word is shown in FIG. 8.

As an example, consider how to set the operating modes and directions of exchange in channels A, B, and C. Let, for example, it is necessary to organize data input on channel A and data output on channels B and C in mode 0. For this, the microprocessor must be formed CSS as follows: 10010000.

This control word with the OUT xxxxxx 11 command is written to the control register, where the two least significant bits of the port 11 address indicate that the contents of the accumulator (USB) should be written to the control register. The remaining bits of the port address are used for addressing to the LSI by generating a VM signal

Data input-output commands for channels A, B and C are as follows:

IN xxxxxx 00 (reading the data byte from channel A and entering it into the battery);

OUT xxxxxx 01 (data output from the processor battery and recording to channel B);

OUT xxxxxx 10 (data output from the processor battery and recording to channel C).

The connection diagram of the programmable interface КР580ВВ55А to the system buses of the microcomputer is shown in Fig.9.

Functional diagram of the control device counter modification address 19 and its relationship with other blocks is shown in Fig.10.

In flight, the information at the inputs DO-D7 of the memory devices RAM 11 and RAM 12 comes from the adders 9 and 10, respectively. Information is recorded on the trailing edge of the signal S4 coming from the control unit 13.

The write address in the memory devices RAM 11 and RAM 12 is formed by the address modification counter 14. During the flight, the address is modified by the signal S1 coming from the control unit 13 through the 2xOR inverter D4 in the control unit of the address modification counter 19.

When the counter overflows the address modification counter, a “Stop” signal is generated at its output, which is input to the control unit 13.

On the ground, resetting the address modification counter 14 is carried out by a signal from the “Manual reset” button, coming through the 2xOR D3 inverter in the control unit of the address modification counter 19.

Information is input from the RAM 11 and RAM 12 storage devices by the IOP system controller that is part of the microcomputer 20. The IOP system controller is implemented on the KR580BK28 chip, the operation of which was described above.

The information output D0-D7 of the RAM 11 is connected to port A of the IOP controller, the RAM 12 to port B, respectively (see Fig. 10).

Reading data from memory devices RAM 11 and RAM 12 is carried out in mode 0. The choice of this mode is due to the fact that the microcomputer solves only one specialized task. Therefore, it does not require either performance or multitasking.

Block 19 is controlled by signals coming from port C of the IOP controller. The list of commands is given in table 4.

Table 4 Unit Control Commands 19 Command code KS3 KS2 KS1 KS0 Team description 0001 Setting the clock signal at the RS output of trigger D2 0010 Reset the clock signal at the RS output of trigger D2 0100 Address Modification 1000 Reset address modification counter 14

The information reading cycle consists of the following operations:

1. Before starting the calculations of Ω _и1л and Ω _{и1п, the} command “Reset address modification counter 14” is displayed on port _C. By this command, “1” from the discharge KC3 of port C goes to the D3 inverter D3 of block 19 and then to the input R of the 16-bit counter for modifying address 14. The bits A15-A0 of the counter are reset to 0.

2. On the port C the command “Reset the clock signal at the RS output of flip-flop D2” is displayed. By this command “1” from the discharge KC1 of port C goes to the inverter D1 2xOR and then to the input R RS of the trigger D2 of block 19. The RS trigger D2 sets the signal ЧТ = 0. By this command, the memory devices RAM 11 and RAM 12 are put into standby mode to the sample at the new address.

3. On the port C the command “Setting the clock signal at the RS output of flip-flop D2” is displayed. By this command “1” from the discharge KC0 of port C is fed to input S RS of flip-flop D2 of block 19. RS flip-flop D2 sets the signal TH = 1. By this command, the memory devices RAM 11 and RAM 12 select data at the modified address.

4. Microcomputer 20 asynchronously reads data from RAM 11 through port A.

5. Microcomputer 20 asynchronously reads data from RAM 12 through port B.

6. Microcomputer 20 performs operations to calculate Ω and _1l and Ω and _1p .

7. The "Address Modification" command is displayed on port C. By this command “1” from the discharge KC2 of port C goes to the inverter D4 2xOR and then to the input +1 of the counter for modifying address 14. The 16-bit address A15-A0 of the counter is increased by one and goes to the address inputs of memory devices RAM 11 and RAM 12 .

After this, operations 2-7 are repeated in a cycle until the counter for modifying address 14 is filled. The amount of data read is determined programmatically, so the Stop signal does not start in microcomputer 20.

The resistors R1 and R2 of block 19 are designed to input “0” to the RS inputs of the trigger when the discharges KC0 and KC1 are set to a high impedance level.

A functional diagram of the block of buffer registers 21 and its relationship with the microcomputer 20 and the on-board device for recording flight parameters 22 is shown in Fig. 11.

Information is output to the block of buffer registers 21 by the IOP system controller, which is part of the microcomputer 20. This IOP system controller, as well as the IOP system controller for inputting information from RAM 11 and RAM 12 devices in Fig. 10, is implemented on the KR580VK28 chip.

The IOP controller for outputting the results of the calculation of Ω and _1l and Ω and _1p in the block of buffer registers 21 operates in mode 1.

Inverter D3 of block 21 is designed to input microcomputer signals ZPR = 1 and RECEPTION = 1 via channels A and B (see table 3).

The result of the calculation of Ω and _1p from port A of the IOP controller of the microcomputer 20 is entered in the bits D0-D7 of the register D1. Recording is carried out by the FBG signal coming from KC7 of port C (see table 3).

The result of the calculation of Ω and _1p from port B of the IOP controller of the microcomputer 20 is entered in bits D0-D7 of register D2. Recording is carried out by the FBG signal coming from KC1 of port C (see table 3).

The resistors R1 and R2 of block 21 are designed to input “0” to the inputs of the RFP registers D1 and D2 when the bits KC1 and KC7 are set to a high impedance level.

The outputs D0-D7 of the registers D1 and D2 are received for recording in the on-board recording device.

Consider the algorithm for calculating Ω _u1l and Ω _u1n .

The disadvantage of the prototype algorithm, namely, the determination of the frequency of natural oscillations of the wing of the aircraft (first tone) should include the need to use double integration operations. If there is a constant error in the accelerator signal, this procedure leads to the appearance of an uncontrolled error in the calculated signal after double integration operations. In addition, to obtain a numerical value of the frequency of natural bending vibrations in the first tone, it is necessary to carry out spectral decomposition of the signals of accelerometers. For such a decomposition, the Fourier and Laplace integral transforms are most widely used.

The significant difficulty associated with the numerical application of integral transformations is caused by infinite limits. In the practical calculation of the Fourier transform, time or spectral windows are usually used, which, in turn, can significantly distort the initial spectrum. For the Laplace transform, you can use the truncation of infinite limits [7]. In this case, the question of spectrum distortion also arises. To convert

the relative error associated with the limitation of the upper limit by the value of t _k has the form:

After changing the variable τ = tt _k, we have

,

,

, а ее модуль

.The value ε (p) is a constant for some signal x (t), the modulus of which depends on the type of signal. Thus, the relative error can be represented as:

, and its module

.

So, for a non-diverging process with | C | ≤1 and σ = α / t _{k, the} relative error does not exceed the value of e ^-α . Therefore, due to the indicated choice of the real part σ of the complex variable p, it is possible to achieve a small error in the constraint of the integral transformation.

To exclude the double integration operation from the algorithm, we use the "symmetric Laplace transform" [8]:

The practically significant property of such a transformation includes:

:Relation (3) allows us to obtain the desired energy characteristic of the process x (t) from the recorded values of the second derivative

:

Relation (4) can be simplified by choosing the origin t = 0, so that x (0) = 0.

As a result, we get finally:

Taking into account discretization and finiteness, the approximate calculated relations for the image (2) have the form:

where i is the number of the discrete time instant; N _T +1 - the number of small segments of the discretization of the segments [-T, 0], [0, T].

Note that in relations (6) p = σ + jω _k , where ω _k is the calculated value of the frequency.

The choice of a sufficiently small sampling step in the calculation of images is similar to the choice of the step of integrating the differential equations of the dynamic model of the system under study when simulating transients and is determined by the upper frequency of the harmonic components taken into account.

The frequencies of the harmonic components of the spectral representations of transients are given by the coefficient ω of the imaginary part of the complex variable p. Therefore, by imposing a restriction on ω, depending on the value of Δt, the required degree of smallness of the sampling error in the calculation of images is provided.

With sufficient accuracy for practical calculations and when applying linear interpolation of processes, this restriction has the form (ω / 2p) <(5-6) f _p , where f _p = 1 / Δt is the frequency of registration processes.

Applied to accelerometer signal recordings:

relation (5) taking into account (6) will take the following form:

.Relations (8) are complex. To simplify the algorithm for calculating the desired energy characteristics, we perform a series of transformations. We consider these transformations as applied to the signal of the left accelerometer

.

Where

имеем:Similarly, for

we have:

Where

Note that relations (9) - (12) were obtained for a specific frequency ω _k .

Taking into account the obtained relations (9), (11), the spectral characteristic for the “right accelerometer” will take the form:

,

,Where

,

,

,

,

The value of the spectral characteristic for the frequency ω _k takes the form:

To obtain the spectral characteristics in the entire range of interest to us from 0 to 10 Hz, it is necessary to cyclically reckon the ratios according to relations (9) - (14) with a given frequency step.

It is advisable to search for the frequency of natural vibrations by direct enumeration, taking into account the small number of points of the spectral characteristic and the presence of a priori one extremum corresponding to the frequency of natural vibrations.

Similarly, the spectral characteristic for the signal of the "left" accelerometer is determined.

Thus, the proposed device eliminates the disadvantages of the prototype, namely the inability to control the stiffness of the wing outside the base airfield, which will improve the reliability of control of the strength properties of the wing of the aircraft and prevent the destruction of the wing in flight.

In addition, the disadvantages of the prototype algorithm were eliminated, which provided for the necessity of using the double integration operation and the appearance of an uncontrolled error in the calculated signal.

To exclude the double integration operation from the algorithm, a “symmetric Laplace transform” is proposed, represented by formulas (1-13).

Information sources

1. Vorobyov V.G. etc. Aviation devices, information-measuring systems and complexes. Textbook for high schools / V.G. Vorobyov et al. - M.: Transport, 1992. - P.104-108.

2. The control system of the strength properties of the aircraft wing. Kashkovsky V.V., Ustinov V.V. Poluektov S.P. Zheltukhin S.N. RF patent No. 2348916, IPC G01N 3/02, G01M 7/02, 2009.

3. Aviation devices. Ed. S.S.Dorofeeva. - M.: Military Publishing House, 1992. - S.373-405.

4. Strygin VV and others. Fundamentals of computing, microprocessor technology and programming. Textbook for students of technical schools. / V.V. Strygin et al. - M.: Higher School, 1989. - P.225, 92, 108, 149, 74, 98, 103.

5. Microprocessors and microprocessor sets of integrated circuits: a Reference. Ed. V.A. Shakhnova. - M .: Radio and communications, 1988. - T.1. - 368 p.

6. Paulov P.M. et al. On-board computing devices and machines. Tutorial. Part II / R.M.Polovov et al. - Moscow: MGTU GA, 2004 .-- 96 p.

7. Kachanov B.O. Laplace image of random processes and nonparametric identification of continuous systems // Automation and Remote Control. No. 1, 2004, p. 74-81.

8. Kachanov B.O. Symmetric and skew-symmetric Laplace transforms for identification problems. - On Sat Mathematical support of tasks of control, assessment and identification of aircraft and their systems. Scientific and methodological materials. - M.: VVIA them. N.E. Zhukovsky, 1996.

Claims (1)

An aircraft wing strength control device comprising three vibration sensors, an analog signal switch, an analog-to-digital converter, three parallel registers, two adders, two random access memory devices, an address modification counter and a control device, the vibration sensors being connected through the switch to the first analog input -digital converter, the output of which is directly connected to the first inputs of the registers, the output of the first register is connected to the first input of the first adder, the output of the third register - with the first input of the second adder, and the output of the second register with the second inputs of the adders, the outputs of which are connected to the first inputs of the storage devices, the second inputs of which are connected to the address modification counter, and the output of the control device, which is simultaneously connected to the second inputs of the registers and the analog-to-digital converter, as well as the fourth input of the switch, while the three information inputs of the control device are connected to the permanent logical elements s ”,“ Flaps removed ”and the“ Manual start ”signal, and the fourth input of the control device is connected to the output of the address modification counter, characterized in that it also includes an address modification counter control device, a microcomputer with a block of buffer registers connected in series with its output and an on-board device for recording flight parameters, while the outputs of memory devices are included on the first and second inputs of the microcomputer, its third input serves as the information input of the “Start” command, and the second output is connected it is connected to the second input of the address modification counter control device, the first input of which serves as the information input of the Manual Reset command, its third input is connected to the third inputs of the storage devices, whose fourth inputs are connected to the first output of the address modification counter control device, the second output of which is connected to address modification counter.

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