RU2462804C1 - Frequency-pulse duration alternating voltage controller - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: frequency-pulse duration alternating voltage controller has an adder, an integrator, a relay element, comparators, dynamic D flip-flops, switch elements (thyristors), load resistors connected in a star circuit with a neutral terminal, a setting signal source and a three-phase voltage source. Said alternating current controller includes three dynamic D flip-flops, which enable to generate 'packets' of sinusoidal voltage across the load with a whole number of periods of mains voltage.

EFFECT: high energy efficiency.

5 dwg

Description

The device relates to the field of power converting technology and can be used, for example, in temperature controllers with “packet” pulse-frequency-pulse-frequency regulation of alternating voltage.

A device for pulse-phase control of a valve converter (SU No. 873374, application. 02.11.78; publ. 15.06.81) containing adders, integrators, relay elements, control pulse shapers, power valve cascades is known.

The disadvantage of the device as applied, for example, to AC voltage regulators is the phase mode of operation of power switches, which adversely affects the energy performance of not only the voltage regulator itself, but also the power system as a whole.

With insignificant circuit changes, the known gate converter can be switched to the mode of latitudinal (PWM) - or frequency-pulse-width (PWM) regulation of the output alternating voltage, when the output coordinate is a "packet" of a sinusoidal signal separated by "zero" pauses. The duration of the "packets" and pauses is determined by the magnitude of the control signal. At the same time, the duration of the “packet” and the pause should correspond to an integer number of periods of voltage, which is not feasible within the framework of the well-known technical solution due to its circuitry features.

Closest to the proposed voltage regulator is a device for pulse-phase control of the converter (SU No. 851729, application. 05.22.79; publ. 03.27.81), containing adders, amplitude modulators, integrators, DC amplifiers, pulse shapers, relay elements, power keys, frequency-to-analog converter.

The prototype device is also characterized by low energy performance when operating as an AC voltage regulator with "batch" regulation due to the impossibility for the CHSS mode to provide an integer number of periods in the active regulation interval. As a result, a constant component appears on the load, which causes an increase in current consumption from the power transformer of the power system, which will reduce its energy efficiency.

An object of the invention is to increase the energy performance of a pulse-frequency-pulse-frequency alternating voltage regulator, namely, reducing the current consumption of the regulator.

The proposed regulator contains voltage sources of phases A, B, C connected to a load connected according to the star circuit with a zero output through normally open first, second and third key elements, respectively, sequentially connected reference signal source - input terminal, adder, integrator , a relay element and a first comparator, and the output of the relay element is connected to the second input of the adder, also containing a second, third and fourth comparators connected to voltage sources of phases A, B, C, respectively, and characterized in that the first, second and third D-flip-flops are introduced into it, the D-input of the first D-flip-flop connected to the output of the first comparator, the C-input of the first D-flip-flop connected to the output of the second comparator, and the output of the first D-flip-flop connected to the control input of the first key element, the output of the third and fourth comparators are connected to the C-input of the second and third D-flip-flops, respectively, the D-input of the second D-flip-flop is connected to the output of the first D-flip-flop, the D-input of the third D-flip-flop is connected to the output of the second D-trigger, WTO output Horn and third D-flip-flops are connected to the control input of the second and third key elements, respectively.

The technical result of the proposed voltage regulator is its increased energy performance, associated primarily with a decrease in current consumption from the power transformer of the power system.

The stated technical problem is achieved through the introduction of three dynamic D-flip-flops, which ensure the formation of a load of "packets" of sinusoidal voltage with an integer number of periods of voltage.

The invention is illustrated by drawings, where

figure 1 is a functional diagram of the proposed controller;

figure 2 shows the timing diagrams of the signals of the proposed controller;

figure 3 shows the signal diagrams of the proposed controller, obtained on the model in the package "Matlab + Simulink";

figure 4 shows the timing diagrams and analytical relationships to a comparative analysis of the characteristics of the known and proposed voltage regulator;

figure 5 presents the structure and signal diagrams of a single-phase unsynchronized voltage regulator to explain the disadvantages of known regulators.

The composition of the proposed AC voltage regulator (figure 1) includes serially connected reference signal source - terminal 1, adder 2, integrator 3, relay element 3 and the first comparator 5. The output of the relay element 4 is connected to the second input of the adder 2. The inputs of the second 6 and the third 7, and the fourth 8 comparators are connected to voltage sources of phases A, B, C, respectively. The outputs of the comparators 6, 7 and 8 are connected to the C-inputs of the first 9, second 10 and third 11 D-flip-flops, respectively. The D-input of the first D-flip-flop 9 is connected to the output of the first comparator 5. The D-input of the second D-flip-flop 10 is connected to the output of the first D-flip-flop 9, and the D-input of the third D-flip-flop 11 is connected to the output of the second D-flip-flop 10. The outputs of the D-flip-flops 9, 10 and 11 are connected respectively to the control input of the first 12, second 13 and third 14 key elements. Voltage sources of phases A, B, C - terminals 15, 16 and 17, respectively connected through the first 12, second 13 and third 14 power switches to the corresponding inputs of the three-phase load 18 connected according to the "star" circuit with a zero output - terminals 19, 20 and 21.

The elements of the voltage regulator have the following characteristics. The adder 2 is made with a single transmission coefficient for each of the inputs.

Integrator 3 implements a transfer function of the form W (p) = 1 / T _and p, where T _and is the integration time constant. Its output signal increases linearly with a jump in the input action with a sign opposite to the sign of the input signal.

The relay element (RE) 4 has a non-inverting hysteresis loop symmetrical with respect to the zero level and switching thresholds ± b.

Comparators 5, 6, 7, 8 have a non-inverting characteristic with zero switching thresholds and are designed to convert a bipolar input signal into unipolar pulses.

D-flip-flops 9, 10, 11 are dynamic and switch to the state of the D-input at the leading edge of the pulse at the C-input.

The keys 12, 13, 14 are closed with a positive sign of the signal at their control inputs.

The principle of operation of the proposed controller is as follows.

Comparators 6, 7, 8 form a signal "I" synchronously with the transition of the corresponding phase voltage through the zero level (figa-d). Blocks 2, 3, 4 in aggregate form a self-oscillating system with FWHM, when one of the intervals of the sweep conversion is determined by the difference of the reference signal from the input terminal 1 and the output signal of the relay element 4, and the second interval depends on the sum of these signals. The law of change of the conversion intervals and the period of self-oscillations at the output of RE 4 corresponds to the relationships shown in the table in FIG. The output signal of the integrator 3 has a sawtooth shape, and is limited in amplitude by the thresholds of switching RE ± b (Fig.2, e).

The comparator 5 converts the bipolar output pulses of RE 4 (figure 2, e) into a unipolar signal (figure 2, e).

On the leading edge of the output pulses of the comparators 6, 7, 8 (FIG. 2, b-d), the dynamic D-flip-flops 9, 10, 11 (FIG. 2, g-i) are switched to a state that has their D-input ( figure 2, e, g-i). In this case, the keys 12, 13, 14 are sequentially closed, providing a load of 18 "packets" of sinusoidal voltage with an integer number of mains voltage periods, sequentially shifted relative to each other (Fig. Turning off the keys 12, 13, 14 also occurs sequentially (figure 2, g-i) under the action of the output pulses of the comparators 6, 7, 8 (figure 2, b-d) in the time interval when the relay element 4 switches to "negative "State (figure 2, d, e). The interval of a pause between the "packets" also corresponds to an integer number of periods of voltage.

The diagrams of the voltage regulator signals obtained as a result of its modeling in the Matlab + Simulink package are shown in Fig. 3 and do not require additional explanations.

Thus, the introduction of D-flip-flops 9, 10, 11 into the control system provides an increase in the energy performance of the voltage regulator with PWM.

Compare the proposed controller (figure 1) with the prototype device.

We believe that the "package" of the sinusoidal voltage corresponds to the interval t ₁ , and the pause - t ₂ latitudinal or frequency-latitude-pulse signal (figa). Moreover, the law of variation of sampling intervals t ₁ , t ₂ and period T ₀ with PWM and PWM is shown in Fig. 4, b.

Figure 5, a shows a diagram of a single thyristor switch 2 with a load of 3, controlled by PWM 1. We believe that with a positive pulse at the output of PWM 1 (Fig. 5, c), the key 2 goes into the closed state. Then, at the load 3, a "package" of sinusoidal voltage is formed (Fig. 5, g). However, due to the inconsistency of the frequencies of the mains voltage (Fig. 5, b) and the modulator 1 (Fig. 5, c) on the load 3, a “packet” may be formed from an integer number of periods of the mains voltage (Fig. 5, g, here, as an example 4.5 periods of the mains voltage are shown). The next "package" may contain at the initial stage only part of the half-cycle of the mains voltage, for example, the thyristor will open at an angle of 90 el. hail. (figure 5, g). As a result, a constant component Y ₀ will appear on load 3 (Fig. 5, d), which will cause an increase in current consumption from the power transformer of the power system, which will reduce its energy efficiency.

The noted drawback is quite easily eliminated in digital PWM with a discrete increment of the “packet” for one period of the network voltage as the control signal grows. However, the PWM has a limited control range "D" (Fig.4, b).

, близком к 1,0, стремится к бесконечности (фиг.4, б). Согласовать же частоту сети с частотой ЧШИМ в аналоговых схемах не представляется возможным ввиду существенной нелинейной зависимости выходной частоты ЧШИМ от сигнала управления.In this regard, promising CWI, where the control range with the growth of the control signal is almost unlimited (Fig.4, b). However, the digital implementation of such a modulation law requires an infinitely large number of bits of the counting circuit, since the interval t ₁ at

, close to 1.0, tends to infinity (Fig.4, b). It is not possible to match the network frequency with the PWM frequency in analog circuits due to the significant nonlinear dependence of the PWM output frequency on the control signal.

Thus, the known technical solution when operating as an AC voltage regulator is characterized by low energy performance.

Comparison of the proposed controller (figure 1) with the prototype device in the composition of the functional blocks allows us to draw the following conclusions:

1. Blocks 4, 10, 13 (prototype device) are equivalent to blocks 2, 3, 4 in the proposed controller.

2. The relay elements 21, 22, 23 in the known device correspond to the comparators 6, 7, 8 of the considered PWM controller.

3. Block 19 in the prototype device corresponds to the keys 12, 13, 14 of the proposed controller.

4. Block 5 (Fig. 1) is not a distinguishing feature of the proposed controller, since it performs the standard function of converting bipolar pulses into a unipolar signal for docking the output of RE 4 with elements of digital electronics (D-triggers 9, 10, 11).

5. A distinctive feature of the proposed controller is the presence of D-triggers 8-11 and the relationships between them.

The claimed regulator is supposed to be used in the electric workshop of Chelyabinsk Pipe-Rolling Plant OJSC to automate the operating modes of heat-heating drying chambers.

Claims (1)

Frequency-pulse-width AC voltage regulator containing voltage sources of phases A, B, C connected to a load connected by a star circuit with a zero output through normally open first, second and third key elements, respectively, sequentially connected reference signal source - an input terminal, an adder, an integrator, a relay element and a first comparator, and the output of the relay element is connected to the second input of the adder, also containing a second, third and fourth comparators connected to the source phase voltage A, B, C, respectively, characterized in that the first, second and third D-flip-flops are introduced into it, the D-input of the first D-flip-flop connected to the output of the first comparator, the C-input of the first D-flip-flop connected to the output the second comparator, and the output of the first D-trigger is connected to the control input of the first key element, the output of the third and fourth comparators are connected to the C-input of the second and third D-triggers, respectively, the D-input of the second D-trigger is connected to the output of the first D-trigger, D-input of the third D-trigger connected to the output of the second D-flip-flop, the output of the second and third D-flip-flops is connected to the control input of the second and third key elements, respectively.

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