RU2460215C1 - Radio modem - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: method is realised by means of using procedures of initial assessment of a frequency shift based on a pilot signal and introduced with a channel in a multi-frequency modem with a differential multiple phase modulation and quadrature realisation of a modulator and demodulator; establishment of symbol synchronisation and tracking the position of symbol synchronisation and frequency shift with application of a working signal.

EFFECT: higher noise immunity of a device, also by elimination of impact from noise concentrated by spectrum and interfering with a frequency band of one of parallel subchannels to other subchannels.

1 cl, 40 dwg

Description

The present invention relates to telecommunication technology and can be used in data transmission systems on KB and VHF radio channels.

Radio modems are already known, described, for example, in [1, 2] and based on serial transmission of data over a fading radio channel. The presence of a multipath effect in such channels, in which the propagation delay of individual beams reaches several milliseconds, leads to significant intersymbol interference (MSI). To combat this phenomenon, adaptive correctors are used, based on a periodic assessment of the channel characteristics by testing it with a special sequence. This sequence should be long enough to reflect all the features of the channel characteristics due to the presence of ISI. This leads to a decrease in the transmission speed (while also reducing the useful power of the transmitted signal). Therefore, as noted in [3], such devices have a relatively low information speed.

Known parallel radio modems [4], built using several dozen pilot signals, the parameters of which depend only on the state of the propagation medium and can be determined and used in the demodulation process on the receiving side of the radio line. The presence of a large number of uninformative signals significantly reduces both the energy efficiency of such devices and the efficiency of their use of the allocated frequency band, which ultimately leads to a decrease in noise immunity.

Known parallel radio modem [5], the closest to the proposed invention. The structural diagram of this device is shown in figure 1. Note that in order to enable the identification of significant distinguishing features of the claimed object, Fig. 1 shows a functional diagram of the device constructed in strict accordance with the description in the text of [5] of the principles of implementation and interaction of the individual nodes of this device. The presented functional diagram is more complete and detailed than in FIGS. 12-17 of the aforementioned work [5]. The radio modem contains five switches (CM) 1, 14, 17, 18 and 19, an encoder 2, a buffer storage device (BN) 3, block 23 distribution and formation of frames (BRFK), block 4, the calculation of the inverse discrete Fourier transform (ODPF), block 5 adding a guard interval (BDZI), a converter of a numerical array into a time sequence (ППМВП) 6, a forming filter (ФФ) 7, a matching unit 8 (BS), a tuning sequence generator (GNP) 9, a block of 10 reference frequencies (BOC), an input block (WB) 11, block 12 automatic gain control (AGC), block 24 convert frequency (BPC), buffer storage unit 13 (BZB), calculator of differential power of non-signal tone 25 (BPMNT), block 15 of the discrete Fourier transform (DFT), block 22 of the calculation of the argument and phase rotation (BAPF), block 26 of the interval orthogonality ( BZIO), a generator 27 of samples of carriers with offset frequencies (FNCH), a block 28 for generating an initial address for testing symbol synchronization (BFNASS), a block 29 for accumulating and averaging (BNU), a block 30 for calculating the average phase shift (VSNF), block 31 for digital synthesizers frequency (CSC), block 32 determining the optimal positions of the frequency and symbol synchronization (FHCHF), block 20 calculating the informative phase increment (BWIPF), block 21 evaluating the values of the symbols and the reference phase (BOS), block 33 calculating the differential power and averaging (BVRM), a reversible counter (PC) 34 and control unit 16 (CU), the first input of switch 1 being connected to the input of the modem transmitter, the second input of this switch being connected to the training sequence generator 9, the third input of switch 1 connected to the first output of CU 16, and the third input of block 31 digital frequency synthesizers, the first input of the starting address generating unit 28, the second inputs of the averaging unit 29 and the 32 determining optimal positions of the frequency and symbol synchronization; the output of the switch 1 is connected to the input of the encoder 2, the output of the encoder 2 is connected to the input of the buffer drive 3, the output of the buffer drive 3 is connected to the input of the block 23 distribution and formation of frames, the output of which is connected to the input of block 4 computing the ODPF, the output of block 4 computing the ODPF connected with the input of the block 5 adding the protective interval 5, the output of which is connected to the first input of the converter of the numerical array in a time sequence 6, the second input of which is connected with the first output of the BOC 10, with the second inputs of the forming filter 7 input unit 11, with the fourth input of the buffer storage unit 13, the third input of the orthogonality interval setting unit 26 and the first input of the digital frequency synthesizer unit 31, the output of the numerical array converter in the time sequence 6 is connected to the first input of the forming filter 7, the output of which is connected to the input of the unit 8 matching, the output of the matching block is connected to the input of the channel; the output of the communication channel is connected to the first input of the input block 11, the output of which is connected to the input of the AGC 12, the output of the AGC is connected to the first inputs of the block 24 of the frequency converters and switch 19, the second input of the block 24 is connected to the output of the block 31 of digital frequency synthesizers, the output of the block 24 of the converters the frequency is connected to the first input of the buffer storage unit 13, the second input of which is connected to the output of the second switch 14, the third input of the buffer storage unit 13 is connected to the second output of the control unit 16; the first and second outputs of the buffer storage unit 13 are connected respectively to the first input of the calculator of the differential power of the non-signal tone 25 and the third input of the block 15 of the DFT, the second input of the calculator of the difference power of the non-signal tone 25 is connected to the output of the block 28 of the formation of the initial address when testing symbol synchronization, the third input of the calculator the differential power of the non-signal tone 25 is connected to the third input of the accumulation and averaging unit 29 and the fourth output of the control unit 16; the fourth input of the calculator 25 of the differential power of the non-signal tone is connected to the fourth input of the block 29 of accumulation and averaging, the third input of the block 28 of the formation of the initial address when testing symbol synchronization and the second output of the BOC 10, the first output of the calculator of the difference power of the non-signal tone 25 is connected with the first input of the block 29 of the accumulation and averaging, the second output of the calculator 25 is connected to the first input of the switch 14, the second input of the switch 14 is connected to the fifth output of the control unit 16 and the second input of the DFT block 15, the third input comm tator 14 is connected to the first output of the DFT block 15, the first input of the DFT block 15 is connected to the fifth inputs of the initial address generating block 28 when testing symbol synchronization and the accumulation and averaging block 29, the first input of the orthogonality interval setting block 26 and the third output of the optimal position determination block 32 frequency and symbol synchronization, the second output of the DFT block 15 is connected to the first input of the argument calculation and phase rotation block 22, the third output of the DFT block 15 is connected to the fourth input of the separation calculation block 33 power and averaging, the second input of the argument calculation and phase rotation unit 22 is connected to the output of the average phase incursion calculation unit 30, the output of the argument and phase rotation calculation unit 22 is connected to the first input of the informative phase increment calculator unit 20, the second input of the orthogonality interval setting unit 26 connected to the third output of the BOC 10, the second inputs of the block 28 for the formation of the starting address when testing symbol synchronization, block 21 for evaluating the values of characters and the reference phase and the fifth input of block 33 is converted frequency, the output of the orthogonality interval setting unit 26 is connected to the second inputs of the switches 17, 18 and 19, the input of the carrier sampler 27 with offset frequencies is connected to the output of the counter 34 and the second input of the block 31 of digital frequency synthesizers, the first and second outputs of the carrier sampler with offset frequencies 27 are connected to the first inputs of the switches 17 and 18, respectively, the fourth input of the block 28 of the formation of the initial address when testing symbol synchronization is associated with the third output of the block management 16; the sixth input of the accumulation and averaging unit 29 is connected to the second output of the block 32 for determining the optimal positions of the frequency and symbol synchronization; the first and second outputs of the averaging block 29 are connected respectively to the first and third inputs of the block 32 for determining the optimal positions of the frequency and symbol synchronization; the first input of the mean phase incursion calculation unit 30 is connected to the third output of the symbol value and reference phase estimation unit 31, the second input of the average phase incursion calculation unit 30 is connected to the output of the informative phase increment calculator unit 20 connected to the first input of the symbol value estimation and reference unit 21 phases, the outputs of the switches 17 and 18 are connected respectively with the third and second inputs of the differential power calculation and averaging unit 33, the second input of the informative phase increment calculator unit 20 is connected to the second the output of the block 26 estimates the values of the symbols and the reference phase, the first output of which is the output of the modem, the output of the switch 19 is connected to the first input of the block 33 for calculating the differential power and averaging, the first and second outputs of the block 33 for calculating the differential power and averaging are connected respectively to the serial inputs of addition 3 and subtracting 4 of the reverse counter 34, the first and second inputs of the parallel code recording of which are connected respectively to the first and fourth outputs of the block 32 for determining the optimal positions often The exact and symbolic synchronization.

,…,

,…,

. При этом i-й фазовый сдвиг φ_i может быть представлен на плоскости с помощью единичного радиус-вектора, образующего угол φ_i с осью абсцисс. Координаты этого вектора: абсцисса a _сn (синфазная составляющая) и ордината a _{кв n} (квадратурная составляющая). Анализируя состав образованной q-битной группы из поступивших данных, кодер 3 выбирает соответствующие группе данных значения a _сn и a _{кв n} и передает их в буферный накопитель 3. Отметим, что для дальнейшего описания работы схемы удобно ввести в рассмотрение комплексный сигнал:The operation of the device is as follows. The data to be transmitted is transmitted to the first input of the switch 1, to the second input of which a digital signal is supplied from the output of the training sequence generator 9. The signal shown on the line in the time diagram shown in Fig. 2 is supplied to the third input of the switch 1 from the first output of the control unit 22 . As will be shown below, during the operation of the modem, 2 modes (cycles) can be distinguished: the mode of entering into communication (1st cycle) and the data transmission mode (2nd cycle). During the 1st cycle, under the influence of a single level at the control input 3, the output signal of the training sequence generator 9 is connected to the output of the switch 1, and during the 2nd cycle (“0” at input 3), the data to be transmitted is transmitted. The output signal of the switch goes to the input of encoder 2. The modem assumes the use of differential multiple phase modulation with a quadrature implementation of the modulator and demodulator [6], and the use of quadrature amplitude modulation is possible. In encoder 2, the sequence of data symbols is divided into groups of q bits (the q value is selected from the condition for applying 2 ^q -fold modulation). Each of the possible m-bit binary code combinations is associated with a certain phase shift selected from row 0,

, ...,

, ...,

. In this case, the ith phase shift φ _i can be represented on the plane using a unit radius vector forming the angle φ _i with the abscissa axis. The coordinates of this vector are the abscissa a _cn (in-phase component) and the ordinate a _{q n} (quadrature component). Analyzing the composition of the formed q-bit group from the received data, the encoder 3 selects the values of a _cn and a _{kv n} corresponding to the data group and transfers them to the buffer drive 3. Note that for a further description of the operation of the circuit it is convenient to introduce a complex signal:

, что необходимо для реализации параллельного способа передачи данных с использованием метода уплотнения с ортогонально-частотным разделением (OFDM - Orthogonal Frequency Division Multiplexing). Для обеспечения высокой скорости передачи данных число параллельных подканалов, а следовательно, и число поднесущих в спектре сигнала должно быть большим. Однако такую систему сложно реализовать по классической схеме с числом модуляторов, равным числу несущих. Вместе с тем существует возможность выполнить операцию модуляции во всех подканалах одновременно с гораздо меньшими реализационными затратами на основе эффективных методов цифровой обработки сигналов, а именно вычисляя ОДПФ с использованием алгоритма ОБПФ [7]. Если N/2 символов модулирующего сигнала

дополнить N/2 комплексно сопряженными символами

containing both information about a _cn and a _{q n} ; in this case, the imaginary unit j in this case plays the role of a label that distinguishes the quadrature component from the in-phase component. In the buffer storage 3 is the accumulation of N _T sequentially arriving at its input signal symbols

, which is necessary to implement a parallel data transmission method using the compression method with orthogonal frequency division (OFDM - Orthogonal Frequency Division Multiplexing). To ensure a high data rate, the number of parallel subchannels, and therefore the number of subcarriers in the signal spectrum, should be large. However, such a system is difficult to implement according to the classical scheme with the number of modulators equal to the number of carriers. At the same time, it is possible to perform the modulation operation in all subchannels simultaneously with much lower implementation costs based on effective methods of digital signal processing, namely, computing the ODPF using the OBPF algorithm [7]. If N / 2 characters baseband signal

complement N / 2 with complex conjugate characters

then after calculating the N-point ODFT, we get an array of real numbers:

The elements of the array { a _k , k = 0 ÷ {N-1)} can be considered as discrete reports of the sum of the outputs of all modulators of parallel channels taken at time instants:

kΔt = kT _opm / N,

по разным соображениям [5, §3.3.2, 3.3.3] выбирается меньшим N/2, т.е.wherein T _opm - the duration of the interval of orthogonality. Note that the size of the ODPF N is equal to the number of discrete samples of the modulated signal in the orthogonality interval. Efficient calculation of the sum (3) is possible using the FFT algorithm, while it is desirable that the size of the FFT N is an integer power of 2. Moreover, the number N _T of 2 signal symbols stored in the node

for various reasons [5, §3.3.2, 3.3.3] is chosen smaller than N / 2, i.e.

, вычисляемыми по правилу (2). Сформированный таким образом N-точечный массив комплексных данных подается на вход блока 4. В блоке 4 формируется совокупность значений фигурирующих в сумме (3) комплексных экспонент

. Эти сигналы образуются аналогично комплексному символу

, задаваемому (1), в соответствии с формулой Эйлера:This means that there are unused frequencies in the transmitted modem signal. In block 23, the addition of N _T of the 3 symbols accumulated by the block to N / 2 is carried out with zero values (corresponding to unused frequencies) and the resulting array is supplemented with N / 2 symbols

calculated by rule (2). The N-point array of complex data thus formed is fed to the input of block 4. In block 4, a set of values of the complex exponents appearing in the sum (3) is formed

. These signals are generated similarly to a complex symbol.

defined by (1), in accordance with the Euler formula:

С использованием этих значений и отсчетов

входного сигнала в соответствии с выражением (3) (либо непосредственно по этой формуле либо с использованием алгоритма БПФ) в блоке 4 осуществляется вычисление ОДПФ. В результате по окончании вычисления ОДПФ на выходе блока 4 получается массив из N действительных чисел, равных отсчетам последовательности a(kΔt)=a _k, определяемой (3). В блоке 5 добавления защитного интервала длина этого массива увеличивается путем его циклического расширения до S=N+N_ЗИ отсчетов, где N_ЗИ - количество отсчетов, содержащихся в защитном интервале OFDM-символа длительностьюThe implementation of this operation can be performed as follows: N equidistant samples of the period of harmonic oscillation are recorded in the storage device. By changing the addresses of the read samples in accordance with the values of n and k prescribed by formula (3) (or the FFT algorithm), and taking into account that the addresses of the samples of the sine wave are delayed by N / 4 relative to the addresses of the cosine wave with the same phase, we obtain oscillation values, the combination of which in according to (5) gives

Using these values and samples

the input signal in accordance with expression (3) (either directly by this formula or using the FFT algorithm) in block 4, the ODPF is calculated. As a result, upon completion of the calculation of the ODLPs at the output of block 4, an array of N real numbers is obtained that is equal to the samples of the sequence a (kΔt) = a _k determined by (3). In block 5 of adding a guard interval, the length of this array is increased by cyclic expansion to S = N + N _ZI samples, where N _ZI is the number of samples contained in the guard interval of an OFDM symbol with a duration

where Δt is the discretization step determined by relation (4).

The mechanism of formation of the cyclic extension is illustrated in Figure 3 and consists in placing copies terminal N _GI samples IDFT output symbols in the OFDM-top (formation of a prefix).

The presence of a guard interval is necessary to eliminate intersymbol interference due to multipath, as a result of which the first N _ZI samples of the next OFDM symbol turn out to be distorted and are simply discarded during demodulation. The restoration of the received information is carried out on N samples of the initial part of the OFDM symbol (Fig. 3) using N-point DFT for demodulation.

The output array of the guard interval adding unit 5, containing S samples, is fed to the first input of the numerical array converter into a time sequence 6, the second input of which from the first output of the reference frequency unit 8 receives the sampling frequency pulses (line a of the timing diagram shown in FIG. 2 ):

The output signal of block 6 is supplied to a shaping filter (FF) 7, which is a digital band-pass filter that limits the spectrum of the overall OFDM signal in accordance with the effective bandwidth of the telephone channel. The output signal of block 7 enters the matching block 8, where digital-to-analog conversion and normalization by the level of the generated signal are carried out, after which the signal is transmitted through the communication channel.

Before proceeding with the description of the operation of the structural diagram of the modem receiver, shown in figure 1, we note that the task of the receiver is to demodulate the received OFDM signal. It can be quite simply solved based on the calculation of the discrete Fourier transform (DFT) using FFT algorithms [7]. However, this requires perfect symbol synchronization and the elimination of the frequency shift introduced by the radio channel.

Since in KB modems a significant shift in the carrier frequency of the transmitted signal is possible, which also continuously changes over time, the estimate of this shift necessary to eliminate it is usually carried out in 2 stages: first, a rough estimate is made, and then an accurate one. Thus, the enlarged structural diagram of the modem receiver has the form shown in Fig.4 (in the description of the prototype [5] it is shown in Fig.14). The designations of the nodes shown in Fig. 4 are deciphered as follows: IF — frequency converter, BV — DFT calculation unit.

In the process of operation of the synchronization system, 2 stages are usually distinguished: the initial assessment of the sync parameters taking place at the stage of entering into communication, and the tracking of the changing values of the sync parameters made during the operation of the modem.

In the prototype device to establish symbolic synchronization, the method of “lagging and leading windows” is used, the essence of which is illustrated in Fig.5.

Figure 5 shows the temporal location of two successively received OFDM symbols containing S samples of the received signal (upper line), as well as the average position of a block of N samples of the OFDM symbol and 2 shifted by N _ZI / 2 corresponding to correctly established symbol synchronization position counts, the first shifted to the lead (leading window), and the second lagging (lagging window).

As noted in the description of the transmitter, the transmitted signal contains tones that are not used for data transmission. Suppose that one of these tones is in the subchannel with number n.

The situation depicted in FIG. 5 is characterized in that all the samples of the leading and lagging windows belong to the same OFDM symbol. In this case, the power of the nth DFT sample calculated from the N samples of the input signal included in the leading window will be equal to the power of the nth DFT sample calculated from N samples belonging to the lagging window. As a result, the output signal of the HC subtraction unit in FIG. 5 will be zero, which indicates the presence of established symbol synchronization. If the symbol synchronization is broken, the samples of one of the windows will go beyond one OFDM symbol, the power balance of the unused DFT samples calculated on the basis of the lagging and leading windows will be violated, and the output signal of the subtraction node will be nonzero. Thus, by the signal at the output of the HC, one can judge the presence of symbol synchronization.

A rough estimate of the frequency shift in the prototype is carried out by a method similar to the above-described method of “leading” and “lagging” windows, but implemented in the frequency domain. The idea of the method is illustrated in the flowchart shown in Fig.6.

This circuit includes 2 frequency converters IF1 and IF2, which transfer the spectrum of the input signal to the frequencies Δƒ + Δƒ _D and Δƒ-Δƒ _D , respectively, where Δƒ is the value of the tested value of the frequency detuning, and Δƒ _D is the deviation of the frequency detuning necessary for implementation of this method (in [5] it is recommended to choose Δƒ _D = 0.1ΔF _OFDM , where ΔF _OFDM is the bandwidth of one subchannel during OFDM transmission).

The calculation of the power, for example, selected for establishing synchronization, of the nth non-informational count of the DFT should be preceded by its selection, carried out by calculating the nth count of the DFT of the input signal.

At zero frequency detuning, the powers calculated in the lower and upper branches of the circuit are the same and there is a zero signal at the output of the HC subtraction node, if there is a frequency drift, the power balance is violated and the sign of the HC output signal indicates the sign of the frequency detuning.

The idea of making an accurate estimate of the frequency shift is based on the use of decisions on the meaning of the symbol transmitted over the i-th subchannel, and will be explained in more detail in the description of the implementation of the prototype device.

It should be noted that the considered method of symbol-by-symbol synchronization assumes that the frequency shift of the spectrum of the received signal introduced by the channel is completely eliminated. Similarly illustrated in Fig.6, the method of estimating the frequency shift is correct only if there is a set of symbol-wise synchronization.

However, at the stage of entering into communication, both of the above conditions are not satisfied. In this situation, in the prior art is realized joint estimation algorithm symbol by symbol synchronization and frequency offset based on the N -fold _SPM testing all possible combinations of positions symbol timing and frequency offset values, and averaging the results and memorizing subsequent finding optimal positions sinhroparametrov as a table cell coordinates with the minimum value average test result.

Let us further consider how all of the above is implemented in the prototype circuit shown in figure 1.

The signal coming from the communication channel is fed to the first input of the input unit 11, the second input of which from the output of the BOC 10 is supplied with clock pulses following with a sampling frequency ƒ _d (line a of the timing diagram of figure 2). In the input unit 11 is the filtering and analog-to-digital conversion. Next, the samples of the digital signal are fed to the input of the AGC block 12, which normalizes the level of the received signal. After that, the samples of the received digital signal s (kΔt) are fed to the first input of the block of frequency converters 24. The block diagram of the block 24 is shown in Fig.7. It is a series connection of a Hilbert PG converter and a set of N _hs parallel-connected frequency converters identical in construction to frequency converters ₁ , IF ₂ , ..., IF _Nch , where N _hs is the number of frequency shift estimation values introduced by the channel tested at the stage of connection.

The need for the parallel inclusion of such a large number of frequency converters is due to the fact that, due to a fairly rapid change in the parameters of the radio channel over time, the algorithm selected in the prototype for joint estimation of symbol-based synchronization and frequency shift based on enumerating all possible combinations and subsequent averaging makes practical sense only if when the evaluation of all tested values of the frequency shift is performed simultaneously. In this case, within one sending of the OFDM symbol, it will be possible (with sufficient speed of the selected element base) to evaluate by the “lagging” and “leading” window all N _ps tested positions of symbol-by-symbol synchronization, and the total time of entering the synchronism will be determined only by the number N _уcp OFDM- parcels on which the test results are averaged. An attempt to implement this algorithm by sequentially testing different values of the frequency shift will make this procedure pointless, since during its execution the channel parameters will change so significantly that the evaluation result will be unreliable.

A diagram of a specific implementation of the i-th frequency converter _i is shown in Fig. 8. It includes two multipliers and an addition node. The output signal of the IF _i s _Δωi (kΔt) is described by the expression:

Сигналы cos Δω_ikΔt и sin Δω_ikΔt, поступающие на вторые входы перемножителей схемы фиг.8, подаются на входы блока 24 с соответствующих выходов блока 31 цифровых синтезаторов частот. Структурная схема блока 31 представлена на фиг.9 и включает в себя ключ K и N_чс цифровых синтезаторов частоты ЦСЧ₁, ЦСЧ₂,…, ЦСЧ_Nчс. Отметим, что схема ЦСЧ₁ несколько отличается от схем остальных ЦСЧ_i, i≠1, поэтому на фиг.10 отдельно изображена структура ЦСЧ_i, i≠1, а на фиг.11 - ЦСЧ₁.Where

The signals cos Δω _i kΔt and sin Δω _i kΔt supplied to the second inputs of the multipliers of the circuit of Fig. 8 are supplied to the inputs of block 24 from the corresponding outputs of block 31 of digital frequency synthesizers. The block diagram of block 31 is shown in Fig. 9 and includes a key K and N _{hs of} digital frequency synthesizers DSCh ₁ , DSC ₂ , ..., DSC _Nchs . Note that the circuit of the DSC _{1 is} somewhat different from the schemes of the remaining DSC _i , i ≠ 1, therefore, in Fig. 10, the structure of the DSC _i , i ≠ 1 is separately shown, and in Fig. 11, the DSC ₁ .

As already noted, during the operation of the modem, two modes can be distinguished: the mode of entering into communication, in which the synchro-parameters are initially evaluated and the mode of operation, in which the transmitted data are received and the tracking of changes in the synchro-parameters (position of symbolic synchronization and frequency shift) necessary for this, due to a change in time of the channel parameters.

In the mode of entering into communication by the signal from the first output of the control unit 22 to the third input of block 31, the key K in the circuit of Fig. 9 is opened, and pulses with a sampling frequency частотой _d supplied to the first input of block 31 from the first output of the block of reference frequencies 10, arrive at the inputs of all the digital clocks _i , i = 1 ÷ N _hs . The functional diagram of one node of the CSC _i , i ≠ 1 (Fig. 10) includes two memories, in one of which are written N _p samples of the discretized period of the cosine wave, and in the other, sinusoid. Address read in the k-th step reference sample determined code at the output of the corresponding adder, this code is the sum modulo N _n number registered in the address register (Pr Adr) and a number ΔN _i, stored in Pg ΔN _i register, and defining the frequency Δω _i read from the DSC; discretized harmonic oscillations cos Δω _i kΔt and sin Δω _i kΔt. The value of ΔN _i is determined from the relation:

where Δƒ _i = Δω _i / 2π. Through the delay element EZ (see Fig. 10), the output code of the adder is fed to the input of the code rewriting circuit (SEC), by means of which, with the arrival of the next sampling pulse at the first input of the DSC 31, it is written to Pr Adr. The delay element EZ provides the ability to read the samples of the CSCH (before they change), prepared in a similar way at the previous sampling step, corresponding to the IF _i (see Fig.7).

The difference between the DSC ₁ circuit shown in Fig. 11 and the considered circuit is that, through a switch controlled by the signal from the first output of the control unit 16 received by the third input of block 31, during the first modem operation mode, the output is connected to one of the inputs of the adders register Рг ΔN ₁ (as in the circuit of FIG. 10), and in the second mode, the output of the reversible counter 34 associated with the second input of the frequency synthesizer unit 31.

Thus, in the first modem operation mode, at the N _h outputs of block 31, N _hs variants of the sampled output signal are generated with the influence of the estimated frequency shift introduced by the radio channel to varying degrees eliminated. These signals are fed through block 24 of the frequency converters to N _hs inputs Bx1, ..., Bx _{Nhs of the} buffer storage unit 13 (all of them are designated as the first input). Functional diagram of the buffer storage unit 13 is shown in Fig.12. It includes N _hc identical buffer storage nodes of the BZU _i ... The block diagram of the BZU _i node is shown in Fig. 13, and its operation algorithm is shown in Fig. 14. The node BZU _i shown in Fig. 13, consists of memory 1 containing S memory cells, and memory 2, including 2 S cells. To describe the algorithm of operation of the BZU _i, it is convenient to allocate ZU2-1, which includes the first S memory cells with addresses 0 ÷ (S-1) and ZU2-2, including the remaining S cells with addresses S ÷ (2S-1), as part of the memory unit2. The processes of writing and reading information in the BZU _{i are} controlled by the control unit of the BZU _i Since the implementation form of the described modem and its constituent blocks involves the use of a programmable multifunctional tool, Fig. 14 shows the functioning algorithm of the BZU _i block, from which the functions performed by the UI BZU _i node become clear. As a result of the analysis of the signal received at the third input of the buffer storage unit 13 (Fig. 12, Fig. 13) from the second output of the control unit 16 of Fig. 1 (see line e of the timing diagram of the operation of the device shown in Fig. 2), _{i of} FIG. 13 provides the execution of actions prescribed either by blocks 1 and 2 of the algorithm of FIG. 14 (these procedures are performed in parallel in time) or by blocks 3 and 4 of the algorithm of FIG. 14, implemented sequentially in time. As can be seen from the time chart, in this case, for almost the entire duration T _S = 1 / ƒ _{S of the} OFDM symbol (line in the diagram of FIG. 2), information recorded in memory 2 and necessary for testing various positions of symbol synchronization performed in accordance with with the algorithm of the “lagging behind” and “leading” windows described above (block 1 of the algorithm), and sequentially recording in memory 1 of new samples of the signal from the output of block 10 of the frequency conversion, arriving with a sampling frequency ƒ _d (block 2 of the algorithm). The sequence of clocked recording pulses with a frequency of ƒ _d is fed to the second input of the buffer storage unit 13 of figure 1.

To implement the synchronization method used in this device and the above, it is necessary, at the stage of entering into communication (i.e., in the 1st mode of the modem), to read N samples received at the buffer storage unit 13 s S times during one OFDM symbol unit 24 converting the signal frequency, while the starting address of each batch of N samples must be sequentially incremented. A similar situation occurs in the second (working) modem operation mode, in which the optimal position of the symbol synchronization is monitored. The difference from the 1st mode here is only in the fact that the number of tested positions can be reduced from S options to ± N _gr around the nominal (determined in 1 cycle and during the previous tracking).

The task of forming the starting addresses of the read batches of samples in the prototype is performed by block 28 of FIG. 1 of forming the starting address when testing symbol synchronization, the operation algorithm of which is shown in FIG. The algorithm starts when the modem is turned on. The algorithm shows the “beginning” and there is no “end”, since its execution stops only when the modem is turned off. The input 1 of the block 28 of FIG. 1 from the first output of the control unit 16 receives the signal shown on line g of the timing diagram of FIG. 2, which is 1 for the duration of the 1st mode and 0 for the 2nd.

Thus, the left part of the algorithm of Fig. 15 illustrates the operation of the start address generation unit 28 when testing symbol synchronization in the communication mode, and the right one in the operating mode. At the second input of block 28 from the third output of BOC 10 (Fig. 1), short single pulses with a frequency of ƒ _S (repetition rate of OFDM symbols) are shown, which are shown on a line in the time diagram (Fig. 2). The appearance of each pulse at the second input of block 28 of Fig. 1 corresponds to the beginning of the next cycle of testing the position of symbol-by-symbol synchronization, carried out during the duration of the OFDM symbol with a positive result of checking the condition Bx.2 = 1. If the result of this analysis is negative (Bx.2 = 0) using block 1 of the algorithm (FIG. 15) “NOP” or “no operation”, the next single pulse is expected to arrive at the second input of block 28. Moreover, in block 2 of the algorithm of FIG. 15, the value of the variable CA (address counter) is reset, then the signal arriving at the third input of block 28 from the second output of the BOC (line b of the time diagram of FIG. 2) is analyzed. This signal is a sequence of two-level square-wave pulses of the meander type (that is, with a duty cycle of 2). The repetition rate of these pulses ƒ _in3 slightly exceeds ƒ _d : ƒ _in3 = 1.3 ƒ _d , which allows S tests to be performed for a time shorter than the duration of the OFDM symbol T _c = S / ƒ _d .

Depending on which of the half-periods of the described signal is currently present at the third input of block 28 of FIG. 1 (in one of the half-periods Bx.3 = 0, in the other - Bx.3 = 1), block 3 or 4 of the algorithm of FIG. .fifteen. In each of these blocks, the value of the starting address for testing is issued to the first output of block 28 of FIG. 1 in accordance with the rule illustrated in FIG. In addition, the auxiliary variable ROM in each of the blocks 3, 4 of the algorithm of FIG. 15 is assigned a value equal to the value of the signal at Bx3. This is necessary in order to ensure, with the help of the subsequent conditional transition (ROM-Bx3 = 0), that the signal is waiting for the signal at Bx.3 to change its value and that the initial value of the output address remains unchanged during the half-cycle of the Bx3 signal. The waiting procedure is implemented using block 5 of the algorithm of FIG. Further, in the algorithm, the CA variable is incremented and the number of tests is checked. If it is less than the stipulated number of tests on a given package of the OFDM symbol N _ps = S, then state Bx.3 is analyzed again and the cycle repeats. At the end of testing on the next OFDM symbol (CA = -N _ps ), the signal status is checked again at Bx1. At the end of the first cycle, the second begins, “B” appears on Bx1 and the right-hand side of the algorithm of FIG. 15 works. Recall that in the second cycle, the task of block 28 of FIG. 1 is to generate the starting addresses of the frames from N samples taken from block 13 of FIG. 1 during the testing of the positions of symbol-based synchronization, carried out as part of tracking changes in the parameters of the radio channel in the operating mode. In this case, the state of the fourth input of block 28 of FIG. 1 is initially analyzed, to which the signal shown on line 3 of the time diagram of FIG. 2 is supplied from the third output of BU 16 and represents short unit pulses corresponding to the beginnings of the allowable interval for testing the positions of symbol synchronization in the operating mode (line x time chart, figure 2). This interval in the 2nd mode begins after the time Δt after the arrival of the next pulse with a frequency ƒ _S and ends by Δt before the arrival of the next pulse ƒ _S. Block 7 of the NOP algorithm (Fig. 15) is used to wait for the arrival of the next single pulse at input 4 of block 28 of Fig. 1. Next, the operation of the right-hand side of the algorithm of Fig. 15 is carried out similarly to its left-hand side, with the only difference being that in block 8 of the algorithm the value CA is assigned the value:

and to count the number of tests, an additional variable CT is introduced, initialized in the same block 8 of Fig. 14 with a zero value. At the input 5 of block 28 of FIG. 1, an “optimal” starting address is used, which is used to demodulate a frame of N samples of memory 2 of the buffer storage unit 13 of FIG. 1, which was determined during the 1st mode and the previous correction steps in the 2nd mode. In accordance with the testing rule illustrated by FIG. 5, to determine the initial value of CA, it is necessary to subtract N _ZI / 2 from it, which is done in block 8 of the algorithm of FIG. 15. By monitoring the optimal position of the N _opt symbol-by-symbol synchronization, the testing range can be narrowed compared to the mode of entering into communication, keeping it within N _opt ± N _gp . Therefore, the initial value of the variable CA is calculated by the formula (10) (subtraction is carried out modulo S, which allows you to take into account the case when N _opt <N _gr ). Obviously, with this choice of the initial value of SA for calculating the number of tests, it is advisable to introduce an additional variable ST.

As a result of the operation of this fragment of the algorithm during time intervals corresponding to single signal values on line g of the time diagram of Fig. 2, the output addresses of block 28 of Fig. 1 will show the starting addresses of frames from N samples necessary for testing the positions of symbol-based synchronization in the operating mode.

The initial frame addresses of N samples generated at the output of block 28 are supplied to the second input of the block 25 of calculators of the differential power of the non-signal tone, the structural diagram of which is shown in Fig. 16. The circuit includes N parallel _chc calculators non-signaling tone power difference VRMNT _i, the first inputs of which are combined in Scheme 1, in one common first input connected to the outputs of respective ZU2 BLT _i buffer memory unit shown in Figure 12. The operation algorithm of a separate block BPMNT _i is presented in Fig.17. The next start of this algorithm is carried out by pulses formed by the AND element depicted in Fig. 16 and the SVFI pulse front allocation circuit. The signal diagrams at the third and fourth inputs of block 25 (at the inputs of the circuit AND FIG. 16), the output of the circuit AND, and the output of the SVFI are shown respectively on lines g, b, and to the time diagram of FIG. 2.

The first block of the algorithm (Fig. 17) prescribes the reading from memory 2 of the BZU _{i of} Fig. 13 frames from N samples whose initial address is supplied to the second input of block 25 from the output of block 28 of Fig. 1. Addresses of sequentially read samples are formed by the read sample address generator (FASO) shown in the diagram of FIG. 16 and are supplied both to the second input of block 13 through switch 14 of FIG. 1 and to the second input of each VRMNT _i (FIG. 16). The latter is necessary to synchronize the cells of the internal memory BPMN _i , taking the values of the read samples, with the address of the read.

In the second block of the algorithm of Fig. 17, the n-th DFT sample is calculated (which is equivalent to the allocation of the n-th tone that is not used for transmission), carried out according to N readout samples in accordance with the expression:

In the third block, the power of the non-signal tone P _ns is calculated, calculated as:

At the fourth input of each block of BPMN _{i of} FIG. 16, a signal is output from the output of circuit I, illustrated by a line and a timing diagram of FIG. 2. Moreover, as can be seen from the comparison of the lines and to the time diagram, each odd start at the fourth input corresponds to 1, and to even 0. Therefore, with each odd start of BPMN _{i, the} left branch of the algorithm will be executed according to the condition Bx.4 = 0 of FIG. 17, which corresponds to the fixation in Pr1 of FIG. 17 of the DFT reading power calculated on the basis of the “leading” window (see FIG. 5), and for each even branch, the right branch fixing the same result for the “lagging” window and determining the difference power module whose value is output 1 _i sppm _i . In Fig.16, the outputs 1 _{i of} all BPMN _{i are} conditionally combined into the first output of block 25, which is shown in the form of a bus in the circuit of Fig.1.

The output signal of block 25 of FIG. 1 is input to the accumulation and averaging block 19, a diagram of which is shown in FIG. Block 29 includes N _hs memory and averaging nodes of the memory _{device i} . The task of each of these nodes is to memorize and average the difference powers calculated in block 25 in the first modem operation cycle at N _hs different values of the frequency offset compensated in block 24 (Fig. 1), in addition, the memory device _i is also used in the second modem operation cycle for tracking the optimal position of character-by-character synchronization The operation algorithm of the memory _{i is} illustrated in Fig.19. The start of this algorithm is carried out by the leading edge of the signal arriving at the third input of the accumulation and averaging unit 29 (inputs 3 _{i of the} memory _i ) and shown on line g of the time diagram of FIG. 2.

As already noted, the algorithm shown in Fig. 19 is implemented in the memory ₁ , which differs from the rest of the memory _i in that it is used in the 1st and 2nd modes of operation of the modem. Therefore, a signal from the first output of the control unit 16, shown on line d of the timing diagram of FIG. 2 and containing information on which of the operation cycles takes place, is fed to the second input of this node (the remaining memory _{I have} no input). Immediately after the start of the algorithm Dzuu ₁ verified condition Bx2 ₁ = 0 and the results of test are set the values of variables N _Fin and N _a, determining the number of symbols (chips) OFDM signal on which the averaging (N _Fin) and the number of test positions symbol unit synchronization (N _a ). In the memory _i for i ≠ 1, this check is absent and always sets the value N _fin = N _уcp , N _a = S inherent in the 1st mode.

Next, the condition M = 0 is checked, where M is a variable that is set to zero either at the end of the averaging cycle or when the modem is initially turned on (this case is not shown in the algorithm). When the condition M = 0 is fulfilled, preparation for a new averaging cycle is carried out, which consists in zeroing all N _a memory cells of the memory _i ; zero initialization of the counter j of averaged packages, and setting to 1 the value of M and the signal to Output2 (only for the memory ₁ ). Next, in the block 4 of the algorithm of Fig. 19, the counter of the memory cell address of the memory _i in which the averaged values of the difference powers are stored is reset. Inputs 4 _{i of} all the memory _i (i = 1 ÷ N _h ) are supplied with short single pulses (line l of the timing diagram of FIG. 2), formed by the conjunctor and the leading edge allocation circuit (FFS), shown in the lower part of the figure in FIG. 18. The inputs of the conjunctor (the third and fourth inputs of block 29) receive the signals depicted in the time diagram (Fig. 2, lines g and b), while the output produces the signal shown in the line and the time diagram. Note that a similar signal also occurs at the output of the conjunctor in the circuit of the calculator of the differential power of the non-signal tone (Fig. 16). However, in this case, the pulses at the output of the SVFI (Fig. 16) are formed not for each, but only for the leading edge of this signal (line l of the time diagram of Fig. 2). As a result, the values of Bx4 _i = 1 occur only at those times when the difference power of the “lagging” and “leading” windows is calculated on the first output of the block 29 of FIG. If the condition Bx4 _i = 1 is not satisfied, using block 5 "NOP"("nooperation") in the algorithm of Fig. 19, an expectation of the arrival of the next pulse on Bx4 _{i is} realized. Next, in block 6 of the algorithm, summation is performed with accumulation in the memory cell with the address CA (Pr (CA)), and then in block 7 the value of the CA address is incremented. The execution of the operations of blocks 6 and 7 of the algorithm (Fig. 19) continues cyclically until the contents of all N _a memory cells are changed, which is guaranteed by checking the condition CA <N _a . Then the value of the counter of the number of averagings j is incremented. When this variable reaches the value of N _fin (which means that the described algorithm has already been launched N _fin times, i.e., the averaging cycle is completed), values of M = 0 and Out2 = 0 are set using block 9 of the algorithm.

The signals from the fifth and sixth inputs (Fig. 18), respectively, received at inputs 5 _{i of the} memory device _i and at the control (lower) input of the KM switch (see Fig. 18), are issued at the end of the described operation cycle of the memory device _{i by} block 32 (Fig. 1) and are necessary for connecting to the first output of block 29 certain memory cells (Fig. 18).

The presence at the second output of the block 29 of accumulation and averaging of a zero signal indicates that information is recorded in the cells of this block, the analysis of which will allow us to conclude about the optimal value of the frequency shift and the position of symbol-by-symbol synchronization. This signal is supplied to the third input of the block 32 for determining the optimal positions of the frequency and symbol synchronization, the operation algorithm of which is shown in Fig. 20, and starts this algorithm. The task of block 32 is to determine the address of the memory cell in block 29 with a minimum value of the averaged differential power. At this address, in the 1st mode, the optimal values of the correcting frequency shift (by the number i of the memory device _i in block 29 to which the found cell belongs) and the position of the symbolic synchronization (by the number of this cell in the memory _i ) are set. In the second mode, when only the memory _{1 is used} , only the address of the cell with the minimum content in this block is determined, by which the position of the symbol synchronization is corrected. In block 1 of the algorithm (Fig. 20), the control variable N _{K is} assigned the value N _max , obviously greater than the maximum expected value of the averaged differential power, in addition, 0 is set at the output 4 of block 32 of Fig. 1. Then, the state of the second input of block 32 is analyzed, to which a signal determining the duration of the 1st mode is supplied from the first output of the control unit 16 (line g of the time chart in FIG. 2). In the 1st cycle (left branching) in block 2 of the algorithm (Fig. 20), the values of the variables i _max = N _h and j _max = S are determined that determine the range of the cell search with the minimum content, and in the 2nd cycle (right branching) when only the first memory _{1 is used} , in block 3 j _max = 2 N _gp <S is _taken , since in the tracking mode the search boundaries should be less than in the mode of entering into communication. Then, in block 4, it is initialized to unity (since the numbering of the memory _i in block 29 starts with i = 1), the value i. In block 5 of the algorithm (Fig. 20), the value i is supplied to the second output of block 32 of Fig. 1, which, entering the sixth input of block 29, connects the output of the memory device _i to the first input of block 32. Next, in block 6 of the algorithm, it is initialized to zero (since the addressing of the memory cells of the memory _i in block 29 starts j = 0), the variable j, and then (block 7 of the algorithm), the value is transmitted to the third output of block 32 of figure 1. Since the third output of block 32 is connected through the fifth input of block 29 to the addressing input 5 _{i of the} memory _i (see Fig. 18), the value j determines the address of the memory cell of the memory _i connected to the first input of the block 32. Thus, upon completion of the operation, prescribed algorithm unit 7 (Figure 20), to the first input unit 24 1 is connected content j-th memory cell i-th Dzuu _i. Next, the number at the first input (Bx1) is compared with the control variable N _K , for Bx1 <N _K in block 8 of the algorithm (Fig. 20), the variable N _{K is} assigned a new value N _K = Bx1, and the values i _min and j _min are fixed i and j at which this event took place. Then, in block 9 of the algorithm, the value j is incremented, the condition of incompleteness of the cycle in j (j = j _max -1) is checked, and in the 1st mode of the modem (Bx2 2 0), similar procedures are performed with the variable i (block 10 and checking the condition i = i _max ). This implements the search algorithm for the memory cell of block 29 of FIG. 1 with a minimum value of the average difference power. At the end of the search procedure in blocks 11, 13 and 14 of the algorithm (Fig. 20) in the 1st modem operation mode, the ΔN _{i min} values (determined by formula (9) with i = i _min and corresponding to the best compensating frequency shift), i _min (determining the best compensating frequency shift), and the value jj calculated through j _min (determining the starting address N _on in memory 2 of block 13 of the middle position of the frame from N samples (see Fig. 5) corresponding to optimal symbol-by-symbol synchronization). Then, in block 15 of the algorithm (Fig. 20), the fourth output of block 32 (Fig. 1) is set to 1. This means that the determination of ΔN _min (block 11 of the algorithm) is completed and the value present at the first output can be rewritten to block 34 (figure 1), which is carried out on the positive edge of the signal supplied to the second input of the reverse counter from the fourth output of block 32. The value ΔN _min to the first input of the reverse counter is supplied from the first output of block 32 of figure 1. In the second mode (tracking mode) from the third output of block 32 of FIG. 1, the initial address jj corresponding to the optimal symbol-by-symbol synchronization determined via j _min in the algorithm block 12 is transmitted. (The formula written in block 12 allows you to recalculate j _min , defined in the range 0 ÷ 2 N _g. , To the value jj calculated at this stage of the algorithm, corresponding to the range 0 ÷ S-1).

Thus, through the interaction of the described set of blocks in the prototype, 2 problems are solved: the initial assessment of the sync parameters at the stage of entering into communication (1st mode) and tracking the optimal position of symbol-by-symbol synchronization during the modem's operation (2nd mode). As noted above, for the correct demodulation of the received data, it is necessary in the process of the modem operation (2nd mode) to also monitor the magnitude of the frequency shift introduced by the channel.

This tracking, implemented on the basis of the method illustrated in Fig.6, is carried out using blocks 26, 27, 17, 18, 19, 33 and 34 of the circuit depicted in Fig.1.

In the block 26 for setting the interval of orthogonality using the initial address N _at specified in block 32 and corresponding to the optimal symbol-by-bit synchronization received at its first input, a time interval is formed during which channel signal samples generated in the transmitter during the orthogonality interval are received at the receiver input .

A functional diagram of the orthogonality interval setting unit 26 is shown in FIG. N _nA value supplied to the first input, is written in the address register RA. Rectangular pulses with a frequency of ƒ _d (line a of the time diagram of FIG. 2) are received at the second input from BOC 10, and pulses with a frequency of ƒ _S (a line in the time chart of FIG. 2), each of which sets the SI pulse counter, are received to zero. Each time at the moment of accumulation in the SI of a number equal to N _on , the coincidence circuit of the CCK codes is activated and sets the output RS-trigger to a single state. In this case, the key K is opened, and the pulses are fed to the input of the frequency divider (DF) with the division coefficient N (recall that N is the number of pulses with a frequency ƒ _d that fit in the orthogonality interval). When a positive edge appears at the output of the RF by means of a short-pulse shaper, the RS-trigger is switched to the state “0” and thereby the key K is closed. Thus, a signal corresponding to the synchronized orthogonality interval is generated at the output of the trigger. This signal is supplied to the second (control) inputs of the switches (KM) 17, 18 and 19 (figure 1). The samples of the received signal are received at the first input of KM 19 from the output of the AGC 12, and the reports of carriers with offset frequencies from the first and second outputs of the carrier sampler with offset frequencies 27, the functional diagram of which is shown in FIG. 22, are received at the first inputs of KM 17 and KM 18 .

The digital frequency synthesizers DSC1 and DSC2 included in this circuit have a structure similar to that shown in Fig. 9, with the only difference being that the role of Pr ΔN _i in Fig. 22 is played by the control registers UR1 and UR2. Codes N _UR1 and N _UR2 recorded in these registers are generated using adders Sm1 and Sm2 and sensors of positive and negative increments ± ΔN _D. In this case, N _UR1 = ΔN-ΔN _D and N _UR2 = ΔN + ΔN _D , where ΔN is the number recorded in the reverse counter 29 (Fig. 1) and corresponding to the value of the frequency shift introduced by the radio channel tracked in the receiver. As a result, at the first and second outputs of block 27 (outputs CSCh1 and CSCh2 of FIG. 22), reference harmonic oscillations with frequencies Δƒ ± Δƒ _D appear, which are necessary to implement the frequency shift tracking algorithm illustrated in FIG. 6.

и

этих сигналов (т.е. выделяется несигнальный тон). После этого в блоках вычисления мощности БВМ1 и БВМ2 по правилу (12) вычисляются мощности Р(Δƒ+Δƒ_D) и Р(Δƒ-Δƒ_D) смещенного по частоте несигнального тона, а в узле вычитания УВ в соответствии с алгоритмом, иллюстрируемым фиг.6, вычисляется разностная мощность Р_Δ=Р(Δƒ+ƒ_D)-Р(Δƒ-ƒ_D). В узле деления УД определяется нормированная разностная мощность Р_ΔН=P_Δ/Р_cp, где P_cp - значение средней мощности сигнальных тонов, поступающих на четвертый вход блока 33 с блока 15 (фиг.1). В моменты времени, определяемые поступлением на пятый вход импульсов с третьего выхода БОЧ 10, следующих с частотой ƒ_S тактирования OFDM-символов, посредством схемы перелиси кода СПК в регистр Рг с выхода сумматора См записывается алгебраическая сумма числа, накопленного в Рг ранее, и поступающего с выхода УД значения P_ΔН. Таким образом, в регистре (Рг) осуществляется накопление суммарного значения разностной мощности (при включении модема Рг инициализируется нулем). В узле вычисления модуля (УВМ) определяется модуль числа, накопленного в Рг, который посредством схемы сравнения (СС) сравнивается с некоторым порогом N_y, выдаваемым датчиком «N_y» и задающим объем усреднения. При превышении выходным сигналом УВМ значения N_y СС выдает короткий импульс, поступающий на сигнальный вход коммутатора КМ. На управляющий вход этого узла поступает сигнал с анализатора знака (A3), определяющего знак числа, накопленного в Рг. В зависимости от уровня (ноль или единица) на выходе A3 коммутатор КМ подключает выходной импульс СС к первому выходу или второму выходу блока 33 фиг.1. Кроме того, через элемент задержки ЭЗ, обеспечивающий возможность четкого срабатывания A3 и КМ, выходной импульс СС сбрасывает регистр Рг в ноль. Сигналы с первого и второго выходов блока 33 поступают соответственно на третий и четвертый входы сложения и вычитания реверсивного счетчика 34 фиг.1 и корректируют тем самым хранящееся в нем значение ΔN₁, определяющее частоту компенсируемого частотного сдвига радиоканала.The output signals of the switches 19, 17 and 18 are fed to the first, second and third inputs of the differential power calculation and averaging unit 33, the functional diagram of which is shown in FIG. 23. In the frequency converters IF1 and IF2, the spectrum of the received signal is transferred to the frequencies Δƒ + Δƒ _D and Δƒ-Δƒ _D. In blocks BVDPF1 and BVDPF2, in accordance with formula (11), n-th DFT samples are calculated

and

these signals (i.e. a non-signal tone is highlighted). After that, in the power calculation units BVM1 and BVM2 according to rule (12), the powers P (Δƒ + Δƒ _D ) and P (Δƒ-Δƒ _D ) of the frequency-shifted non-signal tone are calculated, and in the hydrocarbon subtraction unit in accordance with the algorithm illustrated in FIG. 6, the difference power P _Δ = P (Δƒ + ƒ _D ) -P (Δƒ-ƒ _D ) is calculated. In the division unit UD is determined by the normalized differential power P _ΔН = P _Δ / P _cp , where P _cp is the average power of the signal tones arriving at the fourth input of block 33 from block 15 (Fig. 1). At time instants determined by the arrival at the fifth input of pulses from the third output of BOC 10, following with a frequency ƒ _{S of the} clocking of OFDM symbols, the algebraic sum of the number accumulated in Pr earlier and received from the output of the UD value P _ΔН . Thus, in the register (Pr), the accumulated value of the differential power is accumulated (when the modem is turned on, Pr is initialized to zero). In the module calculation unit (UVM), the module of the number accumulated in Pr is determined, which, by means of a comparison circuit (CC), is compared with a certain threshold N _y provided by the sensor “N _y ” and sets the averaging volume. If the output signal of the UVM value N _y SS produces a short pulse arriving at the signal input of the KM switch. The control input of this node receives a signal from the sign analyzer (A3), which determines the sign of the number accumulated in Pr. Depending on the level (zero or one) at the output A3, the KM switch connects the output pulse of the SS to the first output or second output of the block 33 of figure 1. In addition, through the delay element EZ, which provides the possibility of a clear operation of A3 and KM, the output pulse SS resets the register Pr to zero. The signals from the first and second outputs of block 33 are received respectively at the third and fourth inputs of addition and subtraction of the reverse counter 34 of FIG. 1 and thereby correct the value ΔN ₁ stored in it, which determines the frequency of the compensated frequency shift of the radio channel.

Demodulation and evaluation of the values of the received symbols, as well as accurate tracking of the magnitude of the frequency shift introduced by the radio channel are carried out in the prototype as a result of the interaction of blocks 15, 20, 21, 22 and 30 (Fig. 1). As is known [7], simultaneous demodulation in all parallel subchannels in a system with OFDM can be performed by calculating the DFT from a set of N samples { a _k } received during the orthogonality interval. In this case, the calculation of the nth report of the DFT is carried out according to the formula (11), and in total, N samples are calculated in this way (for n = 0 ÷ N-1). Each of these readings is represented by a complex number, the real and imaginary clean of which contain information on the in-phase a _cn and quadrature a _{kv n} components transmitted over this subchannel. To reduce implementation costs, the DFT calculation procedure is performed using the fast Fourier transform (FFT) algorithm [7]. The described operations in the prototype device are implemented in the DFT block 15. At the first input of the DFT block from the third output of the block 32 of Fig. 1, the value of the starting reference address recorded in the memory 2 of the block 13 of the buffer memory corresponding to the optimal symbol synchronization is supplied. At the second input of the block from the fifth output of the control unit 16, a signal is given that sets the time interval for the operation of the DFT block (orthogonality interval) and is shown on line e of the timing diagram in FIG. 2 as a rectangular unit pulse. With the arrival of level “I” at the second input, the DFT unit sequentially issues to the first output the addresses of N samples stored in memory 2 of block 13. These addresses are the result of sequential increment (that is, an increase of 1) in the value of the initial address received at the first entrance. The addresses thus formed from the first output of block 15 through the switch 14, controlled by the signal from the fifth output of the control unit 16, go to the second input of block 13, as a result of which the necessary for demodulation appear (and are fed to input 3 of the DFT 15) there are DFT calculations) samples of the received signal. Note that the connection of the second output of block 13 with the third input of block 15 in Fig. 1 is shown as a thin rather than a composite line because information is transmitted through this connection only in the second modem operation cycle, when only the output is connected to the first output of block 13 one BZU ₁ (see Fig.12). In this case, the composite line shows the connection of several outputs of one block with several corresponding inputs of another block (for example, the connection of the first output of block 13 with the first input of block 25).

In the DFT block 15, based on the N samples of the received signal read in the described manner, the DFT is calculated based on the FFT algorithm. The results of calculating the DFT are fed to the second output of block 15. Since these results are a set of N complex numbers, the second output of block 15 and a number of other similar compounds in Fig. 1 are shown by composite lines. Also, in the DFT block 15, according to rule (12), the power of each signal tone is calculated, and then their arithmetic average value is determined, which is the value of P _cp supplied to the third output of the DFT block.

(выходом i-го подканала в системе с OFDM при приеме n-го OFDM символа), последовательно выполняются две следующие операции:From the second output of block 15, the complex values of the DFT samples determined by expression (1) are fed to the first input of the argument calculation block and the phase rotation of the BVAPF 22. In this block, with every ith sample of the DFT

(by the output of the ith subchannel in an OFDM system upon receipt of the nth OFDM symbol), the following two operations are performed sequentially:

1) its argument is calculated

2) the refined value of the argument of the symbol φ _оi [n] is determined, in which, with the accuracy of the device available, the influence of the untracked inertial tracking system described above for tracking the frequency shift of the phase incursion due to the fast Doppler frequency change in the radio channel is corrected. Correction is carried out in accordance with the expression:

where Δφ _cp [n-1] is the average over all OFDM symbols received the value of the “fast” phase shift calculated on the (n-1) th OFDM clock in the block for calculating the average phase shift of the VSNF 30 supplied to the second input of the argument calculation block and phase rotation 22.

The values of φ _0i [n], (i = 1 ÷ N _T ) are the output signal of block 22 of FIG. 1 and are fed to the first input of the computational informative phase increment calculation unit of the BVIPF 20. To the second input of this block from the second output of the block for evaluating the symbol values and the reference phase BOS 21 receive the values calculated in this block in the previous clock cycle φ _ETi [n-1], (i = 1 ÷ N _T ) of the reference phase (i.e. the phase determined by the integer number of phase shifts used in coding in block 2, which are multiples of 2π / 2 ^q , where q is the multiplicity of the used phase modulation). In block 20 of FIG. 1, informative phase increments Δφ _i [n] of the demodulated signal in the ith subchannel on the nth OFDM clock are estimated. These values are calculated as:

в узле ВЗЭФ вычисляется новое значение эталонной фазы, подаваемой далее на первый вход регистра Рг. Запись же этой величины в Рг (а следовательно, и выдача ее значения на выход 2_i) осуществляется лишь в начале каждого OFDM-такта с приходом на второй вход регистра Рг коротких единичных импульсов с частотой ƒ_S (строка в временной диаграммы фиг.2). В результате на втором выходе БОЗС 21 формируется величина Δφ_ЭТi[n], в конечном итоге необходимая для формирования фигурирующей в (14) оценки «быстрого» допплеровского набега фазы Δφ_cp[n]. В качестве начального условия при n=0 в приемнике и передатчике может быть использовано Δφ_ЭТi[-1]=0.The output signal of block 20 (the set of values Δφ _i [n], (i = 1 ÷ N _T ) is fed to the input of block 21 for estimating the values of symbols and the reference phase and to the second input of the block for calculating the average phase shift of the VSNF 30. Block 21 includes N _{T of} identical nodes connected in parallel, each of which has a block diagram shown in Fig. 24. The signal acting at the input 1 _{i of the} i-th node Δφ _i [n] is fed to the input of the node for evaluating the values of the symbols (SPD) (see Fig. 24). this comparison is carried node values Δφ _i [n] with phase shifts of multiples of 2π / 2 ^q. The revealed in the results Tate this comparison, the reference phase shift Δφ _ETi [n], the least characterized by Δφ _i [n], is taken as the estimate of the true phase shift and its corresponding binary symbols at the output of 1 _i UOZS fed to the modem output for further processing in a decoder channel. From the second output of the SLD, the value Δφ _ETi [n] is supplied to the first input of the calculator of the values of the reference phase (VZEF) and to the third output of block 21 (see Fig. 24). The value of the reference phase Δφ _ETi [n-1], delayed by one OFDM clock, is applied to the second input of the VZEF from the output of the register Rg and in accordance with the expression

in the VZEF node, a new value of the reference phase is calculated, which is then fed to the first input of the register Rg. The recording of this quantity in Rg (and, therefore, the output of its value to output 2 _i ) is carried out only at the beginning of each OFDM clock with the arrival of short unit pulses with a frequency ƒ _S (line in the time diagram of Fig. 2) at the second input of the Rg register. . As a result, the Δφ _ETi [n] value is formed at the second output of the BOSS 21, which is ultimately necessary for forming the estimate of the “fast” Doppler phase incursion Δφ _cp [n] appearing in (14). As an initial condition for n = 0 in the receiver and transmitter, Δφ _ETi [-1] = 0 can be used.

In the block VSNF 30 (figure 1), the arithmetic mean Δφ _cp [n] of the phase error Δ _i [n], calculated as the difference of the quantities Δφ _ETi [n] and Δφ _i [n] arriving at its inputs, is _determined :

The value Δφ _cp [n] is delayed by one OFDM clock cycle and is supplied to the output of block 30 (Fig. 1). Thus, the value Δφ _cp [n-1], which appears in formula (14), is supplied to the second input of block 22.

The disadvantage of this modem is the low noise immunity due to the following circumstances:

1. As can be seen from the above description, the accuracy of the initial estimate of the channel frequency shift in this device is determined by the number of parallel channels of information processing organized in blocks 13, 24, 25, and 31. So, for estimation, to an accuracy of 1 Hz, the frequency shift in the range of ± 100 Hz 200 parallel channels are needed. A real implementation resource limits the ability to obtain an accurate estimate of the frequency shift. This complicates the operating conditions of the inertial tracking system for the frequency shift: it must have a sufficiently wide capture band. As a result, a low-order phase-locked loop device is used as such a system, which is not able to track fluctuations in the frequency shift that occur during communication between objects moving with changing speeds, which ultimately reduces the modem noise immunity when operating under such conditions.

2. The criterion on the basis of which information is found on the degree of adjustment of the synchro-parameters (both symbol-wise synchronization in the “lagging” and “leading” window method of FIG. 5 and the frequency shift in the method illustrated in FIG. 6) is based on a comparison of the powers contained in a single sample of the DFT of the received signal corresponding to a non-signal tone with various modifications of the values of the estimated sync parameters. In this case, the noise acting in the channel directly affects the information obtained in this way. Used in the prototype, the ability to reduce the influence of noise due to averaging the results of the analysis of the degree of adjustment of the sync parameters is limited, because due to the rapid change in time of the parameters of the radio channel, the averaging time cannot be chosen sufficiently large. As a result of this, the quality of symbol-based synchronization is deteriorating, and the efficiency of the inertial tracking system for tracking the frequency shift is reduced, which reduces the noise immunity of the modem.

3. In the process of accurately tracking the fast Doppler shift carried out by blocks 20, 21, 22 and 30 of the circuit shown in figure 1, the phase correction of the i-th received tone in accordance with expression (11) is carried out by using the average over all N _{T to the} accepted tones of the phase shift Δφ _cp [n-1], calculated in node 20. Since the average value of Δφ _cp does not coincide with the specific value of the phase shift in a separate ith subchannel, the accuracy of tracking the fast Doppler shift decreases, which also ultimately worsens interference stability of the device.

4. Due to the inevitable non-ideality of synchronization in the presence of a powerful narrow-band interference concentrated in the radio channels (located in the band of one of the subchannels of the OFDM system), its interfering effect will not only prevent information from being received in this subchannel (which can be corrected using the noise-immunity code in channel decoder), but also turns out to be very significant in other subchannels and will lead to uncorrectable errors. It also reduces the noise immunity of the device.

The present invention solves the problem of increasing the noise immunity of the modem.

The technical result of the invention is to increase the noise immunity of the device, due to a more efficient implementation of the procedures for the initial assessment and tracking of the frequency shift introduced by the channel and symbol-by-symbol synchronization and decision-making on the meaning of the received symbols, as well as eliminating the influence of the spectrum-centered interference falling into the frequency band of one of the parallel subchannels, to signals transmitted over the remaining subchannels.

The specified technical result is achieved by the fact that in the radio modem, which includes four switches, an encoder, a buffer drive, a block of the inverse discrete Fourier transform, a block for adding a guard interval, a numerical array converter in a time sequence forming a filter, a matching block, a tuning sequence generator, a reference frequency block , input unit, automatic gain control unit, buffer storage unit, discrete Fourier transform unit, informative computer calculator unit phase increment, a block for estimating the values of symbols and a reference phase, and a control unit, wherein the first input of the first switch is connected to the input of the modem transmitter, the second input of the first switch is connected to the output of the training sequence generator, the third input of the first switch is connected to the first output of the control unit, and the output the first switch is connected to the input of the encoder, the output of which is connected to the input of the buffer drive; the output of the inverse discrete Fourier transform block is connected to the input of the guard interval adding block; the output of the guard interval adding unit is connected to the first input of the numerical array converter into a time sequence, the second input of which is connected to the first output of the reference frequency unit, the second input of the shaping filter, the second input of the input unit, the fourth input of the buffer storage unit; the output of the numerical array converter into a time sequence is connected to the first input of the shaping filter; the output of the matching unit is connected to the output of the modem transmitter, the second input of the second switch is connected to the fifth output of the control unit and to the second input of the discrete Fourier transform unit, the third input of the second switch is connected to the first output of the discrete Fourier transform unit, the output of the second switch is connected to the second input of the buffer storage block, the third input of the block of reference frequencies is connected to the second input of the unit for evaluating the values of symbols and the reference phase; the first input of the input unit is connected to the input of the modem receiver; the second output of the control unit is connected to the third input of the buffer storage unit; the third input of the discrete Fourier transform block is connected to the first output of the buffer storage unit; the second input of the informative phase increment calculator block is connected to the second output of the symbol value and reference phase estimator, the first output of which is the output of the modem receiver, an additional block for distributing and generating frames with redundancy, two adders, a pilot signal generator, a block of notch filters, narrow-bandpass filter, two frequency converters with complex output, block accumulating adders, decimator, block of accumulation of samples and calculation of discrete conversion Fourier analyzer, frequency shift analyzer, filter, grouping, synchronization and argument calculation unit, signal spectrum transfer frequency shaper, clock sum calculation and processing unit, address register, phase-by-phase synchronization discriminator, tone power dispersion calculation and analysis unit, switching block and encoder a training sequence drive, the output of the buffer storage device being connected to the input of the distribution and framing unit with redundancy, the output of which is connected to the input ohm of the inverse discrete Fourier transform block, the second input of the numerical array converter into the time sequence is connected to the input of the pilot signal generator, the first input of the control unit, the second inputs of both frequency converters with a complex output, a narrow-band pass filter, a notch filter block and a filter, and a third input of the shaper the frequency spectrum of the signal spectrum and the first output of the block of reference frequencies, the output of the shaping filter is connected to the first input of the first adder, the second input to It is connected to the first output of the pilot signal generator and the third input of the first frequency converter with a complex output, the output of the first adder is connected to the input of the matching unit, the second output of the reference frequency unit is connected to the second inputs of the accumulating adders block, the decimator, the accumulation unit and the discrete conversion calculation Fourier and frequency shift analyzer, the third output of the reference frequency block is connected to the second inputs of the frequency spectrum shaper of the signal spectrum, address register, control unit lane and the unit for evaluating the values of symbols and the reference phase and the fourth input of the grouping unit, synchronizing and calculating the argument, the second output of the pilot signal generator is connected to the fourth input of the first frequency converter with a complex output, the output of the input unit is connected to the first input of the notch filter block, the third input which is connected to the output of the block for calculating and analyzing the dispersion of the power of tones, the output of the notch filter unit is connected to the input of the automatic gain control unit, the output of the automatic gain control is connected to the first inputs of the narrow-bandpass filter and filter, the output of the narrow-bandpass filter is connected to the first input of the first frequency converter with a complex output, the output of which is connected to the first input of the accumulator adders block, the output of the accumulator adders block is connected to the first input of the decimator, the output of the decimator connected to the first input of the sample accumulation and discrete Fourier transform calculation node, the first output of which is often connected to the first input of the analyzer shift, the second output of the block of accumulation of samples and the calculation of the discrete Fourier transform is connected to the third input of the frequency shift analyzer, the first output of the frequency shift analyzer is connected to the fourth input of the shaper of the frequency transfer of the signal spectrum, and the second to the third input of the control unit, the filter output is connected to the first the input of the second frequency converter with a complex output, the third and fourth inputs of which are connected respectively to the first and second outputs of the spec RA, the output of the second frequency converter with a complex output is connected to the first input of the third switch, the second input of the third switch is connected to the sixth output of the control unit, the output of the third switch is connected to the first input of the buffer storage unit, the first output of the buffer storage unit is connected to the first input of the calculation unit and processing the clock sum, the second output of the buffer storage unit is connected to the second input of the block computing and processing the clock sum, the first input of the second switch is connected to the first m is the output of the synchronization sum calculation and processing unit, the first input of the fourth switch is connected to the third output of the synchronization sum calculation and processing unit, the second input of the fourth switch is connected to the output of the second adder, the third input of the fourth switch is connected to the third output of the control unit, the third input of the synchronization calculation and processing unit and the fifth input of the frequency spectrum transfer former of the signal, the output of the fourth switch is connected to the first input of the address register, the first input of the discrete transform block Fourier transform is connected with the second inputs of the second adder and phase discriminator of symbol-based synchronization, the fourth input of the clock calculation and processing unit and the output of the address register, the second output of the discrete Fourier transform unit is connected to the first input of the grouping, synchronization and argument calculation block and the input of the dispersion calculation and analysis block power of tones, the third output of the discrete Fourier transform block is connected to the fifth input of the synchronization sum calculation and processing unit, the second input of the grouping block arithmetic, synchronization and calculation of the argument is associated with the fifth output of the synchrosum sum calculation and processing unit and the first input of the signal spectrum transfer frequency shaper, the third input of the grouping, synchronization and argument calculation unit is connected to the second input of the informative phase increment unit, the output of the grouping, synchronization and calculation unit the argument is connected to the first input of the block of calculators of the informative phase increment, the first input of the block for estimating the values of symbols and the reference phase is connected to the output m of the switching unit, the second output of the synchronization calculation and processing unit is connected to the first input of the phase discriminator of the symbol synchronization, the fourth output of the synchronization calculation and processing unit is connected to the fourth input of the control unit, the first input of the second adder is connected to the output of the phase symbol discriminator, the output of the informative calculator unit phase increment is connected to the first input of the switching unit, the second input of the switching unit is connected to the output of the drive encoder three-way sequence, the third input of the switching unit is connected to the first output of the control unit, the input of the encoder-storage of the training sequence is connected to the output of the generator of the training sequence.

The description of the invention includes 38 figures.

The figure 1 shows a functional diagram of a prototype device.

The figure 2 presents time diagrams illustrating the operation of the prototype.

In figures 3-24 shows the algorithms and functional diagrams of individual nodes that are part of the prototype device.

The figure 25 shows a functional diagram of the invention.

The figure 26 presents time diagrams illustrating the operation of the invention.

In figures 27-38 shows the algorithms and functional diagrams of individual nodes that are part of the invention.

Functional diagram of the invention is presented in Fig.25. It includes four switches (CM) 1, 25, 27, 28, encoder 2, buffer storage (BN) 3, block 4 distribution and formation of frames with the addition of redundancy (BRFKI), block 5, the calculation of the inverse discrete Fourier transform (ODPF) , block 6 adding a protective interval (BDZI), a converter 7 of a numerical array into a time sequence (ППМВП), a forming filter (ФФ) 8, two adders 9 and 33, a block 10 matching (BS), the generator 11 training sequence (GNP), block 12 reference frequencies (BOC), the generator 13 pilot signal (GPS), the input unit (WB) 14, block 15 notch filters (BRF), block 16 automatic gain control (AGC), narrow-band pass filter (UPF) 17, two frequency converters with complex output (PCHC) 18 and 24, block 19 accumulating adders (BNS) , decimator 20, block 21 of the accumulation of samples and the calculation of the DFT (NADPF), the analyzer 22 frequency shift (ASF), filter 23, the buffer storage unit 26 (BZB), block 29 of the discrete Fourier transform (FFT), block grouping, synchronization and calculation of the argument (BGSVA) 30, block 31 of the evaluation of the values of the characters and the reference phase (BOS), p address histogram (RA) 32, signal spectrum transfer frequency shaper (FSPSS) 34, synchro sum calculation and processing unit (BBS) 35, phase-by-phase synchronizer (FPSS) 36, block informative phase increment calculators (BVIPF) 37, switch block (KB ) 38, control unit 39, control unit 40 for calculating the dispersion of power of tones (BVDMT), and a tuning sequence encoder storage device (KNNP) 41, the first input of switch 1 being connected to the input of the modem transmitter, the second input of this switch connected to the output of the GNP 11 and the input of KNNP 41, the third input of the switch 1 is connected to the first output of the BU 39 and the third input of the switch unit 38, the output of the switch 1 is connected to the input of the encoder 2, the output of the encoder 2 is connected to the input of the BN 3, the output of the BN 3 is connected to the input of the BRFKI 4, the output of which is connected to the input of the ODF 5, the output of block 5 is connected to the input of the BDZI 6, the output of the BDZI 6 is connected to the first input of the PCMVP 7, the second input of which is connected to the first output of the BOC 12, with the input of the GPS 13, the first input of the BU 39, the second inputs of the WB 14, BRF 15, UPF 17, ПЧКВ 18 and 24, ФФ 8, ПЧМВП 7, filter 23, third input ФППСС 34 and fourth input БЗБ 26, output ПММВП 7 is connected to the first input of ФФ 8, the output of ФФ 8 is connected to the first input of adder 9, the second input of which is connected with the first output of GPS 13 and the third input of ПЧКВ 18; the output of the adder 9 is connected to the input of the matching unit 10, the output of the BS 10 is connected to the output of the modem transmitter, the second output of the BOC 12 is connected to the second inputs of the decimator 20, the block 21 of the accumulation of samples and the calculation of the DFT, ASF 22 and BNS 19, the third output of the BOC 12 is connected to the second inputs of the BOZS 31, FCHPSS 34, PA 32, BU 39 and the fourth input of the BGSVA 30, the second output of the GPS 13 is connected to the fourth input of the PChV 18, the first input of the WB 14 is connected to the input of the modem receiver, the output of the WB 14 is connected to the first input of the BRF 15, the third input of the BRF 15 is connected to the output of the BVDMT 40, the output of the BRF 15 is connected to the input of the AR 16, the output of the AGC 16 is connected to the first inputs of the UPF 17 and the filter 23, the output of the UPF 17 is connected to the first input of the PCHF 18, the output of the PCHC 18 is connected respectively to the first input of the BNS 19, the output of the BNS 19 is connected to the first input of the decimator 20, the output of the decimator 20 is connected with the first input of NODPF 21, the first output of which is connected to the first input of ASF 22, the second output of block 21 is connected to the third input of ASF 22, the first output of ASF 22 is connected to the fourth input of FSPS 34, the second output of ASF 22 is connected with the third input of BU 39, output the filter 23 is connected to the first input PPCV 24, the third and fourth inputs ChKV 24 are connected, respectively, with the first and second outputs of FCHPSS 34, the output of FKHV 24 is connected to the first input of KM 25, the second input of KM 25 is connected to the sixth output of BU 39, the output of KM 25 is connected to the first input of BZB 26, the second input of which is connected to the output of KM 27, the third input of block 26 is connected to the second output of the control unit 39, the first output of block 26 is connected to the first input of the BVOS 35 and the third input of the DFT 29, the second output of the BZB 26 is connected to the second input of the BVOS 35, the first input of the KM 27 is connected to the first output of the BVOS 35 , the second input of KM 27 is connected to the second input of the DFT 29 and the fifth output of BU 39, the third KM 27 is connected to the first output of the DPF 29, the first input of KM 28 is connected to the third output of the BVOS 35, the second input of KM 28 is connected to the output of the adder 33, the third input of the KM 28 is connected to the third output of the BV 39, the third input of the BVOS 35 and the fifth input 34, the output of the KM 28 is connected to the first input of the RA 32, the first input of the DPF 29 is connected to the output of the RA 32, the second inputs of the adder 33 and the FDPS 36 and the fourth input of the BVOS 35, the second output of the DPF 29 is connected to the first input of the BGSVA 30 and the input of the BVDMT 40, the third output of the DFT 29 is connected to the fifth input of the BVOS 35, the second input of the BGSVA 30 is connected to the fifth output of the BVOS 35 and the first input of the FFPSS 34, the third input of the BSVSA 30 is connected to the second output of the BVPS 31 and the second input of the BVIPF 37, the output of the BSVS 30 is connected to the first input of the BVPS 37, the first input of the BPS 31 is connected to the output of KB 38, the first output of the BPS 31 is the output of the modem receiver the second output of BVOS 35 is connected to the first input of FDPS 36, the fourth output of BVOS 35 is connected to the fourth input of BU 39, the sixth input of BVOS 35 is connected to the fourth output of BU 39, the first input of adder 33 is connected to the output of FDPS 36, the output of BVIPF 37 is connected to the first input KM 38, the second input of KB 38 is connected to the output of KNNP 41.

The operation of the device is as follows. The data to be transmitted is fed to signal input 1 of switch 1, to the second (signal) input of which a digital signal is supplied from the output of the generator of the GNP 11 training sequence. The operation of the switch is controlled by the signal received at its third input from the first output of control unit BU 39, shown on the line to the timing diagram shown in FIG. In the process of entering into communication (1st modem operation mode), a training sequence (input 2) is connected to the switch output. In the data transfer mode (2nd modem operation mode), the signal “1” at the third input of the KM 1 switch ensures that the data to be transferred to the first input is connected to its output. The output signal of the commutator KM 1 is fed to the input of the encoder 2. As in the prototype, the described modem assumes the use of differential multiple phase modulation with a quadrature implementation of the modulator and demodulator. At the same time, the functions, construction and interaction of the modem encoder 1 and the buffer drive that are part of the transmitter are completely the same as those of the same nodes 2 and 3 of the prototype device, and are described in detail above (when describing the prototype).

Block distribution and formation of frames with the introduction of redundancy 4 in principle also performs the same functions as block 23 in the circuit of figure 1 of the prototype device, namely:

массива из N/2 комплексных чисел (при выполнении условия (4));1) the formation of the accumulated in BN 3 aggregate N _T , information complex symbols

an array of N / 2 complex numbers (if condition (4) is satisfied);

, формируемыми по правилу (2).2) addition of the N / 2-point array formed in Clause 1 to the N-point array with additional N / 2 characters

formed by rule (2).

However, in block 4 of the present invention, in contrast to block 23 of the prototype, the first of the two operations is performed in a slightly different way: tones not used due to condition (4) are filled not with zeros (as in the prototype), but with characters duplicating N _T information signs. Thus, redundancy is introduced into the transmitted signal: one information symbol is transmitted in two (or possibly more, depending on the ratio of N _T and N) parallel subchannels.

The functions performed, the construction and interaction of the ODLP calculation unit 5, the block for adding the guard interval 6, the converter of the numerical array into the time sequence 7, and the shaping filter 8, by means of which further processing of the information in the modem transmitter is carried out, are completely the same as with the same type of device nodes - prototype, and are detailed in the description of the prototype.

The samples of the signal from the output of block 8 are fed to the first input of the adder 9. At the second input of this adder from the first output of the generator of the GPS pilot signal 13, samples of the generated harmonic oscillation (pilot signal) x _ps (kΔt) = cos 2πƒ _ps kΔt, spectral line which is located at a frequency of ƒ _ps near the lower limit of the passband of the telephone channel and does not overlap with the OFDM signal spectrum generated by the filter 8. In the adder 9, the samples present at its first and second inputs are added. The output signal of the adder is fed to the input of the matching unit 10, in which its digital-to-analog conversion and leveling are performed. The output signal of block 10 is transmitted to the channel.

The received signal from the output of the communication channel is fed to the first input of the input unit 14, to the second input of which from the first output of the block 12 of the reference frequencies are clock pulses, following with a sampling frequency ƒ _d . At this node, filtering and conversion of the continuous input signal to digital is carried out, which then goes to the first input of the notch filter unit (BRF) 15. A functional diagram of this unit is shown in Fig. 27.

It includes a set of N parallel-connected RF filters _i (i = 1 ÷ N _T ), each of which is configured to suppress a portion of the spectrum of the input signal in the frequency band of the ith subchannel. The second input of the block of notch filters 15 receives pulses following with a frequency of ƒ _d and clocking the operation of digital filters of the RF _i (i = 1 ÷ N _T ). The outputs of these filters are connected to the inputs of the CM switch (see Fig. 27), in addition, one of the CM inputs is directly connected to the first input of block 15. Switching is controlled by a signal fed to the third input of the block, which is formed in the power calculation and analysis block tones of BVDMT 40. The rules for the formation of this signal and the purpose of the notch filters will be explained below. In the meantime, we note that in the connection mode (1st modem operation cycle), the control signal has a value that ensures switching of the output of block 15 n mediocre with his first entrance.

The output signal of block 15 is fed to the input of the AGC 16, in which the level of the received signal is normalized.

имеющий частоту

где ƒ_чс - значение канального частотного сдвига. Этот сигнал далее подается на первый вход преобразователя частоты с комплексным выходом ПЧКВ 18, функциональная схема которого показана на фиг.28.The AGC output signal y _pr (kΔt) is supplied to the first input of a narrow-band bandpass filter 17, the second input of which receives clock pulses with a frequency of ƒ _d . The passband of this filter Δƒ _upf = 2ƒ _{part is} limited to ƒ _ps -ƒ _part (lower limit) and) _ps + ƒ _part (upper limit), where ƒ _part is the absolute value of the maximum estimated frequency shift introduced by the radio channel. Note that ƒ _upf <ƒ _in / 2M, which will subsequently allow M-fold decimation of the transformed symbol. In addition, the narrow passband of UPF 17 contributes to a significant reduction in the power of fluctuation noise. By means of a filter 17, a pilot signal is extracted from the signal y _pr (kΔt)

having a frequency

where ƒ _hs is the value of the channel frequency shift. This signal is then fed to the first input of the frequency converter with a complex output PPCV 18, the functional diagram of which is shown in Fig. 28.

, узел сложения (УС) и узел вычитания (УВ). На второй вход этой схемы с первого выхода БОЧ 12 подаются импульсы с частотой ƒ_d, тактирующие работу ПГ. На третий вход с выхода 1 ГПС поступают отсчеты используемого в передатчике пилот-сигнала x_пс(kΔt)=cos2πƒ_псkΔt, а на четвертый вход - отсчеты находящегося с ним в квадратуре сигнал

. Полагая сигналы

и

реальной и мнимой частями комплексного аналитического сигнала

, а синфазный S_пс(kΔt) (на котором присутствует задержанный входной сигнал) и квадратурный выходы

преобразователя Гильберта аналогичными составляющими сигнала

, правило получения сигналов

и

на выходах ПЧКВ 18 можно описать выражениями (знак * означает комплексное сопряжение):It includes a Hilbert transducer (GH), four multipliers

, the addition node (CSS) and the subtraction node (HC). The second input of this circuit from the first output of the BOC 12 is supplied with pulses with a frequency ƒ _d , clocking the operation of the SG. The third input from the GPS output 1 receives the samples of the pilot signal x _ps (kΔt) = cos2πƒ _ps kΔt used in the transmitter, and the fourth input receives the samples of the signal located with it in quadrature

. Putting Signals

and

real and imaginary parts of a complex analytical signal

, and in-phase S _ps (kΔt) (on which there is a delayed input signal) and quadrature outputs

Hilbert transducer with similar signal components

, the rule for receiving signals

and

at the outputs of ПЧКВ 18 can be described by the expressions (the * sign means complex conjugation):

and

In accordance with these expressions and built the circuit shown in Fig.

на

эквивалентно переносу спектра сигнала

вниз на величину ƒ_пс, получаем, что выходной сигнал ПЧКВ 18Given the property of the frequency shift of the Fourier transform, namely, that the multiplication of the signal

on

equivalent to signal spectrum transfer

down by ƒ _ps , we get that the output signal ПЧКВ 18

can be considered (excluding noise) as a complex harmonic sequence with a frequency equal to the value of the frequency shift introduced by the radio channel ƒ _hs . Note that _{величина hs} can be either positive or negative, which will affect the sign of the component

, содержащий синфазную S_ƒчс и квадратурную

составляющие, поступает на вход блока 19 накапливающих сумматоров, схема которого показана на фиг.29. Блок содержит два параллельно включенных накапливающих сумматора НС1 и НС2, на первые входы которых поступают отсчеты сигналов

и

.From output ПЧКВ 18 complex signal

containing in-phase S _{ƒ hs} and quadrature

components, is fed to the input of the accumulating adders block 19, a diagram of which is shown in Fig. 29. The block contains two parallel-connected accumulating adders НС1 and НС2, the first inputs of which receive signal samples

and

.

After the accumulation in each of the adders of the sum of M samples from the third input of block 19, an impulse arrives at the second inputs of the nodes HC1 and HC2 through the delay element EZ, setting them to the zero state. (The repetition rate of the pulses ƒ _DM arriving at the second input is related to the sampling frequency ƒ _{in the} ratio: ƒ _DM = ƒ _d / M.) The presence of the delay element of the EZ makes it possible to read the accumulated amounts in HC1 and HC2 before they are reset (zeroing). The accumulative accumulators used in block 19 can be considered as non-recursive digital filters, with the impulse response h (kΔt) of the form of a rectangular window:

и

комплексного сигнала

Вместе с тем, накопление сумм отсчетов приводит к усреднению наложенного на них аддитивного шума канала и тем самым способствует уменьшению его мешающего влияния, что в конечном итоге приводит к повышению помехоустойчивости предлагаемого устройства.It can be shown that the frequency response of such a filter with the appropriate choice of M has the form in which in the region of possible values of the frequency shift of the BNS 19 introduced by the radio channel, only a slight change (decrease) in the amplitude of the discrete harmonic components arriving at its input

and

integrated signal

At the same time, the accumulation of the sums of the samples leads to the averaging of the additive noise of the channel imposed on them and thereby reduces its interfering effect, which ultimately leads to an increase in the noise immunity of the proposed device.

The complex output signal of the BNS 19 is supplied to the first input of the decimator 20, which consists of two switches with integrated control inputs connected to the second input. The pulses arriving at the control input with a frequency of f _dm provide the reading of the sums accumulated at that moment in the adders of block 19 by connecting the complex output of this block to the complex first input of the sample accumulation node and calculating the NLDPF 21. Thus, decimation is performed with the frequency conversion coefficient M.

и

которые можно рассматривать как реальную и мнимую части комплексного сигнала:In block 21 in the 1st cycle of the modem, the initial accumulation of N _h from the signal accounts

and

which can be considered as real and imaginary parts of a complex signal:

, для выполнения которого целесообразно использовать алгоритм БПФ. Далее в процессе работы модема на каждом такте Δt_ДМ принимается новый отсчет сигнала

поступающий на первый вход НОДПФ 21, и темсамым производится обновление одного значения накопленного массива, после чего вновь вычисляется его ДПФ.where Δt _DM = 1 / ƒ _DM is the sampling step after decimation. The value of N _hs is selected from the condition of ensuring the necessary absolute error Δƒ _{hs of} determining the value of ƒ _{hs of the} frequency shift in the radio channel and is calculated as N _hs = 2ƒ _hh / Δƒ _hs . Upon completion of the initial accumulation, the DFT signal is calculated

, for the implementation of which it is advisable to use the FFT algorithm. Further, during the operation of the modem at each clock cycle Δt _DM , a new signal count is received

arriving at the first input of NODPF 21, and the same value is updated one value of the accumulated array, after which its DFT is again calculated.

The operation algorithm of block 21 is shown in FIG. The algorithm is launched by each pulse with a frequency ƒ _DM entering the second input. At the beginning, the value of the variable F is analyzed - the “first pass flag”. Since when the modem is turned on, its value is not initialized, initially F ≠ F _counter and the right side of the algorithm is executed (initial accumulation stage). Its execution begins by analyzing the value of another flag - the variable F1. When the algorithm is first launched, the condition F1 ≠ F1 _counter is fulfilled, which makes it possible to assign the variable i in block 5 of the algorithm, by which the accumulated samples of the input signal are calculated, a zero value. In addition, in block 5 of the algorithm, the variable F1 is assigned the value F1 _counter , after which, at subsequent runs of the algorithm, the variable i is not initialized and stores the value equal to the number of the last count entered in the NLDPF 21. In block 6 of the algorithm of FIG. 30, the input samples are recorded in the corresponding memory cells, and in block 7, the number of input samples is counted, and, in addition, a second value is maintained at the second output of the NODPF 21, which indicates that the process is currently being performed initial accumulation of samples. Upon completion of this process (with i = N _on ) in block 8, the flag F is assigned the value F = F _counter , and in block 9, the DFT of the signal is calculated, the readings of which are fixed in the arrays X _Re and X _Im , which completes the execution of the algorithm. The next run in connection with the conditions F = F _counter operates the left part of the algorithm (blocks 1-4). In block 1, the variable i of the cycle of overwriting the contents of memory cells is initialized to zero (blocks 2, 3) and a unit is sent to the second output, indicating that the process of initial accumulation of samples is completed. At the end of the overwrite cycle in block 4, the values of the complex signal counting newly received at the first input of the NLTPF 21 are recorded in the first cells of the X _Re and X _Im arrays, after which the DFT is again calculated in block 9 of the algorithm.

, имеющего наибольшую мощность

. Далее в зависимости от выполнения условия n_max≤<N_чс/2 оценивается, положительной или отрицательной является величина частотного сдвига ƒ_чс и по формулам, приведенным в блоках 2 и 3 алгоритма (фиг.31), вычисляется ее алгебраическое значение. (Δƒ_чс=2ƒ_чст/N_чс - интервал между частотами соседних гармоник ДПФ). Далее проверяется условие F=F_контр, невыполнение которого означает, что прохождение по основному телу цикла осуществляется первый раз и оценка ухода частоты в предыдущем такте ƒ_{чс пред} не выполнялась. В этом случае в блоке 4 алгоритма осуществляются присваивания ƒ_{чс пред}=ƒ_чс, F=F_контр и на втором выходе АЧС 44 поддерживается нулевой уровень (блок 5 алгоритма фиг.31). В случае если F=F_контр, производится проверка соотношения |ƒ_чс-ƒ_{чс пред}|<ƒ_пop, где ƒ_пор - пороговое значение, определяемое из соотношения частоты ƒ_ДМ и предполагаемой скорости изменения частотного сдвига в радиоканале. При невыполнении этого условия делается вывод о том, что результат определения частотного сдвига в данном такте является ошибочным и он не фиксируется. Это позволяет снизить вероятность ошибочного приема символов в условиях импульсных помех и тем самым повышает помехоустойчивость модема. В том случае если данное условие выполняется, в блоке 7 алгоритма (фиг.31) вычисляется значение ΔN_чс, которое нужно занести в качестве начального условия в соответствующий регистр ФЧПСС 34, чтобы с ее выхода считывать отсчеты гармонического колебания с частотой ƒ_чс. Величина ΔN_чс определяется как:Complex DFT samples from the first output of the NODPF are fed to the first input of ASF 22. In this block, based on the analysis of the calculated DFT, an approximate (with accuracy determined by the size of N _hf DFT) _approximate determination of the frequency shift ƒ _{hs of the} spectrum of the signal _taking place in the channel is _performed , and a logical signal (output 2), necessary to synchronize the functioning of other nodes of the modem. The ASF 22 operation algorithm is shown in FIG. The algorithm is launched by each pulse entering the second input with a frequency of ƒ _DM . The algorithm begins by checking the condition Bx3 = 1, the failure of which indicates that in block 21 (Fig.25) there is a process of initial accumulation of samples and the DFT has not yet been calculated. Therefore, at the second output of the ASF, “0” is set and the execution of the algorithm ends. With a positive test result, in block 1 of the algorithm, the number n _{max of the} DFT count is determined

having the greatest power

. Further, depending on the fulfillment of the condition, n _max ≤ <N _h / 2 is estimated whether the frequency shift ƒ _h is positive or negative, and its algebraic value is calculated by the formulas given in blocks 2 and 3 of the algorithm (Fig. 31). (Δƒ _hs = 2ƒ _hh / N _hs - the interval between the frequencies of adjacent harmonics of the DFT). Next, the condition F = F _{counter is} checked, the non-fulfillment of which means that the passage through the main body of the cycle is carried out for the first time and the frequency _drift in the previous clock cycle was not performed _before . In this case, in block 4 of the algorithm, assignments are made ƒ _{hs pre} = ƒ _hs , F = F _counter and at the second output of ASF 44, the zero level is maintained (block 5 of the algorithm of Fig. 31). If F = F is _counter , the relationship | ƒ _hh -ƒ _{hh before} | <ƒ _{pop is checked} , where ƒ _pore is the threshold value determined from the ratio of the frequency ƒ _DM and the expected rate of change of the frequency shift in the radio channel. If this condition is not fulfilled, it is concluded that the result of determining the frequency shift in this clock cycle is erroneous and is not fixed. This reduces the likelihood of erroneous reception of characters in the conditions of impulse noise and thereby increases the noise immunity of the modem. In the event that this condition is met, in block 7 of the algorithm (Fig. 31), the ΔN _hs value is calculated, which must be entered as an initial condition in the corresponding register of the FSFSS 34 in order to read harmonic oscillation samples with a frequency of ƒ _hs from its output. The value of ΔN _hs is defined as:

ΔN _hs = ƒ _hs Δt = ƒ _hs / ƒ _d .

After that, in block 7 of the algorithm (Fig. 31), the found value ΔN _hs is issued to the first output of ASF 22; on the second output of ASF, a unit is set (indicating that the process of initial estimation of the frequency shift is completed) and _{reassignment of} ƒ _{hs pre} = ƒ _{hs is performed} .

The advantage of the proposed system of the initial estimation of the channel partial shift (the set of blocks 17-22 of the circuit shown in Fig. 25) is that the required estimation accuracy can be achieved here by choosing the necessary DFT size, which does not require as much implementation costs as in prototype device. (With the same level of implementation complexity, the accuracy of the assessment in the proposed device will be higher). This allows you to reduce the requirement for the capture bandwidth of the frequency shift tracking tracking system in the operating mode and use a third-order digital phase synchronization system as such, which allows tracking frequency shift fluctuations, which ultimately increases the modem noise immunity.

The signal from the second output of the ASF, shown on line g of the timing diagram of the proposed device (see Fig. 26), is fed to the third input of the control unit 39, the second input of which from the third output of the BCF 12 receives short pulses with a frequency of ƒ _S = 1 / T _S where T _S is the duration of the OFDM symbol. Using these signals, a signal is generated at the sixth output of the control unit on line d of the timing diagram of FIG. 26, the transition to a single state occurs with the arrival of the first pulse after a similar transition at the third input of the control unit (line in the timing diagram of FIG. 26) with a frequency of ƒ _S. This signal from the sixth output of the control unit is fed to the second (control) input of KM 25. A unit at the second input of the switch allows the complex output signal to pass to the first input of the BZB 26:

a frequency converter with a complex output ПЧКВ 24. The circuit ПЧКВ 24 is completely similar to the circuit ППЧВ 18, shown in Fig.28. At the first input of block 24, the output signal y (kΔt) of the digital filter 23 is received, which removes the pilot signal from the spectrum of the output signal of the AGC 16 (pulses with a frequency of ƒ _d clocking its operation are received at the second input of the filter 23. These pulses are fed to the second input PKChV 24 and they clock the operation of the Hilbert transducer included in its composition). The third and fourth inputs of the PCHF 24 from the first and second outputs of the PSFSS 34 are fed cosine and sinusoidal samples, the frequency of which is equal to the estimate of the frequency shift introduced by the communication channel. (At the moment of operation of the device in question, this frequency is equal to the value ƒ _hs defined in ASF 22).

Thus, the search begins for the optimal position of symbol-by-symbol synchronization. Before describing the functioning and interaction of the nodes involved in this procedure, we consider the principle underlying this search.

On Fig shows a time interval equal to two durations of the OFDM symbol, taken in the absence of symbol-by-symbol synchronization. On this interval, the nth OFDM symbol containing S samples is completely fit and there are parts of the (n + 1) th and (n-1) th symbols (in total also containing S samples). If you calculate the sum of the form:

then the value | -B (l) | will be maximum in the case when the number l of the initial reference in the sum (16) coincides with the number of the initial reference of the nth OFDM symbol shown in Fig. 32. Indeed, in this case, the factors involved in the formation of N _{communication} terms of the sum (16) belong to the same OFDM-symbol and according to the rule illustrated in Figure 3 forming OFDM-signal in the absence of a frequency offset, channel distortions and other noise for their fair ratio:

Moreover, all terms (16) are valid and have the same signs.

If the number l is such that the beginning of the summation does not coincide with the beginning of the full OFDM symbol falling within the time interval shown in Fig. 32, the individual summands (16) are complex and can have different signs, since the constituent factors belong to different OFDM- symbols, as a result of which the value of the modulus of the sum (16) decreases.

The presence of a frequency shift ƒ _hs in the radio channel leads to the fact that relation (17) changes as follows:

In this case, expression (16) is transformed to the form:

Where

As a result, the property of the maximum modulus of the sum (16) at l corresponding to the beginning of the OFDM symbol is preserved, in addition, by calculating the argument of the accumulated sum, one can obtain information on the value of the frequency shift in the channel:

where ω _hs = 2πƒ _hs ; NΔt <= T; T is the interval of orthogonality.

и определении значения l, максимизирующего модуль функции B(l). При этом аргумент вычисленной суммы содержит информацию о мгновенном (на интервале OFDM-символа) значении вносимого каналом частотного сдвига. Преимуществом данного подхода по сравнению с реализованным в прототипе методом «отстающего» и «опережающего» окна заключается в том, что информация о значениях синхропараметров получается не на основе анализа одного отсчета, а по итогам накопления суммы отсчетов, что приводит к усреднению шума канала и в конечном итоге повышает помехоустойчивость модема. Дополнительное снижение влияния шума может быть достигнуто либо путем вычисления В(l) на нескольких OFDM-символах с последующим усреднением результатов (в режиме вхождения в связь) либо путем фильтрации выходного сигнала такого фазового дискриминатора в системе фазовой синхронизации.Thus, the task of symbol-by-symbol synchronization is reduced to calculating, in accordance with (16), the quantities B (l) for all

and determining a value l maximizing the modulus of the function B (l). The argument of the calculated sum contains information about the instantaneous (in the interval of the OFDM symbol) value of the frequency shift introduced by the channel. The advantage of this approach compared to the “lagging” and “leading” window methods implemented in the prototype is that information on the values of the sync parameters is obtained not based on the analysis of one sample, but based on the results of the accumulation of the sum of samples, which leads to averaging of the channel noise in ultimately increases the noise immunity of the modem. An additional reduction in the influence of noise can be achieved either by calculating B (l) on several OFDM symbols with subsequent averaging of the results (in the communication mode) or by filtering the output signal of such a phase discriminator in a phase synchronization system.

The practical implementation of the above approach in the proposed device is carried out in the process of interaction of the buffer storage unit BZB 26 and the unit for calculating and processing the sync sum BVOS 35.

(БЗУ1) и мнимой

(БЗУ2) частей комплексного сигнала

. Функциональная схема каждого из этих блоков имеет вид, показанный на фиг.13, алгоритм их функционирования представлен на фиг.14. Сигнал, поступающий на третий вход БЗБ 26 с выхода 2 БУ 39, показан на строке е временной диаграммы фиг.26. Подробное описание схемы и алгоритма представлены при рассмотрении одноименных узлов (полностью идентичных БЗУ1 и БЗУ2) устройства-прототипа. Отметим лишь, что из анализа работы схемы и алгоритма можно заключить, что начиная со второго тактового периода OFDM сигнала после установления «1» на выходе 6 БУ 39 в ЗУ2 узлов БЗУ1 и БЗУ2 содержится 2S отсчетов, соответствующих длине двух OFDM-символов в ситуации, изображенной на фиг.32. При этом влияние частотного сдвига канала на значения этих отсчетов в значительной степени (определяемой точностью оценки сдвига в АЧС 22) устранено в ПЧКВ 24.Functional diagram BZB 26 is shown in Fig.33. It includes two identical buffer storage nodes BZU 1 and BZU 2, designed for storing, storing and issuing real readings

(BZU1) and imaginary

(BZU2) parts of the complex signal

. The functional diagram of each of these blocks has the form shown in Fig.13, the algorithm of their functioning is presented in Fig.14. The signal supplied to the third input of the BZB 26 from the output 2 of the BU 39 is shown on line e of the timing diagram of Fig.26. A detailed description of the scheme and algorithm is presented when considering the nodes of the same name (completely identical to BZU1 and BZU2) of the prototype device. We only note that from an analysis of the operation of the circuit and the algorithm, we can conclude that starting from the second clock period of the OFDM signal after setting “1” at the output 6 of the BU 39 in the memory 2 of the nodes BZU1 and BZU2 contains 2S samples corresponding to the length of two OFDM symbols in a situation depicted in Fig. 32. At the same time, the influence of the channel frequency shift on the values of these samples to a large extent (determined by the accuracy of the shift estimate in ASF 22) is eliminated in PCRF 24.

The procedure for finding the starting address of the nth OFDM symbol (i.e., establishing symbol-by-symbol synchronization, see Fig. 32) in the 1st modem operation cycle (communication mode) is implemented in the sync sum calculation and processing unit 35, the operation algorithm of which presented in Fig. 34.

The algorithm is triggered by short single pulses generated at the fourth output of the control unit 39 (line 3 of the timing diagram of Fig. 26), which are fed to the sixth input of the BVOS 35. As can be seen from the diagram, these pulses are delayed in time relative to the pulses at the third output of the BOC 12, which follow with a frequency ƒ _S = 1 / T _S (line in the time diagram of FIG. 26), by the value of the sampling step Δt = 1 / ƒ _d . At the same time, their arrival at the input 6 of the BVOS starts only after the formation of the first frequency shift estimate is completed in ASF 22.

, служащих для накопления значений суммы (16) при разных значениях начального адреса. Также в этом блоке алгоритма присваивается нулевое значение переменной n, используемой в алгоритме для подсчета числа OFDM-символов, на которых осуществляется усреднение синхросуммы; устанавливается в «0» сигнал на четвертом выходе БВОС 35, по значению которого блок управления 39 определяет длительность 1-го цикла, кроме того флагу F присваивается значение F_контр, обеспечивающее в дальнейшем выполнение блоков 15-27 алгоритма (фиг.34).At the beginning of the algorithm, the signal arriving at input 3 of the BVOS 35 from the third output of the control unit 39 is analyzed. When the modem is turned on (or when the connection mode is restarted in the event of a communication failure), this signal has a zero value, in the operating mode its value is “1” (line and timing diagram of FIG. 26). Therefore, in the 1st cycle (at the stage of entering into communication), the right-hand side of the algorithm is executed. It begins by checking the conditions F = F _count and F1 = F1 _count , which are not satisfied during the first two passes (the first two runs of the algorithm). This is due to the fact that during the first two OFDM symbols of memory 2 of the buffer storage unit 26 is not yet full and therefore the calculation and processing of the clock sum (16) does not make sense. Due to the execution at the first passage of the command of block 28 of the algorithm (Fig. 34), at the second passage, the condition F1 = F1 _counter is met and in block 29 of the algorithm (Fig. 34), elements of the complex array are set to zero

serving to accumulate the values of the sum (16) at different values of the starting address. Also, in this block of the algorithm, the zero value of the variable n is used, which is used in the algorithm to count the number of OFDM symbols on which the synchro sum is averaged; the signal at the fourth output of the BVOS 35 is set to “0”, by the value of which the control unit 39 determines the duration of the 1st cycle, in addition, the value F _{counter is} assigned to the F flag, which ensures further execution of blocks 15-27 of the algorithm (Fig. 34).

(В алгоритме значение

предполагается хранить в тех же ячейках памяти, что и

, поэтому последнее равенство записано в обозначениях:

. Это позволяет повысить помехоустойчивость приемника, поскольку при малых значениях Р_ср поднимает уровень анализируемой далее величины

. Результаты этих вычислений фиксируются в комплексном (т.е. двумерном, имеющем реальную и мнимую части) массиве

. В блоке 22 алгоритма (фиг.34) осуществляется подсчет числа OFDM-символов n, на которых производится накопление сумм

с целью усреднения результатов, минимизирующего мешающее влияние шума канала. До тех пор пока n не достигла значения заранее заданного числа N_yn, определяющего объем усреднения (до выполнения условия n=N_yn), выполнение алгоритма на этом заканчивается. При n=N_yn вычисление синхросуммы (16) заканчивается и начинается обработка полученных результатов. В новом цикле по k (блок 23 инициализации и блоки 24-26 тела цикла (фиг.34)) определяется значение начального адреса k, при котором накопленная нормированная синхросумма имеет максимальный модуль МВ(K). Значение этого адреса присваивается переменной N_a, оно определяет начало n-го OFDM-символа на фиг.32, что и является задачей посимвольной синхронизации. В блоке 27 алгоритма это значение выдается на третий выход блока БВОС 35, на четвертом выходе БВОС устанавливается уровень «1», свидетельствующий о том, что задача установления синхронизации на этапе вхождения в связь выполнена; кроме того, осуществляется обнуление массива

, необходимое для функционирования БВОС 35 в начинающимся далее 2-м режиме работы модема (в режиме передачи данных).At the third and subsequent runs of the algorithm in the cycle with respect to the variable r (block 16 of initialization r and blocks 17-20 of the body of the cycle), the sum (16) is calculated with the value of its initial address l = k (l is the variable of formula (16), k is the variable algorithm of Fig. 34). As can be seen from the timing diagram (line g, Fig. 26), the signal from the fifth output of the control unit 39, which is supplied to the second (control) input of the KM 27 in the 1st cycle, has a zero value. This ensures the connection of the address of the readout coming from the first output of the BVOS 35 to the first (signal) input of KM 27 to the second input of the BZB 26 connected to the output of KM 27, as a result of which the value of the addressed reference appears at the first output of block 26 and at the input 1 of BVOS 35. In the loop in the variable k (initialization block 15 and blocks 16-21 of the body of the cycle of Fig. 34), the sums (16) are calculated for all S possible values of their starting address l = k, (k = 0 ÷ (S-1). in addition, in block 15 of the algorithm (Fig. 34), the variable P is assigned the value calculated in the DFT block 29 and supplied to the fifth input of the BVOS 35 of the average power of signal tones P _cp , in block 21 of the algorithm of Fig. 34, for each k, the normalized value of the clock sum

(In the algorithm, the value

supposed to be stored in the same memory cells as

, therefore, the last equality is written in the notation:

. This allows you to increase the noise immunity of the receiver, since at low values of P _cf raises the level of the further analyzed value

. The results of these calculations are recorded in a complex (i.e., two-dimensional, having real and imaginary parts) array

. In block 22 of the algorithm (Fig. 34), the number of OFDM symbols n, on which the sums are accumulated, is calculated

with the aim of averaging the results, minimizing the interfering effect of channel noise. Until n reaches the value of a predetermined number N _yn that determines the volume of averaging (until the condition n = N _yn is fulfilled), the execution of the algorithm ends there. When n = N _{yn, the} calculation of the synchro sum (16) ends and the processing of the obtained results begins. In a new cycle in k (initialization block 23 and blocks of the cycle body 24-26 (Fig. 34)), the value of the initial address k is determined at which the accumulated normalized clock sum has the maximum module MV (K). The value of this address is assigned to the variable N _a , it determines the beginning of the nth OFDM symbol in Fig. 32, which is the task of symbol-by-symbol synchronization. In block 27 of the algorithm, this value is output to the third output of the BVOS block 35, the fourth output of the BVOS is set to level “1”, indicating that the task of establishing synchronization at the stage of entering into communication is completed; in addition, zeroing the array

required for the operation of the BVOS 35 in the 2nd modem operation mode starting further (in the data transfer mode).

The value of N _a from the output 3 of BVOS 35 is fed to the signal input 1 KM 28, the third (control) input of which from the third output of the control unit 39 receives the signal shown on the line and time diagram of Fig.26. As can be seen from the diagram, in the 1st mode, this signal has a zero level. Under the influence of this level KM 28 (Fig.25) connects to the first input of the address register RA 32 a signal present at its first input. With the arrival of the next pulse with a frequency ƒ _S from the third output of the BOC 12 (line in the time diagram of Fig. 26) at the second input of the clocking of the recording of RA 32, the number present at the first input of RA 32 is written into the register. Thus, in RA 32, the value of N _a determined in the 1st cycle is recorded, i.e. set the number N _PA = N _a . Recording with each pulse of frequency ƒ _S in RA 32 a random number present at the input 1 of RA 32 at the moments preceding the determination of N _a does not interfere with the operation of the device, since the use of the contents of RA 32 is carried out only in the second cycle of the modem.

The beginning of the second mode (data transfer mode) is set by the control unit BU 39 (Fig. 25) after it receives at the fourth input a unit level of the signal from the fourth output of the BVOS 35, with the arrival of the next pulse BOC 12 at the second input of the BS 39 with a frequency of ƒ _S . When, the signal at the output of 3 CU 39 receives a one value (line 26 and a time chart). In the operating mode, a dedicated data signal is demodulated and the necessary tracking of the correct position of the symbol synchronization and the value of the frequency shift introduced by the radio channel is carried out.

The task of tracking the correct position of the character-by-symbol synchronization in the operating mode is solved as a result of the interaction of the modem units 28, 32, 33, 35, 36 (Fig. 25). At the same time, in the BVOS 35, based on the analysis of the values of the synchro sum of the form (16), the estimate of the initial address N _{a of the} set of samples belonging to the nth OFDM symbol fixed in the memory of the BZB 26 is still determined, however, this address is now not searched for over the entire duration interval OFDM symbol, including S samples, and at narrower boundaries. In addition, the accumulation of the sync sum in this case is carried out on only one OFDM symbol, since the averaging and correction of the results are carried out by a combination of modem blocks 28, 32, 33, 36 (Fig. 25).

The operation of the algorithm depicted in Fig.34, in this case, is as follows. As already noted, in the operating mode, the signal from the third output of the control unit 39 supplied to the input of the BVOS 35 has a single level, therefore, according to the results of checking the value of this signal, the left-hand side of the algorithm is executed, including blocks 1-14 (Fig. 34).

As follows from the time chart (line g, Fig. 26), the signal at the fifth output of the control unit 39, arriving at the first (control) input of the KM 27 during the period of time following the start of the operation of the BVOS 35, is still zero, therefore, as in the 1st cycle of KM 27, to the second input of addressing of the memory device 2 in the BZB 26, during the execution of the algorithm, it connects the output 1 of the BVOS 35. At the same time, the first input of the BVOS 35 from the first output of the BZB 26 receives addressable samples. In block 1 of the algorithm (Fig. 34), the variable N _{PA is} assigned the value of the starting address of the OFDM symbol fixed in memory 2 of the BZB 26. When the algorithm is first run in the 2nd cycle, it is equal to the value of N _a given in block 27 of the algorithm (Fig. 34) ) to the third output of BVOS 35 at the end of the 1st cycle, then as a result of the interaction of blocks 32, 33, 35 and 36, this value changes, tracking the correct position of the symbol synchronization. In addition, in block 1 of the algorithm (as well as in block 15 of the algorithm), the variable P is assigned the average power of the signal tones P _cf.

In block 2 of the algorithm (34) sets a lower N _N = N _PA -ΔN and top N _in = N _PA +? T boundary value search start address complete OFDM-symbol asked on the assumption that a time elapsed since the last time algorithm of it (starting address), the value could not change by more than ± ΔN units. Also here (in block 2), the loop variable k and the auxiliary variable i are initialized.

. При этом в блоке 8 алгоритма также и с той же целью, что и в блоке 21 алгоритма (см. выше), осуществляется нормирование значения

по переменной Р. По окончании описанного цикла по k организуется новый цикл по k (блок 9 инициализации и блоки 10-12 алгоритма). В этом цикле определяется начальный адрес синхросуммы с максимальным модулем МВ(k). Значение этого адреса присваивается переменной N_а, оно и определяет текущую оценку начального адреса полного OFDM-символа.Then, in the cycle with respect to the variable r (block 3 of initialization r and blocks 4-7 of the body of the cycle), as in the right-hand side of the algorithm, the sum (16) is calculated with the value of its initial address l = k (l is the variable of formula (16), k is an algorithm variable). In the loop with respect to the variable k (partially the initialization block 2 and blocks 3-8 of the cycle body), the sums (16) are calculated for 2AN possible values of their starting address l = k, (k = N _n ÷ N _k ). The results of these calculations are recorded in a complex array

. Moreover, in block 8 of the algorithm, for the same purpose as in block 21 of the algorithm (see above), the value is normalized

in the variable P. At the end of the described cycle in k, a new cycle in k is organized (block 9 of initialization and blocks 10-12 of the algorithm). In this cycle, the starting address of the clock with the maximum module MV (k) is determined. The value of this address is assigned to the variable N _a , and it determines the current estimate of the starting address of the full OFDM symbol.

; подготавливающее алгоритм к новому запуску.In block 13 of the algorithm (Fig. 34), in accordance with rule (18), the phase shift of the group signal Δφ _gr = ω _hs T over the orthogonality interval is determined due to the frequency shift uncompensated in the PFSS 24. In block 14 of the algorithm, the values of N _a and Δω _gr are given to the second and fifth outputs of the BVOS 35 (Fig.25); in addition, the complex array is zeroed

; preparing the algorithm for a new launch.

The value of the starting address N _a [n], determined in the nth OFDM clock present at the second output of the BVOS 35, is supplied to the first input of the FDPS 36 (Fig. 25). At the second input of this block, the value of the address N _PA [n] recorded in the nth step is supplied from the output of RA 32. In FDPS the difference signal is calculated:

ΔN _PD [n] = N _a [n] -N _PA [n],

which is then averaged over several OFDM cycles.

поступает на первый вход сумматора 33, на второй вход которого с выхода РА 32 подается число N_PA[n]. В результате на выходе сумматора 33 появляется новое скорректированное значение:PDPS output signal

arrives at the first input of the adder 33, to the second input of which the number N _PA [n] is supplied from the output of RA 32. As a result, the output of the adder 33 appears a new adjusted value:

which is fed to the second input of KM 28. In the second cycle of the modem, the signal supplied to the third (control) input of KM 28 takes a single value (line and time diagram of FIG. 26). As a result, the output of KM 28 is connected to the signal supplied to its second input from the adder 33, that is, N _PA [n + 1]. This value is supplied to the first input (record) of the address register PA 32 and is recorded when the next pulse arrives at the second input RA from the third output of the BOC 12. Thus, the correct position of the symbol synchronization is monitored.

The exact tracking of the time-varying value of the frequency shift introduced by the radio channels into the group signal is carried out in the frequency shaper of the spectrum transfer signal FFPSS 34, the functional diagram of which is shown in Fig. 35. The circuit includes four multipliers P1, P2, P3, P4, four adders СМ1, СМ2, СМ3, СМ4, three commutators KM1, KM2, KM3, three registers Рг1, Рг2, Рг3, sensor “0” and the memory unit UP, in which are recorded discrete samples of the full period of the sine wave and cosine wave. Each of the multipliers multiplies the number supplied to its first input by a certain fixed coefficient applied to the second input. The operation of the FSPS is described by the following equations:

определяет прогнозируемое в i-м такте значение набега фазы, обусловленного наличием нескомпенсированного частотного сдвига, которое рекуррентным образом вычисляется в соответствии с уравнением (21). При этом приращение набега фазы Δf[i] рассчитывается как линейная комбинация присутствующего в i-м такте на первом входе ФЧПСС набега фазы группового сигнала Δφ_гр[i] и величины

, характеризующей вычисленную в предыдущем такте оценку скорости изменения набега фазы, обусловленного нескомпенсированным частотным сдвигом. Величина Δφ_гр[i] вычисляется в БВОС 35 и обуславливается частотным сдвигом, нескомпенсированным в ПЧКВ 24 при действии на его третьем и четвертым входах отсчетов выходных сигналов ФЧПСС, сформированных в предыдущем, (i-1)-м такте. Рекуррентный процесс вычисления величины

описывается уравнением (20). На первом шаге (при начальном условии

) значение

выбирается равным (1-α₂)Δƒ_i, где в соответствии с (19) Δƒ_i=α₁Δφ_гр[i]. На последующих шагах оно рассчитывается как линейная комбинация

и Δƒ[i].Equation (22) allows you to directly calculate the phase read from the UE (Fig. 35) to the first and second outputs of the samples of harmonic oscillations. Addition in (22) is carried out modulo P, where P is the number of discrete samples of the full period of the cosine wave and sinusoid recorded in the UE (Fig. 35). The phase calculated in accordance with (22) is the address of the corresponding reference. The quantity appearing in (22)

determines the predicted phase incursion value in the ith step due to the presence of an uncompensated frequency shift, which is calculated recursively in accordance with equation (21). In this case, the increment of the phase shift Δf [i] is calculated as a linear combination of the phase shift of the group signal Δφ _gr [i] present in the i-th cycle at the first input

, which characterizes the estimate of the rate of change in the phase incursion calculated in the previous measure due to the uncompensated frequency shift. The value Δφ _gr [i] is calculated in the BVOS 35 and is determined by the frequency shift, which is not compensated in ПЧКВ 24 when the third and fourth inputs of the samples of the output signals of the PSFSS formed in the previous (i-1) -th clock are applied. The recurrent process of calculating a quantity

is described by equation (20). In the first step (under the initial condition

) value

is chosen equal to (1-α ₂ ) Δƒ _i , where in accordance with (19) Δƒ _i = α ₁ Δφ _gr [i]. In the next steps, it is calculated as a linear combination

and Δƒ [i].

Equations (19-22) in the scheme of Fig. 35 are implemented by the following nodes: equation (19) - P1, P3 and CM1; equation (20) - P2, P4, CM2 and Pr1; equation (21) is CM3 and Prg2 and equation (22) is CM4 and Prg3. Short single pulses with a frequency of ƒ _S are applied to the second clock inputs of the register recordings of the registers Рг1 and Рг2 (line in the time diagram of FIG. 26). Pulses with a frequency of Р _d are fed to the second input of the register Рg3 from the third input (line a of the time diagram of Fig. 26). The switches Km1, Km2 and Km3 are used to provide the initial installation mode, in which the frequency of the output oscillations of the PSFSS 34 is set equal to ƒ _hs defined in the ASF unit. At the same time, a signal is fed to the third (control) inputs of all three switches, which arrives at the fifth input of the PSFSS from the third output of the control unit (line 3 of the time diagram of FIG. 26). At a zero value of this signal (entry into communication mode), their second (signal) inputs are connected to the outputs of the switches, and at a single value (in operating mode), the first inputs are connected. In the operating mode, the values prescribed by equations (19-22) are supplied to the first inputs of the entries of the registers Pr1, Pr2, and Prg3 from the outputs of the switches. In the mode of entering into communication, the signal from the sensor “0” is received at the first inputs of the registers Рг1 and Рг3, and the signal ΔN _hs arriving through the fourth input from the first output of the ASF 22 (Fig. 25) is received at the first input of the register Рг2, which ensures generation с _{hs oscillations} in this mode. Note that in a rather long (due to averaging over several OFDM-clocks) process of initial search for the position of symbol-wise synchronization performed in BVOS 35, the value ΔN _hc (and hence the corresponding frequency ƒ _hs ) determined by ASF 22 is repeatedly updated and thereby monitors the change in the value of the frequency shift. This allows you to increase the accuracy of synchronization and, as a result, increase the noise immunity of the modem.

It can be shown that the block under consideration is a third-order digital phase synchronization system that allows one to track (in the tracking mode) with fast error the rapidly changing frequency shift values, which increases the modem noise immunity during operation under such conditions. In practice, its testing was carried out at the following values of the coefficients: α ₁ = 0.125; α ₂ = 0.5; α ₃ = 0.85.

Demodulation and evaluation of the values of the received symbols, as well as the elimination of residual desynchronization are carried out in the proposed device as a result of the interaction of blocks 29, 39, 38, 37 and 31 (Fig.25). As in the prototype device, simultaneous demodulation in all parallel subchannels of an OFDM system is performed by calculating the DFT from the set of N samples {y _hs (kΔt)} implemented by the DFT 29. In the present invention, input 1 of the DFT block 29 from the output of RA 32 the value of the starting address recorded in the memory 2 (see Fig. 13) of the BZB 26 of the reference corresponding to the set symbol-by-symbol synchronization is supplied. To the second input of the DFT block 29 from the fifth output of the BU 39, the signal shown on line g of the timing diagram of Fig. 26 is fed, on the positive edge of which the work of the DFT block 29 begins. With the arrival of level “1” to the second input of the block 29 from its first output, sequential in time, the issuance of the addresses of N samples stored in the memory 2 of the BZB 26 (see Fig.13). Through KM 27, controlled by the same signal supplied to its second input from the fifth output of BU 39, the addresses are supplied to the second input of the BZB 26, as a result of which, from its first output, the samples to be demodulated (i.e., the DFT calculation) are sent to the third input of the block 29 the received signal y _hs (kΔt).

In block 29 (FIG. 25), using the FFT, the DFT of the readout batch of samples is calculated, after which the arithmetic average value P _{cf of the} power of all DFT samples is determined, then supplied to the third output.

Note that, as can be seen from line g of the timing diagram of FIG. 26, the execution by the block 26 of the described operations is performed not only in the operating mode, but also in the mode of entering into communication (starting from the process of establishing symbol-by-symbol synchronization). This is necessary to calculate the average power P _cf used in this process (input 5 of the BVOS block 35 connected to the third output of block 29), which, as is easy to show, does not depend on the correct choice of the starting party address from the N input samples of the DFT block 29 installed in the process of character-by-character synchronization.

From the second output of block 29, the results of the DFT calculation are sent to the first input of the grouping, synchronization, and argument calculation block (BSSA) 30, the functional diagram of which is shown in Fig. 36. As noted in the description of the transmitter unit 3, the transmitted modem signal is formed in such a way that one information symbol is transmitted over several (two or more) parallel subchannels. In the upper left part of Fig. 36, it is shown how N _{T is} formed from the whole set of DFT samples received at the first input of the DFT block 30. groups including 3 or 2 samples corresponding to the outputs of the subchannels used to transmit one information symbol. The i-th group of samples goes to inputs 1 _i (including 3 or 2 inputs for separate samples of the i-th node of grouping, synchronization, and calculation of the argument (BGSVA _i , i = 1-N _T )). A functional diagram of the implementation of such a node, designed to process three input samples, is shown in Fig. 37. It contains 3 identical parallel-coupled phase alignment paths of input samples, each of which includes a complex KP multiplier, an VA argument calculator, a UV subtraction unit, a digital filter and a complex memory, and a complex KSm adder, an VA total signal argument calculator _∑ and delay element EZ.

Each of the phase equalization paths is a first-order digital phase-locked loop (FAP) system that eliminates the residual desynchronization of the received k-tone. In the complex KP multiplier, the complex input DFT (output of the kth subchannel) is multiplied by the readout on the nth OFDM clock from the output of the short-circuit amplifier, the phase-adjusted complex harmonic oscillation exp (-jφ _k [n]) = cos φ _k [ n] -sin φ _k [n].

ПГ в данном случае используются реальная и мнимая части входных отсчетов ДПФ.A specific circuit implementation of the KP has the form depicted in Fig. 28 (without the Hilbert PG converter). Instead of the output signals S _nc and

In this case, the GHGs use the real and imaginary parts of the input DFT samples.

Next, in block VA, the argument of the result of this multiplication is calculated, from which then, in the shock wave (on the third input of the shock wave) received on the third input of the HVAC (and therefore on the input 3 _{i of the} HVAC,) are subtracted from the second output of the symbol value estimation block 31 described below (BOS ) the value of the reference phase φ _{et i of the} i-th information symbol and (via the second input of the shock wave) supplied to the second input of the HVACS (and therefore to the second input of the HVACS _i ) from the fifth output of the HVAC 35 the value of the phase shift of the group signal Δφ _gr on the orthogonality interval due to incompetent PCHKV 24 in th e frequency offset. The output signal of the shock wave Δφ _{k is} fed to a first-order digital filter. The algorithm of this filter is described by the difference equation:

where φ _k [n] is the filter output signal in the nth OFDM clock cycle, which determines the phase (address) of the samples of complex harmonic oscillation exp (-7φ _k [n]) read further from the ROM in this clock cycle; α = const; addition is carried out modulo N _p ; N _p - the number of samples in the period of the cosine and sinusoids recorded in the complex storage node of the short-circuit memory.

A practical implementation of the filter can be performed according to the scheme of Fig. 38, which includes a multiplier Π by a constant coefficient α, an adder Сm and a register Rg with inputs of a record 1 and a clock of record 2. Note that the delayed EZ delay element ( see Fig. 37) a pulse from the fourth input of the BGSVA (that is, a short single pulse from the third output of the BOC 12, line 3 of the time diagram of Fig. 26). As will be shown below, with the same pulse in block 31, the value of the reference phase of the ith information symbol calculated in the nth OFDM clock is written to the output register. A slight delay introduced by the EZ element ensures that by the moment of fixing the result of addition in Pr in the adder (Fig. 38), the values φ _{et i} [n] and Δφ _gr are applied to the second and third inputs of the calculator of the argument VA in the circuit of Fig. 37 [n] calculated in the nth OFDM clock cycle, which ensures the operation of the digital filter in accordance with equation (23). In this case, the HC output signal in the circuit of Fig. 37, resulting from the subtraction from the full phase of the received K-tone taking place in the n-th OFDM clock (VA output of Fig. 37), formed in the transmitter and restored in the receiver unit 31 the reference phase φ _{et i} [n] of this tone, and the phase incursion in the nth clock 35 (and not yet used in the PSPS 34) of the phase shift Δφ _gr [n], caused by the frequency shift in the channel, and represents the residual phase desynchronization this tone, which is fully tracked (i.e., reduced to zero) of the described digital system 1st FAP 1st order (nodes KP, VA, HC, CF and KZU Fig.37). Thus, the phase alignment of the signals present at the outputs of the complex multipliers KP in all (three) branches BGSVA, shown in Fig.37. This allows you to algebraically add (according to the rules for adding complex numbers) these signals in the complex adder KSM and use the total signal for further processing. In accordance with the theory of diversity reception, the modem noise immunity is significantly increased.

The output signal of the complex adder is fed to the input of the VA _узла node, in which its argument φ _oi [n] is calculated, which is supplied to the output of the BGSVA _i . The set of outputs of the nodes BGSVA _i , (i = 1 ÷ N _T ) in the circuit of Fig.36 forms the output signal BGSVA 30, fed to the input 1 of the block of calculators informative phase increment (BVIPF) 37.

In its purpose and implementation, block 37 is completely similar to the block of the same name in the circuit of the prototype device. At its second input, from the output of the block for estimating symbol values (BOS), a set of values of φ _{et i} [n-1], (i = 1 ÷ N _T ) of the full reference phase of signals supplied by the i-th subchannels, is calculated in the previous step. Note that despite the fact that the second input of block 37 and the third input of block 30 are connected to the second output of the BOSC 31, by block 37 in the nth OFDM clock cycle the values φ _{et i} [n-1] calculated in (n-1 ) -th step, and block 30, φ _{et i} [n], calculated in the nth step. This is due to different points in time of reading the output information of the BOSS 31 by these blocks. As indicated above, BGSVA reads this information immediately after writing the result of calculations in the nth step (i.e., the end of the nth step) to the output register of the BOSC. The block 37 under consideration fulfills its functions and receives this information during the nth step, when the values of φ _{et i} [n-1] calculated in the previous cycle are in the output registers of the BOSC 31.

In block 37, informative phase increments Δφ _i [n] of the demodulated signal in the ith subchannel on the nth OFDM clock are determined. These values are calculated as:

Δφ _i [n] = φ _оi [n] -φ _{et i} [n-1].

The combination of the values Δφ _i [n] found in this way (i = 1 ÷ N _T ) makes up the output signal of the BVIPF 37 and is supplied to the first input of the switching unit 38, to the second input of which the output signal of the encoder-storage of the tuning sequence of the KNNP 41 is received. KNNP from the output of the GNP 11 is supplied with a training sequence, which is simultaneously generated and used as transmitted data in the mode of entering into communication and in a remote modem, the output signal of the transmitter of which is fed to the input of the reception path of the described device Properties. In the KNNP block 41 (as well as in the transmitter encoder), q-bit code combinations (where 2 ^q is the multiplicity of the phase modulation used) are encoded, formed from the training sequence, with a phase shift Δφ _npi in accordance with the manipulation code (unlike the encoder the coding result here is the value of the phase shift itself, and not the value of the in-phase and quadrature coordinates of the vector forming such a shift with the abscissa). In addition, in block 41, an accumulation of N _T phase shifts Δφ _nni [n] is transmitted in the nth OFDM clock. The combination of these values as the output signal of the KNNP 41 and is fed to the second input of the KB 38.

The third (control) input KB 38 from the first output of the control unit BU 39 receives the signal shown on the line to the time diagram of Fig.26. The positive front of this signal is formed in the control unit after the accumulation of a predetermined N _nn number of pulses with a frequency ƒ _S received at its second input, after the unit level is received at the fourth input from the fourth output of the CWS, indicating that the initial establishment of symbol synchronization is completed. The value of N _{pp is} determined on the basis of the maximum possible duration of the transition process of the first-order digital phase-locked loop implemented on the basis of the phase alignment path in the BSVA 30 unit. As a result, in the connection mode (level “0” at the third input of the switching unit 38) to the output KB 38 (and, consequently, to the first input of the block for evaluating the values of symbols and the reference phase of the OSB 31) the output of block 41 is connected, and in the data transfer mode the output of block 37.

In its purpose and implementation, the unit for determining the values of symbols 31 is completely similar to the block of the same name 21 in the circuit of the prototype device. It includes N _t in parallel connected identical nodes, each of which has a functional diagram shown in Fig.24. A detailed statement of the principles of functioning and interaction of the nodes included in it (UOZS - node for evaluating the values of symbols, VZEF - calculator of the values of the reference phase and register Rg) is given in the description of the prototype device, so here we note only some features of the use of this scheme in the proposed device. Connection to the first input of block 31 (and therefore to input 1 _{i of the} i-th node of this block shown in Fig. 24) in the communication mode formed in the block 41 of the "error-free" phase shifts Δφ _нni [n] allows you to enter synchronism of digital phase-locked loop systems of the first order CSFAP implemented as phase alignment paths in block 30. Indeed, while these digital combination probes are in transition mode (that is, until the signals at the inputs of the complex KSM adder of the BGSVA _i nodes in Fig. 37 are not formed), the output the signal of these nodes φ _oi [n] is uninformative and ultimately does not allow to develop in block 31 the correct assessment of the reference phase φ _eti [n] supplied to the third input of block 30 and necessary for its correct operation. Using in this case the values Δφ _нni [n] generated in the described manner, under the condition that the remote modem simultaneously transmits a signal corresponding to the same training sequence, solves this problem. In the data transfer mode, the signal φ _oi [n] with greater reliability than in the prototype, provides an estimate of the received symbols, supplied to the output of block 31, which is the modem output.

Depicted in FIG. 24, the output of the 3rd _i -th node included in the BOSS (the combination of these outputs in the prototype formed the output 3 of the BOSS) is not used in block 31 of the proposed device, since the need for information presented on this output during the interaction of block 31 with other units of the device, missing.

The clock in the register Rg calculated in the VZEF (Fig. 24) and applied to output 2 (and therefore to output 2 of the BOS 31) of the reference phase φ _eti is supplied to the input 2 of the BOS 31 from the output 3 of the BOC 12 short unit pulses with frequency ƒ _S shown on line 3 of the timing diagram of FIG.

As already noted in the analysis of the properties of the prototype, one of the significant interfering factors when transmitting data over radio channels is a powerful narrow-band spectrum-focused noise that falls into the frequency band of one of the parallel subchannels of an OFDM system. This interference not only does not allow the reception of information in this subchannel, but also due to the inevitable synchronization errors significantly worsens the reception conditions in other subchannels and thereby leads to a significant deterioration in noise immunity. The proposed device provides measures to reduce the interfering effect of this interference, which are as follows. As can be seen from the diagram of Fig. 25, the signal from the output 2 of the FFT block 29 also goes to the input of the block for calculating and analyzing the power dispersion of the BVDMT 40 tones. In this block, the power dispersion of the ith tone D _{Pi is} calculated over a certain time interval T ₀ = N ₀ T _S (T _S = 1 / ƒ _S - OFDM symbol duration) according to the formulas:

- i-й отсчет ДПФ (комплексное число), вычисленный в блоке ДПФ 29 в n-м после начала накопления суммы (24) или (25) OFDM-такте;Where

- the i-th DFT sample (complex number) calculated in the DFT block 29 in the nth after the start of accumulation of the sum (24) or (25) of the OFDM clock;

- мощность величины

;

- power value

;

* - sign of complex conjugation;

- оценка математического ожидания величины

.

- estimate of the mathematical expectation of a quantity

.

по формуле (25).Obviously, the calculation of D _Pi , by formula (24) is preceded by the calculation

by the formula (25).

, (N - размер ДПФ) в блоке 40 осуществляется проверка выполнения условия D_Pi<D_доп, где D_доп - некоторая заранее определенное допустимое значение величин D_Pi,. (Отметим, что при практической реализации удобнее вычислять величину N₀D_Pi и проверить выполнение условия N₀D_Pi<D_доп, т.к. при этом в формуле (24) отпадает необходимость деления на N₀). Невыполнение данного условия означает, что среднее отклонение мощности i-го тона от ее среднего значения превышает установленное на основе предварительных исследований допустимое значение. Это и говорит о наличие в i-ом подканале сосредоточенной по спектру помехи. Номер i этого подканала фиксируется и выдается на выход БВДМТ 40 (при отсутствии такого подканала на выходе этого блока присутствует "0"). Выходной сигнал блока 40 подается на вход 3 описанного выше блока режекторных фильтров 15, структурная схема которого показана на фиг.27. Этим сигналом управляется коммутатор Км (фиг.27), пропускающий на выход сигнал i-го режекторного фильтра РФ_i. При этом участок спектра входного сигнала в полосе частот i-го подканала оказывается подавленным и влияние сосредоточенной по спектру помехи на другие подканалы устраняется. Возникающая в данном случае потеря информации, передаваемой по i-му каналу, компенсируется используемым в блоке 30 (фиг.25) алгоритмом выделения информативной фазы φ_0i[n] по суммарному сигналу, кроме того ошибки малой кратности могут быть исправлены в декодере канала (подключаемого к выходу модема) на основе помехоустойчивого кодирования.After calculating each value of D _Pi ,

, (N is the size of the DFT) in block 40, the fulfillment of the condition D _Pi <D _add is checked, where D _add is some predetermined allowable value of the values of D _Pi,. (Note that in practical implementation it is more convenient to calculate the value of N ₀ D _Pi and verify that the condition N ₀ D _Pi <D _add , because in this case, there is no need to divide by N ₀ in formula (24)). Failure to do so means that the average deviation of the power of the i-th tone from its average value exceeds the permissible value established on the basis of preliminary studies. This indicates the presence in the i-th subchannel focused on the spectrum of interference. The number i of this subchannel is fixed and issued to the output of the BVDMT 40 (in the absence of such a subchannel, "0" is present at the output of this block). The output signal of the block 40 is fed to the input 3 of the above-described block of notch filters 15, the structural diagram of which is shown in Fig.27. This signal is controlled by the Km switch (Fig. 27), which passes the output signal of the i-th RF RF _i filter. In this case, the portion of the spectrum of the input signal in the frequency band of the ith subchannel is suppressed and the influence of the noise concentrated in the spectrum of the other subchannels is eliminated. The loss of information that occurs in the i-th channel that occurs in this case is compensated by the algorithm used to block the informative phase φ _0i [n] used in block 30 (Fig. 25) by the total signal, in addition, low-frequency errors can be corrected in the channel decoder (connected to the modem output) based on noise-resistant coding.

Thus, the introduced set of new nodes and connections allows us to obtain a technical result - an increase in the noise immunity of the modem, due to the following most important factors:

1. The option proposed in this device for constructing an initial frequency shift estimator in a channel (set of blocks 39-44) at equivalent implementation costs allows for a higher accuracy in estimating the frequency shift value. This reduces the requirements for the swath of the tracking system for tracking the frequency shift in the operating mode and allows you to use the proposed third-order digital phase synchronization system as such, providing the ability to track fluctuations in the frequency shift and thereby increase the noise immunity of the modem.

2. In the proposed version of constructing a system of symbol-by-symbol synchronization (both in the mode of entering into communication and in the operating mode) and the tracking system for tracking the frequency shift in the operating mode, information on the values of the sync parameters is obtained based on the analysis of not one reference, but the accumulated amount of the correspondingly processed samples, which reduces the effect of channel noise (due to its averaging) and ultimately increases the modem noise immunity.

3. The elimination of residual desynchronization when making decisions about the meaning of the received symbols is not due to the use of the phase error value averaged over all subchannels (which does not coincide with the true phase shift in each individual subchannel), but is carried out by detecting and tracking the phase mismatch using the phase-locked loop system in each subchannel. This allows you to implement the principle of diversity reception in the proposed modem, based on the addition of pre-phased signals transmitted over different subchannels, and thereby increase the modem noise immunity.

4. A technical solution is proposed in the modem that allows eliminating the interfering effect of spectrum-concentrated noise falling into the frequency band of one of the parallel subchannels on the signals transmitted through the remaining subchannels, and thereby increase the modem noise immunity.

INFORMATION SOURCES

[1] D. D. Klovsky, B. I. Nikolayev. Engineering implementation of radio circuits. M., “Communication”, 1976, Ch. 5, pp. 136-193.

[2] Egorov V.V., Mingalev A.N. Serial KB modems with adaptive correction. Papers of the 7th International Conference and Exhibition “Digital Signal Processing and its Application”. M., 2005

[3] Egorov V.V., Mingalev A.N. Establishing communication and selecting the structure of the correction filter for sequential transmission of messages over KB radio channels. Papers of the 8th International Conference and Exhibition “Digital Signal Processing and its Application”. M., 2006

[4] Zabirov D.P., V.L. Khazan. High speed modem for trunk KB radio links. Radio engineering / Omsk Research Institute of Instrument Engineering. - 2004 - Issue 9. - p.20-26 /.

[5] M.S. Gill. Coded-Waveform Design for High Speed Data Transfer over High Frequency Radio Channels. § 3.4, pp3-44. PhD thesis, Institute for Telecommunications Research School of Electronic Engineering University of South Australia, 1998. http://www.itr.unisa.edu.au/research/pubs/thesis/mcg.pdf.

[6] B. Sklyar. Digital communication. Moscow - St. Petersburg - Kiev. William Publishing House, 2003, §4.6.1-4.6.3, pp. 213-236.

[7] J. Procis. Digital communication. M. Radio and communications. 2000. §12.2.2, p. 593-596.

Claims (1)

A radio modem including the first, second, third and fourth switches, an encoder, a buffer drive, a unit for calculating the inverse discrete Fourier transform, a unit for adding a guard interval, a numerical array converter in a time sequence, a filter, a matching unit, a tuning sequence generator, a reference frequency unit, input unit, automatic gain control unit, buffer storage unit, discrete Fourier transform unit, informative phase increment calculator unit , a unit for evaluating the values of the symbols and the reference phase and a control unit, the first input of the first switch connected to the input of the modem transmitter, the second input of the first switch connected to the output of the training sequence generator, the third input of the first switch connected to the first output of the control unit, and the output of the first switch connected to the input of the encoder, the output of which is connected to the input of the buffer storage; the output of the inverse discrete Fourier transform calculation unit is connected to the input of the guard interval adding unit; the output of the add guard interval unit is connected to the first input of the numerical array converter into a time sequence, the second input of which is combined with the second input of the shaping filter, the second input of the input block and the fourth input of the buffer storage unit and is connected to the first output of the reference frequency block, the output of the numerical array converter the time sequence is associated with the first input of the shaping filter; the output of the matching unit is connected to the output of the modem transmitter, the second input of the third switch is connected to the fifth output of the control unit and to the second input of the discrete Fourier transform unit, the third input of the third switch is connected to the first output of the discrete Fourier transform unit, the output of the third switch is connected to the second input of the buffer memory unit, the first input of which is connected to the output of the second switch, the third output of the block of reference frequencies is connected to the second input of the unit for evaluating the values of symbols and pubic phase; the first input of the input unit is connected to the input of the modem receiver; the second output of the control unit is connected to the third input of the buffer storage unit; and the third output is with the third input of the fourth switch, the third input of the discrete Fourier transform unit is connected to the first output of the buffer storage unit; the second input of the informative phase increment calculator block is connected to the second output of the symbol value and reference phase estimator, the first output of which is the output of the modem receiver, characterized in that a distribution and formation block with redundancy is introduced into it, the first and second adders, the pilot generator -signal, block of notch filters, narrow-band bandpass filter, first and second frequency converters with complex output, block of accumulating adders, decimator, block of accumulation of readings and computing a discrete Fourier transform, a frequency shift analyzer, a filter, a grouping, synchronization and argument calculation unit, a signal spectrum transfer frequency shaper, a synchro sum calculation and processing unit, an address register, a phase-by-phase synchronizer, a tone power dispersion calculation unit, a switching unit and an encoder a storage of the training sequence, the output of the buffer storage being connected to the input of the distribution and formation unit with redundancy One of which is connected to the input of the inverse discrete Fourier transform calculation unit, the first output of the reference frequency unit is additionally connected to the input of the pilot signal generator, the first input of the control unit, to the second inputs of both frequency converters with a complex output, a narrow-bandpass filter, a notch filter unit, and a filter , to the third input of the frequency spectrum transfer former, the output of the shaping filter is connected to the first input of the first adder, the output of which is connected to the input of the unit with glasovaniya, and the second input is combined with the third input of the first frequency converter with a complex output and connected to the first output of the pilot signal generator, the second output of the reference frequency block is connected to the second inputs of the accumulating adders block, the decimator, the block of accumulation of samples and the calculation of the discrete Fourier transform and analyzer frequency shift, the third output of the block of reference frequencies is connected to the second inputs of the frequency former of the signal spectrum transfer, address register, control unit and the fourth input of the block while grouping, synchronizing and calculating the argument, the second output of the pilot signal generator is connected to the fourth input of the first frequency converter with a complex output, the output of the input block is connected to the first input of the notch filter block, the third input of which is connected to the output of the tone power dispersion calculation block, the block output notch filters connected to the input of the automatic gain control unit, the output of the automatic gain control unit is connected to the first inputs of the narrow-band bandpass filter and liter, the output of the narrow-bandpass filter is connected to the first input of the first frequency converter with a complex output, the output of which is connected to the first input of the accumulating adders block, the output of the accumulating adders block is connected to the first input of the decimator, the decimator output is connected to the first input of the accumulation of samples and the calculation of discrete conversion Fourier, the first output of which is connected to the first input of the frequency shift analyzer, the second output of the block of accumulation of samples and the calculation of the discrete transform Fourier analyzer is connected to the third input of the frequency shift analyzer, the first output of the frequency shift analyzer is connected to the fourth input of the frequency spectrum shaper, and the second to the third input of the control unit, the filter output is connected to the first input of the second frequency converter with a complex output, the third and fourth the inputs of which are connected respectively to the first and second outputs of the spectrum transfer frequency driver, the output of the second frequency converter with a complex output is connected to the first input the second switch, the second input of which is connected to the sixth output of the control unit, the first output of the buffer storage unit is connected to the first input of the synchronization sum calculation and processing unit, the second output of the buffer storage unit is connected to the second input of the synchronization sum calculation and processing unit, the first input of the third switch is connected to the first the output of the block for computing and processing the clock sum, the first input of the fourth switch is connected to the third output of the block for calculating and processing the clock, the second input of the fourth comm the tator is connected to the output of the second adder, the third input of the clock calculation and processing unit is connected to the fifth input of the signal spectrum transfer frequency driver and is connected to the third output of the control unit, the output of the fourth switch is connected to the first input of the address register, the first input of the discrete Fourier transform unit is connected to the second the inputs of the second adder, phase discriminator of symbol-wise synchronization and the fourth input of the block for computing and processing the clock and connected to the output of the address register, second the output of the discrete Fourier transform block is connected to the first input of the group for grouping, synchronizing and computing the argument and the input of the block for calculating the variance of the tone power, the third output of the discrete Fourier transform block is connected to the fifth input of the block for calculating and processing the synchro sum, the second input of the grouping, synchronization and argument computation unit is combined with the first input of the frequency spectrum transfer former of the signal and connected to the fifth output of the block for calculating and processing the clock sum, the third input of the group block argument synchronization and calculation is connected to the second output of the block for evaluating the values of symbols and the reference phase, the output of the grouping block, synchronization and calculation of the argument is connected to the first input of the block of calculators of the informative phase increment, the first input of the block for evaluating the values of the symbols and the reference phase is connected to the output of the switching block , the second output of the block for computing and processing the clock sum is connected to the first input of the phase discriminator of symbol-based synchronization, the fourth output of the block for calculating and processing the clock sum is connected to the fourth input of the control unit, the first input of the second adder is connected to the output of the phase discriminator of symbolic synchronization, the output of the informative phase increment calculator unit is connected to the first input of the switching unit, the second input of which is connected to the output of the training sequence encoder-drive, and the third input is connected to the first output of the control unit, the input of the training encoder-drive is connected to the output of the training sequence generator.

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