RU2446559C1 - Data transfer controller with pseudorandom operating frequency tuning - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: device includes five registers (1, 2, 3, 4, 5), (K+7) arithmetic logic devices (9₁-9_k, 6, 8, 10, 13, 15, 20, 22), two adder units (7, 18), (K+3) comparator units (11₁-11_k, 14, 34, 36), (K+4) latch registers (12₁-12_k, 16, 17, 19, 21), (M+1) probabilistic arithmetic logic devices (23₁-23_M+1); M code arithmetic logic devices (24₁-24_M), M probabilistic comparator units (25₁-25_M), M code comparator units (26₁-26_M), (M+1) code latch registers (27₂-27_M+1), (K+3) decoders (29₁-29_k, 28, 30, 31), M probabilistic decoders (32₁-32_M), M code decoders (33₁-33_M), and two demultiplexers (35, 37).

EFFECT: increasing data transfer validity owing to minimising the action of natural and intentional interference on the equipment.

2 dwg

Description

The invention relates to the field of radio engineering and may find application in adaptive radio means of special radio communication for transmitting data over a radio channel under the influence of a complex of intentional interference.

A known communication controller described in [1], which includes a multi-mode controller, a cell reselect predictor associated with a multi-mode controller, and a handoff controller associated with a multi-mode controller. The multi-mode controller is designed to generate control signals for switching between the first mode of operation, which does not support a communication connection during cell reselection, and the second mode of operation, which supports a communication connection during a handoff, until the time at which the need for reselecting a cell.

Known controller channel inter-block exchange, described in [2], in which the exchange of information between computers and external devices is carried out by frames consisting of a header and data. The address of the external device, the number of transmitted words and the direction of transmission are transmitted in the header.

The disadvantage of the above devices is the lack of adaptation of the clock signal to changes in the interference situation in the event of intentional interference.

The closest in technical essence to the claimed is a programmable controller described in [3], adopted as a prototype.

The functional diagram of the prototype device is shown in figure 1, where the following notation:

1 - first register;

2 - second register;

3 - third register;

4 - the fourth register;

5 - fifth register;

29 - decoder;

106 - transmitter unit;

107 - write buffer;

108 - transmitter bit counter;

109 - output multiplexer;

110 - receiver unit;

111 - read buffer;

112 - sixth register;

113 - block logic exchange;

114 - receiver bit counter;

116 - transmitter frequency divider;

117 - receiver frequency divider;

118 - transmitter clock generation unit;

119 - transmitter clock multiplexer;

120 - transmitter clock signal converter;

121 - receiver clock generation unit;

122 - receiver clock multiplexer;

123 - receiver clock;

124 - transmitter control signal generation unit;

125 - transmitter control signal shaper;

126 - transmitter control signal converter;

127 - receiver control signal generation unit;

128 - receiver control signal shaper;

129 - Converter control signal receiver;

130 - terminal control unit.

The prototype device contains the control and status registers of the receiver and transmitter (the first register is the transmitter control register, the second register is the transmitter status register, the third register is the receiver control register, the fourth register is the receiver status register), the frequency dividers of the receiver and transmitter, clock generation blocks receiver and transmitter, each of which consists of a clock multiplexer and a clock converter, blocks for generating control signals of the receiver and transmitter ka, each of which consists of a driver of control signals and a converter of control signals, a transmitter unit consisting of a write buffer, counter and multiplexer, a receiver unit consisting of a read buffer, an exchange logic block, sixth register - receive register, counter and decoder, block pin management, fifth register - pin control register.

The prototype device operates as follows.

The controller circuit is functionally divided into two parts - a receiver and a transmitter. At the same time, the receiver and transmitter can work both independently (operating on different interfaces and at different frequencies), and in a dependent state (in this case, the control and clock signals of the transmitter are duplicated for the receiver), which allows the receiver and transmitter to use one control and one clock signal when the port works on one interface.

The exchange logic 113 performs zeroing or padding with the high bit value of the excess bits. This avoids additional software processing and possible errors when receiving words less than the length of the reception register. Sampling data through a multiplexer and recording using a decoder allows you to transfer words of arbitrary length with both the most significant and the least significant bit forward with minimal hardware costs.

The control registers 1, 3 allow independent programming of the transmitter and receiver. The state registers of the transmitter and receiver 2, 4 contain information about the status of the read buffer and the write buffer, as well as interrupt flags.

Pin Management Register 5 contains bits that let you specify the direction of each pin. Frequency dividers 116, 117 allow you to generate clock signals for the receiver and transmitter by dividing the frequency of the system clock.

The transmitter clock generation unit 118 consists of a transmitter clock signal multiplexer 119 and a transmitter clock signal converter 120. The transmitter clock multiplexer makes it possible to use both an external clock signal and a clock signal received from a transmitter frequency divider to control the transmitter block. The transmitter clock signal inverts the clock signal when the transmitter needs to operate on a negative edge. The clock generator unit of the receiver 121 consists of a clock multiplexer of the receiver 122 and a clock converter of the receiver 123.

The receiver clock multiplexer allows you to use both the clock signal received from the terminal control unit (which, in turn, can either be received from the external output or duplicate the transmitter clock signal) or the clock signal received from the receiver frequency divider to control the receiver unit. The receiver clock signal inverts the clock signal when the receiver needs to work on a negative edge. The use of clock converters allows the use of receiver and transmitter blocks in the circuit, which operate on a fixed clock edge.

The transmitter control signal generation unit 124 consists of transmitter control signal generator driver 125 and transmitter control signal converter 126. The transmitter control signal generator, in accordance with the output settings, either generates a control signal for the selected interface (in this case, the clock signal received from the clock generation logic is used ), or its reception from the external conclusions of the circuit.

The transmitter control signal converter converts the interface control signal received from the transmitter control signal generator to three universal control signals: TEN (transmit permission), ReadWB (read permission from the write buffer) and trst (transmitter counter reset).

The transmitter control signal generation unit contains the logic for generating a two-bit slave select bus. In this case, the lowest bit of the bus is sent to the output of the control signal of the transmitter, and the senior bit to the output of the control signal of the receiver, thus allowing in full duplex SPI mode to work with two parallel connected slave devices.

The control signal generation block of the receiver 127 consists of the blocks of the control signal generator of the receiver 128 and the control signal converter of the receiver 129. In accordance with the output settings, the control signal generator of the receiver either generates a control signal for the selected interface (in this case, the clock signal received from the clock generation logic is used ), or its reception from the external conclusions of the circuit. The receiver control signal converter converts the interface control signal received from the receiver control signal generator to three universal control signals: REN (receive permission), WriteRB (write write buffer enable) and rrst (receiver counter reset).

The control signals generated by the control signal generation blocks for the receiver and transmitter are universal and do not depend on the selected transmission protocol. This allows the use of universal receiver and transmitter units in the circuit, which significantly simplifies the logic of the circuit. In addition, control signals are generated automatically, which allows the controller to transmit data without the participation of the processor. The blocks for generating the control signals of the receiver and transmitter also contain the logic for automatically detecting the channel for operation in I2S mode, and the block for generating the control signals of the transmitter contains the logic for generating a two-bit signal for selecting the slave for full duplex SPI mode.

In general, the receiver and transmitter can operate independently. However, it is possible for the receiver to operate in a transmitter-dependent mode.

In the prototype device, the correct decoding of information is effective only under conditions of unintentional interference. In special radio communications, the central direction is to increase noise immunity in the conditions of continuous improvement of radio countermeasures (SRP), in particular, when a radio line with frequency hopping is exposed to suppress one of the delayed interference, effective from the point of view of energy capabilities, in combination with barrage interference in a part of the band STD).

The last condition indicates that the unchanged radio line formed by the operation of the prototype device is not able to provide the specified quality of communication throughout the communication session, since the input conditions may change from time to time. Thus, the disadvantage of the prototype device is the low quality of information transfer under conditions of intentional interference. In this case, there is a need to use an adaptive control device, which, using a regular search process, constantly searches for the optimum within an acceptable class of capabilities.

The task of the invention is the introduction of adaptation of a control device for transmitting data with frequency hopping to changes in the interference environment and reducing information loss.

The technical result achieved in this case is to minimize the impact of natural and deliberate interference on communication equipment, of which this controller is an integral part, and to increase the reliability of information transfer.

To accomplish this task, in the microcontroller containing five registers and a decoder, according to the invention, two adders, two demultiplexers, (K + 3) comparators, M code comparators, M probability comparators, (K + 4) latch registers, (M + 1) are introduced ) code register-latches, (K + 2) decoders, M code decoders, M probabilistic decoders, (K + 7) arithmetic logic devices (ALU), M code ALU and (M + 1) probabilistic ALUs, with the output of the first register through the series-connected (K + 1) -th ALU, (K + 5) -th ALU, (K + 1) -th comparator, (D +2) -th decoder, (K + 1) -th register-latch, second adder, (K + 6) -th ALU, (K + 3) -th comparator and (K + 3) -th decoder connected to the second the input of the second adder; the output of the second register through a series-connected (K + 3) -th ALU, (K + 2) -th comparator, (K + 1) -th decoder, the first adder and the first demultiplexer connected to the second inputs of the (K + 5) -th ALU , (K + 6) th ALU, (K + 7) th ALU and 1st M-th code ALU; the output of the first adder is connected, in addition, to the second input of the (K + 3) -st ALU, and the second output of the (K + 1) -st ALU is connected to the third input of the (K + 3) -st ALU, the fourth input of which, combined with the second input of the (K + 3) -th register-latch is the third input of the device; the output of the (K + 3) -th register-latch is connected to the third input of the second adder, the output of which is connected, in addition, through the second demultiplexer with the first input of the (K + 4) -th register-latch, the output of which is connected to the fifth input by a bus (K + 7) -th ALU and with the output of (K + 2) -th register-latch, is the second output of the device; the second output of the (K + 3) -th decoder is connected to the second input of the (K + 4) -th register-latch; the output of the (K + 3) -th comparator is connected, in addition, to the second input of the second demultiplexer, and the second output of the (K + 5) -th ALU is connected by a bus to the (K + 2) -th latch register; the fourth input of the (K + 6) th ALU connected to the fourth input of the (K + 7) th ALU is the fourth input of the device; the output of the (K + 2) -th comparator is connected, in addition, to the second input of the 1st demultiplexer; the output of the fourth register is connected to the fourth input of the (K + 5) -th ALU and the first input of the (K + 7) -th ALU, the output of which is the third output of the device; the output of the third register is connected to the second input of the first adder; the second output of the (K + 1) -st decoder is connected to the third inputs of the (K + 5) -th, (K + 6) -th and (K + 7) -th ALU, as well as with the first inputs of the 1st-М- th code ALU, wherein the output of each i-th code ALU (where i∈ [1, ..., M]) is connected to the first input of the corresponding i-th code comparator, the output of which is connected to the input of the corresponding i-th code decoder; the bus-connected inputs of the 1st (M + 1) -st probabilistic ALU are the second input of the device, and the output of each i-th probabilistic ALU is connected to the first input of the corresponding i-th probabilistic comparator, the output of which is connected to the input of the corresponding i-th probabilistic decoder; the output of the (M + 1) -th probabilistic ALU is connected to the second inputs of the 1st-Mth probabilistic comparators; the second output of each i-th code decoder is connected to the input of the corresponding i-th code register-latch; the output of the (M + 1) th code register-latch connected to the outputs of the 1st-M-th code register-latches is the fourth output of the device; the output of the fifth register is connected to the second input of the (K + 1) -th comparator; the combined inputs of the 1st - Kth ALU are connected by a bus to the first input of the device, and the output of each jth ALU (where j∈ [1, ..., K]) is connected to the corresponding jth input of (K + 2) ALU, the output of which is connected to the inputs of the 1st - Kth comparators, and the output of each jth comparator is connected to the input of the corresponding jth decoder, the output of which is connected to the input of the corresponding jth register-latch, the output of which is connected to the corresponding the j-th input of the (K + 4) -st ALU, the output of which is connected to the fifth input of the (K + 5) -st ALU; in addition, the outputs of the 1st - Kth register-latches are combined in the first output of the device; the second output of each ℓ-th decoder (where ℓ∈ [1, ..., K-1]) is connected to the second input of the corresponding (ℓ + 1) -th comparator, and the output of each β-th probabilistic decoder, where β∈ [1, ..., M-1], combined with the output of the corresponding β-th code decoder, connected to the input of the corresponding (β + 1) -th probabilistic comparator; the second output of each probabilistic decoder is connected to the input of the corresponding code comparator; the output of the Mth probabilistic decoder is connected to the input of the (M + 1) th code register-latch, and the output of the Mth code decoder is connected to the third input of the first adder; the clock inputs of each of the above blocks are connected to the fifth, synchronizing input of the device.

Functional diagram of the inventive device is shown in figure 2, where the following notation:

1 - first register;

2 - second register;

3 - third register;

4 - the fourth register;

5 - fifth register;

6 - (K + 1) -th arithmetic logic unit (ALU);

7 - the first adder;

8 - (K + 2) th ALU;

9 ₁ -9 _K - 1st-K-th ALU;

10 - (K + 3) th ALU;

11 ₁ -11 _K - from the 1st to the Kth comparators;

12 ₁ -12 _K - from the 1st to the Kth registers-latches (RE);

13 - (K + 4) th ALU;

14 - (K + 1) -th comparator;

15 - (K + 5) th ALU;

16 - (K + 1) th RE;

17 - (K + 2) th RE;

18 - second adder;

19 - (K + 3) th RE;

20 - (K + 6) th ALU;

21 - (K + 4) th RE;

22 - (K + 7) th ALU;

23 ₁ -23 _{M + 1} - from the 1st to (M + 1) -th probabilistic ALUs;

24 ₁ -24 _M - from the 1st to the M-th code ALU;

25 ₁ -25 _M - from 1st to Mth probability comparators;

26 ₁ -26 _M - from the 1st to the Mth code comparators;

27 ₁ -27 _{M + 1} - from the 1st to (M + 1) -th code RE;

28 - (K + 1) -st decryptor;

29 ₁ -29 _K - from the 1st to the Kth decoders;

30 - (K + 2) th decryptor;

31 - (K + 3) -st decryptor;

32 ₁ -32 _M - from the 1st to the Mth probabilistic decoders;

33 ₁ -33 _M - from the 1st to the Mth code decoders;

34 - (K + 2) th comparator;

35 - the first demultiplexer;

36 - (K + 3) -th comparator;

37 - the second demultiplexer.

The inventive device contains a series-connected first register 1, (K + 1) th ALU 6, (K + 5) th ALU 15, (K + 1) th comparator 14, (K + 2) th decryptor 30, ( К + 1) -th register-latch (РЗ) 16, second adder 18, (К + 6) -th ALU 20, (К + 3) -th comparator 36 and (К + 3) -th decoder 31, the output of which connected to the second input of the second adder 18; series-connected second register 2, (K + 3) th ALU 10, (K + 2) th comparator 34, (K + 1) th decryptor 28, the first adder 7 and the first demultiplexer 35, the output of which is connected to the second inputs (K + 5) th ALU 15, (K + 6) th ALU 20, (K + 7) th ALU 22, as well as with the second inputs of M code ALU 24 ₁ -24 _M. The output of the first adder 7 is connected, in addition, to the second input of the (K + 3) th ALU 10, and the second output of the (K + 1) th ALU 6 - with the third input of the (K + 3) th ALU 10, the fourth input which is the third input of the device connected to the second input of the (K + 3) th RE 19, the output of which is connected to the third input of the second adder 18, the output of which is also connected to the first input of the second demultiplexer 37, the output of which is connected to the first input (K + 4) th RZ 21, the output of which, connected by a bus with the fifth input of the (K + 7) th ALU 22 and with the output of the (K + 2) th RZ 17, is the second output of the device. The output of the (K + 3) th decoder 31 is connected to the second input of the (K + 4) th RP 21. The output of the (K + 3) th comparator 36 is connected, in addition, to the second input of the second demultiplexer 37. The second output (K The +5) th ALU 15 is connected by a bus to the input of the (K + 2) th RE 17. The fourth input of the (K + 6) th ALU 20 connected to the fourth input of the (K + 7) th ALU 22 is the fourth input devices. The output of the (K + 2) th comparator 34 is also connected to the second input of the first demultiplexer 35. The output of the fourth register 4 is connected to the fourth input of the (K + 5) th ALU 15 and the first input of the (K + 7) th ALU 22, output which is the third output of the device. The output of the third register 3 is connected to the second input of the first adder 7.

The second output of the (K + 1) th decoder 28 is connected to the third inputs of the (K + 5) th ALU 15, (K + 6) th ALU 20 and (K + 7) th ALU 22, as well as with the first inputs 1st, ..., Mth code ALU 24 ₁ -24 _M , and the output of the i-th code ALU 24 _i (where i∈ [1, ..., M]) is connected to the input of the i-th code comparator 26 _i , output which is connected to the input of the i-th code decoder 33 _i .

The bus-connected inputs of the 1st (M + 1) -th probabilistic ALU 23 ₁ -23 _{M + 1} are the second input of the device, and the output of the i-th probabilistic ALU 23 _{i is} connected to the input of the i-th probabilistic comparator 25 _i , the output of which connected to the input of the i-th probabilistic decoder 32 _i .

The output of the (M + 1) -th probabilistic ALU 23 _{M + 1 is} connected to the second inputs of the 1st- _Mth probability comparators 25 ₁ -25 _M. The output of the i-th code decoder 33 _{i is} connected to the input of the i-th code RE 27 _i . The combined outputs of the 1st-Mth code РЗ 27 ₁ -27 _{М are} combined with the output of the (М + 1) -th code РЗ 27 _{М + 1} into the fourth output of the device.

The output of the fifth register 5 is connected to the second input of the (K + 1) th comparator 14. The combined inputs of the 1st - Kth ALU 9 ₁ -9 _{K are} connected by a bus to the first input of the device, and the output of the jth (where j∈ [ 1, ..., K]) ALU 9 ₁ -9 _{K is} connected to the corresponding j-th input of the (K + 2) -st ALU 8, the output of which is connected to the inputs of the 1st - Kth comparators 11 ₁ -11 _K , and the output of the jth comparator 11 _{j is} connected to the input of the jth decoder 29 _j .

The output of the j-th decoder 29 _{j is} connected to the input of the j-th RE 12 _j , the output of which is connected to the j-th input of the (K + 4) th ALU 13, the output of which is connected to the fifth input of the (K + 5) th ALU 15 . Also, the outputs of the 1st - Kth RE 12 ₁ -12 _K are combined into the first output of the device.

The second output of the ℓ-th decoder 29 _ℓ , where ℓ∈ [1, ..., K-1], is connected to the second input of the (ℓ + 1) -th comparator 11 _{ℓ + 1} . The output of the β-th probabilistic decoder 32 _β , where β∈ [1, ..., M-1], is combined with the output of the corresponding β-th code decoder 33 _β and connected to the input of the (β + 1) -th probabilistic comparator 25 _{β + 1} . The second output of each probabilistic decoder 32 _{i is} connected to the corresponding input of the code comparator 26 _i . The output of the Mth probabilistic decoder 32 _{M is} connected to the input of the (M + 1) th code RE 27 _{M + 1} . The output of the Mth code decoder 33 _{M is} connected to the third input of the first adder 7.

The clock inputs of each of the five registers 1, 2, 3, 4 and 5, the first 7 and second 18 adders, the first 35 and second 37 demultiplexers, (K + 1) comparators 11 ₁ -11 _K and 14, M code comparators 26 ₁ -26 _M , M probability comparators 25 ₁ -25 _M , (K + 4) latch registers 12 ₁ -12 _K , 16, 17, 19 and 21, (M + 1) code latch registers 27 ₁ -27 _{M + 1} ( K + 3) decoders 29 ₁ -29 _K , 28, 30, 31, M code decoders 33 ₁ -33 _M , M probabilistic decoders 32 ₁ -32 _M , (K + 7) ALU 9 ₁ -9 _K , 6, 8 , 10, 13, 15, 20, 22, M code ALUs 24 ₁ -24 _M , (M + 1) probabilistic ALUs 23 ₁ -23 _{M + 1 are} connected to the fifth, synchronizing input of the device.

The inventive device operates as follows.

The work begins with the zero state of block 3, where the number of information slots is zero (δ = 0), and also with the assignment in block 1 of the frequency tuning time Tn = const 1, in block 2 - the values of the frequency synthesizer desync time Tr = const 2, in block 4, the values of the number of repetitions of synchronization slots d = const 3; and in block 5, the values of the minimum required number of bits in service frames e = const 4.

Based on the value of block 1, in block 6, the required number of frequency tuning bits is calculated:

,

,

where V is the transmission rate in the radio;

[] is the integer part.

In block 7, the value of block 3 is initially increased by one, and this value is loaded into block 35.

Based on the values of blocks 6, 2, 7 and the value of the technical information transfer rate V from the 3rd input of the device, in block 10, the value of the number of information bits of the slot is calculated:

,

,

where q = [x · λ] - the number of protective bits of the information slot;

λ ₂ is a coefficient depending on the amount of frequency hopping frequency and a priori known signal propagation conditions (for example, for a fixed frequency, you can take λ ₂ ≈3%; for frequency hopping from two frequencies - λ ₂ ≈6%, etc.).

The resulting value of x goes to block 34, where the condition x - integer is checked.

From block 34, blocks 35 and 28 receive a signal that is a control signal for these blocks:

- if condition x - the integer is not fulfilled, then this signal is a logical "0", which in block 35 prohibits the output signal, and in block 28 sends the signal to block 7, where the value of this block increases by one and this value is loaded into blocks 35 and 10;

- if condition x is an integer, then this signal represents the value of x, which through block 28 is loaded into blocks 15, 20, 22, 24 ₁ -24 _M , and in block 35 it enables the output signal, and from this block the value δ comes into blocks 15, 20, 22, 24 ₁ -24 _M.

,

, …,

, соответственно (n₁, n₂,…, n_M - длины тех М помехоустойчивых кодов, которые используются в данном радиосредстве).In blocks 24 ₁ -24 _{M, the} number of codewords in the information frame is calculated

,

, ...,

, respectively (n ₁ , n ₂ , ..., n _M are the lengths of those M error-correcting codes that are used in this radio).

From the first entrance to the blocks 9 ₁ -9 _K , the quality characteristics of the synchronization channel are received via the data bus to determine the probabilities of the correct reception of P _pr and false alarm R _lt [4]. In these blocks the calculation of average risks R _j (j = 1 ... K) is performed according to the formula:

R = a · P · _nal.sign (1-P _pr) + b · P · _ots.sign (1-P _Lt),

where R _s.sign - the a priori probability of the absence of a signal;

P _nal.sign - the a priori probability of the presence of a signal;

a and b are weights, depending on how dangerous P _lt is compared to 1-P, _etc.

Obtained in the unit 9 ₁ -9 _K values medium risks R ₁ -R _K received in block 8, which defines a minimum value of them - min, is supplied to block 11 ₁ -11 _K, each of which generates control signals for the unit 29 ₁ -29 _K , respectively.

In blocks 11 _ℓ , where ℓ∈ [1, ..., K-1], sequentially, starting from block 11 ₁ , the following conditions are checked:

- if the condition min = R _ℓ is satisfied, then the control signal is a logical "1", which directs the signal from block 29 _ℓ to block 12 _ℓ , where the value of the sync sequence length L = L _{ℓ is} assigned; if the condition min = R _{ℓ is} not satisfied, then the control signal is a logical "0", which routes the signal from block 29 _ℓ to block 11 _{ℓ + 1} , where the condition min = R _{ℓ + 1} is checked.

Then, in block 11 _K , the conditions are checked:

- if the condition min = R _K is satisfied, then the control signal is a logical "1", which routes the signal from block 29 _K to block 12 _K , where the value of the sync sequence length L = L _{K is} assigned; if the condition min = R _{K is} not satisfied, then the control signal is a logical "0", which does not allow to transmit a signal from block 29 _K.

The value of one of the blocks 12 ₁ -12 _K , where the assignment occurred, is sent to the first output of the controller to regulate the type of synchronization sequence at the transmitting and receiving parts of the radio, which includes this controller, and to block 13, where the number of protective bits of the service slot is calculated:

z = [L · λ ₁ ],

where [] is the integer part, and λ ₁ is a coefficient depending on the number of frequency hopping frequencies and a priori known signal propagation conditions, similar to that described above.

The values of blocks 4, 6 and 13 are entered into block 15, where the number of bits in the frame is calculated Ψ = (y + L + z) · d + (y + x + q) · δ. The values of y, L, x, z, d, Ψ and δ are written to the block 17 via the data bus and fed to the second output of the controller via the data bus to adjust the type of packet on the transmitting and receiving parts of the radio, which includes this controller.

The value of the necessary information transfer rate C supplied from the fourth input of the device, as well as the value Ψ obtained in block 15 and the value of block 18, are loaded into block 20, where the calculation of the value of the packet transmission time takes place:

.

.

The obtained value of T goes to block 36, where the condition T is checked - the final decimal fraction. From block 36, blocks 31 and 37 receive a signal that is a control signal for these blocks:

- if condition T - the final decimal fraction is not fulfilled, then this signal is a logical "0", which in block 37 prohibits the output signal, and in block 31 sends the signal to block 18, where the value of this block increases by one and this the value is loaded into blocks 37 and 20;

- if condition T is the final decimal fraction, then this signal represents the value of T, which through block 31 is loaded into blocks 21, and in block 37 enables the output signal, and from this block the value δ goes to block 21.

From block 21, the values of T and g are transmitted via the data bus to the second output of the controller to adjust the type of packet on the transmitting and receiving parts of the radio, which includes this controller. In addition, the values of T and g from block 21 via the data bus are loaded into block 22. The value of block 4 and the value of the necessary information transfer rate C from the fourth input of the device are also loaded here, and the frequency hopping speed is calculated:

From block 22, the value of γ is supplied to the third output of the controller for adjustment by the modulation and demodulation processes at the transmitting and receiving, respectively, parts of the radio, which includes this controller.

From block 15, the value of Ψ, in addition, is loaded into block 14, where the condition e≤Ψ is checked. From block 14 to block 30 receives a signal that is a control signal for this block:

, где [] - целая часть на основании поступающего значения технической скорости передачи информации V с 3-го входа устройства;- if the condition e≤Ψ is not satisfied, then this signal is a logical "0", which sends the signal to block 19, where the assignment

, where [] is the integer part based on the incoming value of the technical information transfer rate V from the 3rd input of the device;

- if condition T is the final decimal fraction, then this signal is a logical "1", which sends the signal to block 16, where the assignment g = 0.

The value of that of blocks 16 or 19, where the assignment occurred, is loaded into block 18, where it increases by one.

From the second input to blocks 23 ₁ -23 _{M + 1} , the characteristics of the information channel are received via the data bus to determine the probabilities of the correct reception of W, W ₁ -W _M code words of those M noise-resistant codes that are used in this radio (W is calculated for the case when error-correcting code is not used) [5]. Received in blocks 23 ₁ -23 _M values W ₁ -W _M are received, respectively, in blocks 25 ₁ -25 _M.

The value of the block 23 _{M + 1} also enters each of the blocks 25 ₁ -25 _M , each of which generates control signals for blocks 32 ₁ -32 _K , respectively. In blocks 25 _β , where β∈ [1, ..., M-1] sequentially, starting from block 25 ₁ , the conditions are checked:

- if the condition W _β > W is satisfied, then the control signal is a logical "1", which routes the signal from block 32 _β to block 26 _β , where Ω _β is compared with an integer; if the condition W _β > W is not satisfied, then the control signal is a logical "0", which routes the signal from block 32 _β to block 25 _{β + 1} , where the condition W _{β + 1} > W is checked.

Then, in the 25 _M block, the conditions are checked:

- if the condition W _M > W is satisfied, then the control signal is a logical "1", which routes the signal from block 32 _M to block 26 _M , where Ω _M is compared with an integer; if the condition W _M > W is not satisfied, then the control signal is a logical "0", which directs the signal from the 32 _M block to the 27 _{M + 1} block, where i = 0 is assigned.

The values of Ω ₁ , Ω ₂ , ..., Ω _M calculated in blocks 24 ₁ -24 _M arrive, respectively, in blocks 26 ₁ -26 _M , each of which generates control signals for blocks 33 ₁ -33 _M , respectively. In blocks 26 _β , where β∈ [1, ..., M-1], sequentially, starting from block 26 ₁ , the conditions are checked:

- if the condition is satisfied that Ω _β is an integer, then the control signal is a logical "1", which routes the signal from block 33 _β to block 27 _β , where the assignment i = β; if the condition that Ω _{β is} not an integer, then the control signal is a logical "0", which routes the signal from block 33 _β to block 25 _{β + 1} , where the condition W _{β + 1} > W is checked.

Then, in a block of 26 _M , the conditions are checked:

- if the condition is satisfied that Ω _M is an integer, then the control signal is a logical "1", which routes the signal from block 33 _M to block 27 _M , where the assignment i = M; if the condition that Ω _M is an integer is not fulfilled, then the control signal is a logical "0", which routes the signal from block 33 _M to block 7, where the value of block 7 increases by one.

The value of that of the blocks 27 ₁ -27 _{M + 1} , where the assignment occurred, is sent to the fourth output of the controller to adjust the type of error-correcting code on the transmitting and receiving parts of the radio, which includes this controller.

From the 5th input of the controller, clock pulses are sent to blocks 1-37 via the data bus, which determine the beginning of each microoperation, as a result of which the operation of the device as a whole is synchronized.

Registers, ALUs, adders, comparators, decoders and demultiplexers can be implemented physically based on the elements described in [8]. Latch registers can be implemented physically based on the elements described in [7].

The controller as a whole can be implemented as a reprogrammable digital device [6].

Thus, the introduction of new blocks and communications in the claimed device allows to increase the reliability of receiving information by adapting to changes in the interference environment, which allows it to be used in special communications under the influence of intentional interference.

Information sources

1. RF patent for the invention No. 2366107 "Communication controller and method for maintaining communication connection during the re-selection of a cell. Sheiman A., Black G., Song M., 2007.

2. RF patent for the invention No. 2345407 "Controller channel inter-block exchange", Gorshkov SN, 2007.

3. RF patent for the invention No. 2360282 "Programmable controller of serial buses." Putrya F.M., 2007.

4. Noise-like signals in information transmission systems./ Ed. prof. V. B. Pestryakova. M., "Sov. Radio", 1973.

5. Feer. K. Wireless digital communications. Methods of modulation and spreading: Per. from English / Ed. V.I. Zhuravleva. - M., Radio and Communications, 2000.

6. Technical support for digital signal processing. Directory. Kupriyanov M.S., Matyushkin B.D., Ivanova V.E., Matvienko N.I., Usov D.Yu. - SPb. The Fort, 2000.

7. The art of circuitry. P. Horowitz, W. Hill - Moscow. "World", 1998, p.8.24.

8. Alekseenko A.G., Shakulin I.I. "Microcircuitry". Textbook for universities. - 2nd ed., Revised. and add. - Moscow, Radio and Communications, 1990.

Claims (1)

A data transfer controller with pseudo-random tuning of the operating frequency, containing five registers and a decoder, characterized in that two adders, two demultiplexers, (K + 3) comparators, M code comparators, M probability comparators, (K + 4) registers are introduced into it latches, (M + 1) code register-latches, (K + 2) decoders, M code decoders, M probabilistic decoders, (K + 7) arithmetic logic devices (ALU), M code ALU and (M + 1) probabilistic ALU, while the output of the first register through a series-connected (K + 1) -th AL , (K + 5) th ALU, (K + 1) th comparator, (K + 2) th decryptor, (K + 1) th latch register, second adder, (K + 6) th ALU , (K + 3) -th comparator and (K + 3) -th decoder connected to the second input of the second adder; the output of the second register through a series-connected (K + 3) -th ALU, (K + 2) -th comparator, (K + 1) -th decoder, the first adder and the first demultiplexer connected to the second inputs of the (K + 5) -th ALU , (K + 6) th ALU, (K + 7) th ALU and 1st - M-th code ALU; the output of the first adder is connected, in addition, to the second input of the (K + 3) -st ALU, and the second output of the (K + 1) -st ALU is connected to the third input of the (K + 3) -st ALU, the fourth input of which, combined with the second input of the (K + 3) -th register-latch is the third input of the device; the output of the (K + 3) -th register-latch is connected to the third input of the second adder, the output of which is connected, in addition, through the second demultiplexer with the first input of the (K + 4) -th register-latch, the output of which is connected to the fifth input by a bus (K + 7) -th ALU and with the output of (K + 2) -th register-latch, is the second output of the device; the second output of the (K + 3) -th decoder is connected to the second input of the (K + 4) -th register-latch; the output of the (K + 3) -th comparator is connected, in addition, to the second input of the second demultiplexer, and the second output of the (K + 5) -th ALU is connected by a bus to the (K + 2) -th latch register; the fourth input of the (K + 6) th ALU connected to the fourth input of the (K + 7) th ALU is the fourth input of the device; the output of the (K + 2) -th comparator is connected, in addition, to the second input of the 1st demultiplexer; the output of the fourth register is connected to the fourth input of the (K + 5) -th ALU and the first input of the (K + 7) -th ALU, the output of which is the third output of the device; the output of the third register is connected to the second input of the first adder; the second output of the (K + 1) th decoder is connected to the third inputs of the (K + 5) th, (K + 6) th and (K + 7) th ALU, as well as with the first inputs of the 1st - M- th code ALU, wherein the output of each i-th code ALU (where i∈ [1, ..., M]) is connected to the first input of the corresponding i-th code comparator, the output of which is connected to the input of the corresponding i-th code decoder; the bus-connected inputs of the 1st - (M + 1) -th probabilistic ALU are the second input of the device, and the output of each i-th probabilistic ALU is connected to the first input of the corresponding i-th probabilistic comparator, the output of which is connected to the input of the corresponding i-th probabilistic decoder; the output of the (M + 1) -th probabilistic ALU is connected to the second inputs of the 1st - Mth probabilistic comparators; the second output of each i-th code decoder is connected to the input of the corresponding i-th code register-latch; the output of the (M + 1) th code register-latch connected to the outputs of the 1st - Mth code register-latch is the fourth output of the device; the output of the fifth register is connected to the second input of the (K + 1) -th comparator; the combined inputs of the 1st - Kth ALU are connected by a bus to the first input of the device, and the output of each jth ALU (where j∈ [1, ..., K) is connected to the corresponding jth input of the (K + 2) th ALU the output of which is connected to the inputs of the 1st to Kth comparators, the output of each jth comparator connected to the input of the corresponding jth decoder, the output of which is connected to the input of the corresponding jth register-latch, the output of which is connected to the corresponding j the input of the (K + 4) th ALU, the output of which is connected to the fifth input of the (K + 5) th ALU; in addition, the outputs of the 1st - Kth register-latches are combined in the first output of the device; the second output of each ℓ-th decoder (where ℓ∈ [1, ..., K-1]) is connected to the second input of the corresponding (ℓ + 1) -th comparator, and the output of each β-th probabilistic decoder, where β∈ [1, ..., M-1], combined with the output of the corresponding β-th code decoder, connected to the input of the corresponding (β + 1) -th probability comparator; the second output of each probabilistic decoder is connected to the input of the corresponding code comparator; the output of the Mth probabilistic decoder is connected to the input of the (M + 1) th code register-latch, and the output of the Mth code decoder is connected to the third input of the first adder; the clock inputs of each of the above blocks are connected to the fifth, synchronizing input of the device.

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