RU2444113C2 - Device for introduction and matching of corrected and correcting signals at inputs of modulator-correctors - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device for introduction and matching of corrected and correcting signals at the inputs of modulator-correctors relates to radio engineering, to the field of linear amplification of amplitude modulated signals and may be used in systems of linearisation of power amplifier characteristics. The device comprises a modulator-corrector (2) and serially connected components: a memory device (MD) (4), a digital to analog converter (DAC) (5), a noise filter (6), the output of which is connected to a modulation input of the modulator-corrector (2), and also a digital detector (DD) (3) of the correcting signal envelope, the input of which is connected to the signal input of the device, and inputs of sync pulses of DD (3) and MD (4) data processing and transfer are connected with the input of sync parcels from the external device. The device differs by the fact that the signal input of the modular-corrector (2) is connected to the signal input of the device, and also a link of sync pulses delay (7) is introduced with a controlled external signal of time delay and a data-hold device (8), connected along the data bus between the DD (3) and the address input of the MD (4), at the same time the input of the data-hold device (8) sync pulses is connected to the input of the device sync messages directly, and the input of sync pulses to the input of data into the DAC (5) is connected to the input of the sync messages via the link of the sync pulses delay (7) with the controlled external signal of the time delay.

EFFECT: invention provides for matching of correcting and corrected signals that is controlled in the wide range of time intervals at the inputs of the modulator correctors by methods of digital technologies without application of analog delay lines.

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Description

The invention relates to radio engineering, and in particular to the field of linear amplification of amplitude-modulated signals, and can be applied in linearization systems of the characteristics of power amplifiers.

Known input devices for correcting and correcting signals, predistortion signals, in which the codes of the correcting signals generated by the linearization system and stored in the storage device, address codes of the measured envelope level of the input corrected signal are read from the storage device, subjected to digital-to-analog conversion and filtered analog signal are fed to the modulation input modulator-corrector. The correction signal at the modulation input of the modulator-corrector is delayed relative to the corrected signal at the signal input of the modulator-corrector. The delay time τ _s , determined by the inertia of the path for generating the correction signal, includes the delay time in the digital detector, in the storage device, in the digital-to-analog converter and in the noise suppression filter.

The delay leads to a mismatch in the values of the correcting and corrected signals at the inputs of the modulator-corrector and, as a result, to errors in the correction of the nonlinear characteristics of the power amplifier. The combination in time of the action of the corrected signal with the corrective in known devices is carried out using delay lines that are included on the signal inputs of modulator-corrector, that is, the delay of the corrected signal. In modulators-correctors with correctable signals in the form of digital streams, naturally, delay lines also have solutions based on digital technologies. In modulators-correctors with analog input corrected signals, the delay lines are analog.

Closest to the claimed device for inputting and combining corrective and correcting signals is the device according to the patent US 6512417 "Linear amplifier arrangement" from 01/28/2003, IPC H01F 1/26. This device is taken as a prototype.

In the prototype device, as in other known similar devices, the combination of the corrected signal in amplitude or phase and the corresponding correction signals is carried out by delaying the corrected signal using an analog delay line in the circuit of the corrected signal.

The control circuits of the modes in the prototype device, including data transmission through a circuit of a series-connected digital detector, a storage device and a digital-to-analog converter, are connected to sources of clock pulses and clock pulses ensuring the operation of the device.

Due to the uniformity of input devices and combining corrected signals and signals correcting the amplitude and phase, the principle of operation of the prototype is considered according to the generalized functional diagram presented in figure 1.

In the prototype diagram of FIG. 1, the mode control circuits are displayed as a chain of clock packages-sync pulses, starting for operations of digitizing the envelope level and transmitting data to subsequent elements of the device.

In the circuit of FIG. 1, the input of clock-start pulses, synchronizing signal processing and data transmission, is designated as “SI”, the signal analog input of the prototype device is “Bx”, the output is “Out”.

Figure 1, the input device and combining the corrective and corrected signals contains a modulator-corrector 2, the signal input of which is connected to the signal input "Bx" of the input device and combining the corrective and correctable signals through the delay line 1, and the input "Bx" of the input and combining device of the correcting and correcting signals is connected to the modulation input of the modulator-corrector 2 through sequentially connected digital detector 3 of the envelope of the corrected signal, a storage device 4, digital-to-analog an output converter 5, an interference suppression filter 6, while the inputs of the sync pulses of the digital detector 3, the storage device 4, and the digital-to-analog converter 5 are connected to the SI input of the clock parcels-sync pulses from an external source, the function of which can be performed by either a separate unit or a microcontroller (microprocessor) of the system linearization of the characteristics of the amplifier.

The device in figure 1 works as follows. According to the clock pulse from the input "SI" as the starting digital detector 3, the envelope level of the corrected signal is measured, digitized, the values of the measured envelope level are converted into codes and transmitted to the memory device 4 via the address bus of the envelope level code as the address of the cell of the memory device 4 in which it is stored correction signal level code, determined and stored for the value of the measured envelope level. According to the same clock pulse, as the start pulse, the correction signal level code is read from the memory device 4 into the digital-to-analog converter 5, from the output of which an analog signal (current, voltage) is fed through the interference suppression filter 6 to the modulation input of the modulator-corrector 2.

The clock is the key, allowing using internal or external clock pulses to process and transmit data through a serial circuit of the elements of the input device and combining the corrective and corrected signals. As a rule, the clock repetition rate corresponds to the envelope sampling frequency. The formation of the input signal from the input device and combining the correcting and correcting signals of the correcting signal takes time τ _s , consisting of the detection time with the conversion of the envelope level into code, sending the code to memory 4, reading the correcting signal code from memory 4, and loading the code into digital-to-analog Converter 5, transmission, bringing the correction signal to the modulation input of the modulator-corrector 2. Time τ _s is the time delay delaying the correction signal relative to the signal at the input of the input device and combining the correction and corrected signals.

To combine the corrected signal with the “lagging” corrective in the prototype device, between the signal input of the modulator-corrector 2, an analog delay line 1 with a delay time equal to τ _{s is} included. The combination of the delay signals of the analog corrected signal using the analog delay line is effective in a narrow band of carrier frequencies and becomes problematic in wide-band and ultra-wide-band paths due to difficulties in maintaining the characteristics of the delay lines both in the delay time and in the amplitude-frequency and frequency-phase characteristics. That is, the disadvantage of the prototype is the complexity of the structural implementation of the input device and the combination of corrective and correctable signals due to the cumbersomeness of decisions on wide-range delay lines.

The aim of the invention is the implementation of managed in a wide range of time intervals of combining corrected and correcting signals at the inputs of modulator-corrector methods of digital technology without the use of analog delay lines.

The goal is achieved by introducing into the inventive input device and combining the corrected and correcting signals of the extrapolator of the output data of a digital detector, which provides the ability to determine the values of the corrected signal with anticipation, taking into account the delay time in the path of the formation of the correcting signal, separation with time shift of synchronization pulses synchronizing signal processing and data transmission in the path of the formation of correcting signals, using the input and combination entered into the claimed device corrections and corrected signals of the delay link of the clock pulses with an external signal controlled by the delay time of the clock pulses.

The technical result is achieved by the fact that the input device and the combination of the corrected and correcting signals at the inputs of the modulator-corrector, containing the modulator-corrector and a series-connected memory device, digital-to-analog converter, an interference suppression filter, the output of which is connected to the modulation input of the modulator-corrector, as well as digital envelope detector of the corrected signal, the input of which is connected to the signal input of the input device and combining the corrected and corrective signals al, and the inputs of the clock pulses of processing and transmitting data of a digital detector and a storage device are connected to the input of the clock packets from an external device, characterized in that in order to provide controlled over a wide range of time intervals combination of corrected and correcting signals at the inputs of modulator-corrector by digital technology without using analog delay lines, the signal input of the modulator-corrector is connected to the signal output of the input device and combining the corrected and corre of the input signals and into the input and combining of the corrected and correcting signals, a delay component of the clock pulses with an external signal controlled by the delay time and an extrapolator are inserted, connected via the data bus between the Digital detector and the address input of the storage device, while the input clock of the extrapolator is connected to the input clock of the input device and combining the corrected and correcting signals directly, and the input of the clock pulses to enter data into a digital-to-analog converter sinhroposylok connected to the input through a delay unit with a clock signal controlled by an external delay time.

The entered elements of the device perform the following functions. The extrapolator calculates (extrapolates “forward”) the values of the envelope level ahead of the last read from the output of the digital detector for a certain time interval; when calculating, the values of the previous levels and the last read level are used.

Figure 2 conventionally shows the envelope U in _x (t) as a function of time t. At times t _i ... t ₁ , t ₂ , t ₃ , t ₄ , the envelope levels measured by the digital detector are read, respectively, U _i ... U ₁ , U ₂ , U ₃ , U ₄ . Using n values of the read levels, including the last read value in the extrapolator, the value of the envelope level, which is expected in the subsequent count, is calculated. The calculation is carried out according to the formula

where U _{n + 1} is the expected estimated level of the envelope when reading the first clock after the n-th last reading.

n is the number (conditional) of the last count;

i - 1, 2, 3 ... n - the number of values of the read envelope levels used in the calculations;

a _i is the weight coefficient.

Figure 2 shows a graph for n = 4, that is, the calculation of the value of U ₅ ^{* is} carried out on four sequentially read values of the envelope level at time t ₁ , t ₂ , t ₃ , t ₄ . The intervals between the times t ₁ t ₂ , t ₂ t ₃ , t ₃ t ₄ , t ₄ t ₅ are the sampling intervals of the envelope ΔT.

The delay link of the clock pulses with an external signal controlled by the delay time delays the pulses (pulse edges for a given delay time), that is, it is a digital pulse delay line (shift registers, counters, timers, etc.).

Based on the calculated value of the envelope level U ₅ ^* from the storage device, the value of the correction signal necessary for the level U ₅ ^{* is} read and entered into the circuit for converting the codes of the correction signal to the correction signal with a lead (value).

A functional diagram of the claimed input device and combining the corrected and correcting signals at the inputs of modulators-correctors is presented in figure 3.

The input device and combining the corrected and correcting signals at the inputs of modulator-corrector, shown in figure 3, contains a modulator-corrector 2, the input of which is connected to the signal input "Bx" input device and combining the corrected and correcting signals directly (without delay lines), a memory device 4, a digital-to-analog converter 5, an interference suppression filter 6, the output of which is connected to the modulation input of the modulator-corrector 2, a digital detector 3 of the envelope the projected signal, the input of which is connected to the signal input "Bx", and the inputs of the clock pulses of processing and transmitting data of the digital detector 3 and the storage device 4 are connected to the input "SI" of the clock packets from an external device, the extrapolator 8 of the output data of the digital detector 3, connected between the digital detector 3 and the address input of the storage device 4, the delay link 7 of the clock pulses with an external delay time controlled by the external signal, while the input of the extrapolator 8 clock pulses is connected to the SI input ok directly, and the inputs of the clock pulses of the digital-to-analog converter 5 are connected to the input "SI" of the clock packages through the link 7 of the delay of the clock pulses.

The introduction into the device of the extrapolator 8 and the link 7 of the delay of the clock pulses with an external controlled delay time and the separation of the feed channels of the clock pulses into circuit elements allow combining the corrected and correcting signals at the inputs of the modulator-corrector 2 not with a time delay of the corrected signal, but with the formation of time delays in the path of the correction signal, anticipating the value of the value of the correction signal necessary to correct the level of the input signal of the input device and combining the corrected and correction signals when simultaneous arrival of the inputs of the equalizer modulator 2.

The claimed device for inputting and combining corrective and correcting signals at the inputs of modulators-correctors works as follows. A sync pulse from the SI input of a device for inputting and combining corrective and correcting signals from an external clock source, a digital detector 3, an extrapolator 8, and a memory device 4 are entered into modes that provide the internal or external necessary clock pulses, pulse packets, performing a certain sequence of the following operations: generating the output of the digital detector 3, transferring data from the output of the digital detector 3 to the registers of the extrapolator 8, calculation of the extrapolator 8 the expected envelope value of the envelope of the corrected input signal calculated with a lead in time, entering the code of the calculated envelope level into the address bus of the memory device 4, and outputting to the bus or the buffer output register of the memory device 4 from the cell of the code of the level of the correction signal necessary to correct the input signal with an envelope level equal to the calculated. The table of correspondence of the levels of corrective and correctable signals determined during testing of the amplifier is stored in memory in the cells of the storage device 4 in the form:

cell address - envelope level code;

data is a correction signal code.

The clock pulse received at the inputs of the clock pulses of the digital detector 3, extrapolator 8, the storage device 4, is simultaneously fed to the input of the link 7 delay clock. The output pulse of the sync delay link 7 is the starting clock to read the correcting signal level code 4 from the output of the memory 4 and input this code into the digital-to-analog converter 5. The output pulse of the sync delay link 7 is shifted (delayed) relative to the main input for the sync delay link 7 time Δτ set by an external signal.

In the inventive device for inputting and combining corrective and correcting signals at the inputs of modulators-correctors for the path of formation of the correcting signal, the following time relationships for the delay times take place:

τ _d - the delay time of the output signal of the digital detector 3, the time taken to generate the codes of the measured envelope level of the corrected signal;

τ _a is the formation time from the code word by the digital-analog converter 5 of the analog signal and the signal delay by the interference suppression filter 6;

τ _DAC - the time of digital signal processing from the input of the extrapolator 8 to the output of the storage device 4.

The inertia of the digital detector 3 τ _d leads to the fact that the output of the digital detector 3, generated and read at time t _i , corresponds to the level of the envelope at the instant of time t _i -τ _d (Fig. 4).

Therefore, the calculated value of the envelope level in the above example U ₅ ^* for the moment of reading t ₅ will be the value of the envelope level for the time t ₅ -τ _d , this is the input time of the correcting analog signal for the envelope level that takes place at time t ₅ - τ _d But from the moment the code is entered into the digital-to-analog converter 5, the analog signal reaches the modulation input of the modulator-corrector 2 after a time equal to τ _and , therefore, the input of the correction signal code to the digital-to-analog converter 5 must be anticipated by τ _and relative to real time t ₅ -τ _d . That is, at time t ₅ -τ _d -τ _a or relative to the last sample t ₄ + ΔТ-τ _d -τ _a (ΔT - envelope sampling intervals, arrival intervals of clock pulses). The clock pulse for entering the code in the digital-to-analog converter 5 should be applied at time t ₄ + ΔТ-τ _d -τ _а , that is, with a delay relative to time t _{4 of the} last readout by the value ΔТ-τ _д -τ _а , which corresponds to the future future reading time t ₅ at the time τ _d + τ _a .

The delay time equal to ΔT-τ _d -τ _a is provided by setting the delay time in the delay link 7 of the clock pulses.

The time τ _{DAC of the} digital signal processing should be less than the delay time ΔТ-τ _д -τ _а , since at the moment of inputting the data (codes) of the correction signal to the digital-to-analog converter 5, these data must be generated and take place at the output of the storage device 4.

The claimed device for inputting and combining corrective and correcting signals at the inputs of modulators-correctors has the following qualities:

- the combination of the corrected and correcting signals at the inputs of the modulators-correctors is controlled by the introduction of the link 7 delay pulses with a controlled external signal delay time;

- in the input device and combining the corrected and correcting signals at the inputs of the modulator-corrector there is no analog delay line, problematic for wide-range devices, which increases the manufacturability of the claimed device using the electronic hardware base.

The implementation of the input and combining the corrected and correcting signals of the extrapolator and the delay component of the clock pulses with an external signal controlled by the delay time based on the modern high-speed element base of digital FPGA technology is not difficult.

Claims (1)

A device for inputting and combining corrective and correcting signals at the inputs of modulator-corrector, containing a modulator-corrector and a series-connected memory device, a digital-to-analog converter, an interference suppression filter, the output of which is connected to the modulation input of the modulator-corrector, as well as a digital envelope detector of the corrected signal, input which is connected to the signal input of the input device and combining the corrected and correcting signals, and the inputs of the processing clock and Data transmissions of a digital detector and a storage device are connected to the input of sync packets from an external device, characterized in that, in order to provide a wide range of time intervals for combining corrected and correcting signals at the inputs of modulator-corrector using digital technology without the use of analog delay lines, a signal input the modulator-corrector is connected to the signal input of the input device and combining the corrected and correcting signals, and to the input device and combining the corrected and correcting signals, a delay component of the clock pulses with an external delay time signal controlled by an external signal and an extrapolator connected via a data bus between the digital detector and the address input of the storage device are introduced, while the sync pulse input of the extrapolator is connected to the sync input of the input device and combining the corrected and correcting signals , and the input of the clock for data input into the digital-to-analog converter is connected to the input of the clock through veno delay clock with controllable external signal delay time.

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