RU2441318C1 - Device to decode reed-solomon codes - Google Patents

Abstract

FIELD: information technologies. ^ SUBSTANCE: device comprises a buffer data memory, a unit of syndromes calculation, a Galois processor, a unit of discrete Fourier transformation, a unit for searching of weight error positions t+1, a unit of symbol positions sorting, a unit of error values calculation, a summator of Galois field elements. ^ EFFECT: higher efficiency of errors correction outside the border of the half of minimum distance by using information on reliability of symbols received from the channel. ^ 6 cl, 10 dwg

Description

The invention relates to telecommunication systems and computer engineering and may find application in devices for receiving information from a transmission channel or reproducing information with a high level of errors.

Currently, in practice, Reed-Solomon code decoding devices (PC codes) are used that implement the classical decoding algorithms (Peterson-Gorenstein-Zirler, Berlekamp-Messi, Euclid) that allow correcting no more than t erroneous characters in the codeword (t =  (d-1) / 2, d is the minimum code distance).

A device for list decoding of Reed-Solomon codes is known that corrects errors beyond half the minimum code distance t, [1], comprising: an input block, a decoding block, and an output block. The decoding method used is based on finding a nonzero element in the core of the structured matrix.

The disadvantage of this device is the complexity of its implementation.

A decoding device is known that implements an algebraic algorithm for decoding Reed-Solomon codes using soft solutions [2], comprising: a re-coding unit, an interpolation unit, a factorization unit, a block for selecting interpolation points, and a selector.

The algorithm of the device is as follows: using estimates of the reliability of the characters of the received code word, the matrix M is calculated, which determines the interpolation points and their multiplicity; the interpolation procedure is performed to find the polynomial Q _M (X, Y); in the polynomial Q _M (X, Y), factors of the form Yf (X) are distinguished; codewords are reconstructed from polynomials f (X); the most probable of them is selected as a result of the algorithm.

The disadvantage of this device is its complexity, due to the complexity of the implementation of procedures for interpolation and factorization of polynomials of large degrees.

The closest in technical essence to the claimed invention is the Reed-Solomon code decoding device selected as a prototype [3], which allows one additional error to be corrected beyond half the minimum code distance. The prototype device comprises: a data buffer, a syndrome calculation unit, a Galois processor, a discrete Fourier transform unit, an error position search unit of weight t + 1, and an error value calculation unit.

The prototype device searches for error positions beyond half the minimum code distance by calculating sequences of possible values of unknown residuals of the analytic continuation of the Berlekamp-Messi algorithm and counting the residual values in these sequences.

The disadvantage of the prototype is the relatively low speed due to the exhaustive nature of the search for unknown residuals when correcting t + 1 errors. The number of calculations of the possible values of the unknown residual is n _S = (n-1 + t) (nt) / 2, where n is the length of the code word of the Reed-Solomon code.

The speed of the decoder [3] can be increased by averaging the decoding time of code words with a different number of errors. However, in order to ensure constant bandwidth, it is necessary to introduce an additional buffer for storing codewords, which will simultaneously increase the data delay in the decoder.

An object of the invention is to increase the speed of error correction beyond half of the minimum distance by using information about the reliability of the symbols received from the channel.

The technical problem posed is solved by  what's in the Reed-Solomon code decoding device,  containing a data buffer  syndrome calculation unit,  Galois processor  discrete Fourier transform unit,  block for finding error positions,  unit for calculating error values,  the first adder of the Galois field elements,  moreover, the inputs of the buffer data memory and the inputs of the block computing syndromes are inputs of data symbols of the device for decoding Reed-Solomon codes,  the outputs of the data buffer memory are connected to the first inputs of the first adder of the Galois field elements,  the outputs of the syndrome calculation unit are connected to the first inputs of the Galois processor,  the first outputs of the Galois processor are connected to the first inputs of the discrete Fourier transform block,  the second outputs of the Galois processor are connected to the second inputs of the discrete Fourier transform block,  the third outputs of the Galois processor are connected to the third inputs of the discrete Fourier transform block,  the fourth outputs of the Galois processor are connected to the fourth inputs of the error position search unit,  the fifth outputs of the Galois processor are connected to the first inputs of the error value calculation unit,  the sixth outputs of the Galois processor are connected to the second inputs of the error value calculation unit,  the seventh outputs of the Galois processor are connected to the third inputs of the error value calculation unit,  the second outputs of the discrete Fourier transform unit are connected to the third inputs of the Galois processor,  the third outputs of the discrete Fourier transform unit are connected to the fourth inputs of the Galois processor,  the fourth outputs of the discrete Fourier transform unit are connected to the first inputs of the error position search unit,  the fifth output of the discrete Fourier transform unit is connected to the second input of the error position search unit,  the sixth outputs of the discrete Fourier transform unit are connected to the third inputs of the error position search unit,  the first outputs of the error position search unit are connected to the fifth inputs of the Galois processor,  the second outputs of the error position search unit are connected to the sixth inputs of the Galois processor,  the third outputs of the error position search unit are connected to the seventh inputs of the Galois processor,  the fourth outputs of the error position search unit are connected to the eighth inputs of the Galois processor,  the outputs of the unit for calculating error values are connected to the second inputs of the first adder of the Galois field elements,  the outputs of the first adder of the Galois field elements are the data outputs of the Reed-Solomon code decoding device,  a block for sorting character positions has been introduced,  moreover, the first inputs of the block for sorting the positions of characters are inputs of estimates of the reliability of the characters of the data of the Reed-Solomon code decoding device,  the fifth outputs of the block for searching error positions are connected to the second inputs of the block for sorting the positions of symbols,  the first outputs of the discrete Fourier transform unit are connected to the third inputs of the character position sorting unit,  the first outputs of the block for sorting character positions are connected to the second inputs of the Galois processor,  the second outputs of the block for sorting character positions are connected to the fifth inputs of the block for searching error positions,  moreover, the unit for sorting the positions of characters contains the first scheme for comparing codes,  first memory block of sorted items,  a second memory block of sorted items,  a third memory block of sorted items,  fourth block of memory of sorted items,  fifth block memory of sorted items,  first switch  second switch  third switch  fourth switch  fifth switch  Sixth switch  seventh switch  first counter  second counter  third counter  first decoder,  second decoder,  moreover, the first inputs of the first scheme for comparing codes are the first inputs of the block sorting character positions,  the second inputs of the first code comparison circuit are connected to the Thres constant bus,  the output of the first circuit comparing codes is connected to the second input of the first memory block of sorted items,  with the second input of the second memory block of sorted items,  with the second input of the third memory block of sorted positions,  with the second input of the fourth memory block of sorted positions and with the second input of the fifth memory block of sorted positions,  the first outputs of the first counter are connected to the first inputs of the first memory block of sorted items,  with the first inputs of the second memory block of sorted positions,  with the first inputs of the third block of memory of sorted items,  with the first inputs of the fourth memory block of sorted positions and with the first inputs of the fifth memory block of sorted positions,  the second output of the first counter is connected to the input of the second counter,  the outputs of the second counter are connected to the inputs of the first decoder,  the first output of the first decoder is connected to the third input of the first memory block of sorted items,  the second output of the first decoder is connected to the third input of the second memory block of the sorted positions,  the third output of the first decoder is connected to the third input of the third block of memory of sorted items,  the fourth output of the first decoder is connected to the third input of the fourth memory block of sorted items,  the fifth output of the first decoder is connected to the third input of the fifth memory block of sorted positions,  the outputs of the first memory block of sorted positions are connected to the second inputs of the first switch and the fourth inputs of the second switch,  the outputs of the second memory block of sorted positions are connected to the third inputs of the first switch and the fifth inputs of the second switch,  the outputs of the third memory block of sorted positions are connected to the fourth inputs of the first switch and the first inputs of the second switch,  the outputs of the fourth memory block of sorted positions are connected to the fifth inputs of the first switch and the second inputs of the second switch,  the outputs of the fifth memory block of sorted positions are connected to the first inputs of the first switch and the third inputs of the second switch,  the outputs of the third counter are connected to the sixth inputs of the first switch,  with the sixth inputs of the second switch and the inputs of the second decoder,  the first output of the second decoder is connected to the third input of the seventh switch,  the second output of the second decoder is connected to the third input of the third switch,  the third output of the second decoder is connected to the third input of the fourth switch,  the fourth output of the second decoder is connected to the third input of the fifth switch,  the fifth output of the second decoder is connected to the third input of the sixth switch,  the first entrances of the third,  the fourth  fifth  the sixth and seventh switches are the third inputs of the block sorting character positions,  second entrances of the third,  the fourth  fifth  the sixth and seventh switches are the second inputs of the block sorting character positions,  the outputs of the third switch are connected to the fourth inputs of the first memory block of sorted items,  the outputs of the fourth switch are connected to the fourth inputs of the second memory block of sorted positions,  the outputs of the fifth switch are connected to the fourth inputs of the third memory block of sorted positions,  the outputs of the sixth switch are connected to the fourth inputs of the fourth memory block of sorted positions,  the outputs of the seventh switch are connected to the fourth inputs of the fifth memory block of sorted positions,  the outputs of the first switch are the second outputs of the block for sorting character positions,  the outputs of the second switch are the first outputs of the block for sorting character positions,  moreover, the memory block of the sorted positions contains the first random access memory block,  a second random access memory unit,  the first logical element AND NOT,  the second logical element AND NOT,  fourth counter  fifth counter  eighth switch  Ninth switch  tenth switch  eleventh switch and subtractor,  moreover, the first inputs of the first random access memory block,  the first inputs of the second random access memory block are the first inputs of the sorted position memory block,  the first input of the first logical element AND NOT,  the first input of the second logical element AND NOT,  the third input of the eighth switch,  the third input of the ninth switch is the third input of the memory block of sorted items,  the second input of the first logical element AND NOT,  the second input of the second logical element AND is NOT the second input of the memory block of sorted positions,  the output of the first logical element AND is NOT connected to the second input of the first random access memory block and the input of the fourth counter,  the outputs of the fourth counter are connected to the first inputs of the eighth switch,  the second inputs of the eleventh switch and the first inputs of the subtractor,  the outputs of the eighth switch are connected to the third inputs of the first random access memory unit,  the outputs of the first random access memory unit are connected to the first inputs of the tenth switch,  the output of the second logical element AND is NOT connected to the second input of the second random access memory unit and the input of the fifth counter,  the outputs of the fifth counter are connected to the first inputs of the ninth switch,  the outputs of the ninth switch are connected to the third inputs of the second random access memory unit,  the outputs of the second random access memory unit are connected to the second inputs of the tenth switch,  the second inputs of the subtractor and the second inputs of the eighth switch are the fourth inputs of the memory block of sorted positions,  and the senior bit of the fourth inputs of the memory block of sorted items is connected to the third input of the eleventh switch,  the first outputs of the subtractor are connected to the second inputs of the ninth switch,  the second output of the subtractor is connected to the third input of the tenth switch,  the outputs of the tenth switch are connected to the first inputs of the eleventh switch,  the outputs of the eleventh switch are the outputs of the memory block sorted items,  moreover, the unit for finding error positions contains the first unit for calculating residuals,  the second block calculating the residuals,  first block of residual counting,  second block for calculating residuals,  twelfth switch  first register latch,  coefficient memory block,  first local control unit  moreover, the first inputs of the first local control device are the fourth inputs of the block search for error positions,  the second inputs of the first local control device and the first inputs of the coefficient memory block are the fifth inputs of the error position search block,  the third inputs of the unit for searching for error positions are the least significant bits of the second inputs of the coefficient memory block,  the first inputs of the block for searching error positions are the middle bits of the second inputs of the coefficient memory block,  the second input of the error position search block is the highest bit of the second inputs of the coefficient memory block,  the least significant bits of the first outputs of the coefficient memory block are connected to the first inputs of the first residual computing block and to the first inputs of the second residual computing block,  the middle bits of the first outputs of the coefficient memory block are connected to the third inputs of the first residual calculation block and to the third inputs of the second residual calculation block,  the senior bit of the first outputs of the coefficient memory block is connected to the fifth input of the first residual computing unit and to the fifth input of the second residual computing unit,  the least significant bits of the second outputs of the coefficient memory block are connected to the second inputs of the first residual computing unit and to the second inputs of the second residual computing unit,  the middle bits of the second outputs of the coefficient memory block are connected to the fourth inputs of the first residual calculation block and to the fourth inputs of the second residual calculation block,  the senior bit of the second outputs of the coefficient memory block is connected to the sixth input of the first residual computing unit and to the sixth input of the second residual computing unit,  the first outputs of the first block calculating the residuals are connected to the sixth inputs of the twelfth switch,  the second outputs of the first block computing the residuals are connected to the fifth inputs of the twelfth switch,  the third output of the first residual calculation unit is connected to the fourth input of the first residual calculation unit,  the fourth outputs of the first residual calculation unit are connected to the third inputs of the first residual calculation unit,  the fifth output of the first residual calculation unit is connected to the third input of the first local control device,  the first output of the first residual counting unit is connected to the fifth input of the first local control device,  the second outputs of the first block counting residuals connected to the fourth inputs of the twelfth switch,  the first outputs of the second residual calculation unit are connected to the first inputs of the twelfth switch,  the second outputs of the second block calculating the residuals are connected to the second inputs of the twelfth switch,  the fifth output of the second residual calculation unit is connected to the fourth input of the first local control device,  the fourth outputs of the second residual calculation unit are connected to the third inputs of the second residual calculation unit,  the third output of the second residual calculation unit is connected to the fourth input of the second residual calculation unit,  the second outputs of the second block counting residuals connected to the third inputs of the twelfth switch,  the first output of the second residual counting unit is connected to the sixth input of the first local control device,  the third output of the first local control device is connected to the seventh input of the first residual calculation unit,  the fourth output of the first local control device is connected to the eighth input of the first residual calculation unit,  the fifth output of the first local control device is connected to the ninth input of the first residual computing unit,  the sixth outputs of the first local control device are connected to the fourth inputs of the coefficient memory unit,  the seventh outputs of the first local control device are connected to the third inputs of the coefficient memory unit,  the eighth outputs of the first local control device are connected to the second inputs of the first residual counting unit,  the ninth output of the first local control device is connected to the first input of the first residual counting unit,  the tenth output of the first local control device is connected to the fifth input of the second residual counting unit,  the eleventh output of the first local control device is connected to the fourth input of the first register-latch,  the twelfth outputs of the first local control device are connected to the seventh inputs of the twelfth switch,  the thirteenth output of the first local control device is connected to the fifth input of the second residual counting unit,  the fourteenth output of the first local control device is connected to the first input of the second residual counting unit,  the fifteenth outputs of the first local control device are connected to the second inputs of the second residual counting unit,  the sixteenth output of the first local control device is connected to the ninth input of the second residual calculation unit, the seventeenth output of the first local control device is connected to the eighth input of the second residual calculation unit,  the eighteenth output of the first local control device is connected to the seventh input of the second residual calculation unit,  the first outputs of the first local control device are the fifth outputs of the error position search unit,  the second outputs of the first local control device are the first outputs of the error position search unit,  the first outputs of the twelfth switch are connected to the first inputs of the first register-latch,  the second outputs of the twelfth switch are connected to the second inputs of the first register-latch,  the third outputs of the twelfth switch are connected to the third inputs of the first register-latch,  the second outputs of the first register-latch connected to the tenth inputs of the first block calculating residuals,  the tenth inputs of the second block calculating the residuals and are the second outputs of the block searching for error positions,  the first outputs of the first latch register are the third outputs of the error position search unit,  the third outputs of the first latch register are the fourth outputs of the error position search unit,  wherein the residual calculation unit contains the thirteenth,  fourteenth and fifteenth switches,  second latch register,  third latch register,  the second adder of the Galois field elements,  the third adder of the Galois field elements,  the first inverter of the Galois field elements,  the first multiplier of the elements of the Galois field,  a second code comparison scheme,  the first selector of the zero elements of the Galois field,  the first logical element And,  the second logical element And,  logical element OR NOT  D trigger  moreover, the first inputs of the thirteenth switch are the first inputs of the block computing residuals,  the second inputs of the thirteenth switch are the second inputs of the block calculating residuals,  the first inputs of the fourteenth switch are the third inputs of the residual calculation unit,  the second inputs of the fourteenth switch are the fourth inputs of the block calculating residuals,  the first input of the fifteenth switch is the fifth input of the residual calculation unit,  the second input of the fifteenth switch is the sixth input of the residual calculation unit,  the third input of the thirteenth switch,  the third input of the fourteenth switch,  the third input of the fifteenth switch is the seventh input of the residual calculation unit,  the outputs of the thirteenth switch are connected to the first inputs of the second register-latch and the second inputs of the second adder of the Galois field elements,  the second input of the second register-latch,  the second input of the third register-latch,  the second input of the D-flip-flop is the eighth input of the residual calculation unit,  the outputs of the second register-latch are connected to the first inputs of the second adder of the Galois field elements and are the second outputs of the residual calculation unit,  the outputs of the second adder of the elements of the Galois field are connected to the inputs of the first inverter of the elements of the Galois field,  the outputs of the first inverter of the elements of the Galois field are connected to the first inputs of the first multiplier of the elements of the Galois field,  the outputs of the first multiplier of the Galois field elements are connected to the second inputs of the second code comparison circuit and are the fourth outputs of the residual calculation unit,  the first inputs of the second code comparison circuit are the tenth inputs of the residual computing unit,  the output of the second code comparison circuit is connected to the first input of the first logical element AND,  the output of the first logical element And is the fifth output of the block calculating the residuals,  the outputs of the fourteenth switch are connected to the first inputs of the third register-latch and the second inputs of the third adder of the Galois field elements,  the outputs of the third register-latch are connected to the first inputs of the third adder of the Galois field elements and are the first outputs of the residual calculation unit,  the outputs of the third adder of the elements of the Galois field are connected to the inputs of the first selector of the zero element of the Galois field and the second inputs of the multiplier of the elements of the Galois field,  the output of the first selector of the zero element of the Galois field is connected to the first input of the second logical element And,  the second input of the second logical element And is the ninth input of the block calculating the residuals,  the output of the second logical element AND is connected to the first input of the logical element OR NOT  the output of the fifteenth switch is connected to the second input of the OR-NOT logical element and the first input of the D-trigger,  the output of the D-trigger is connected to the third input of the logic element OR-NOT,  the output of the OR gate is NOT connected to the second input of the first logical gate AND is the third output of the block for calculating residuals,  wherein the residual counting unit comprises a first valve block,  third random access memory block,  increment scheme  third code comparison scheme,  sixteenth switch  fourth latch register,  the third logical element And,  fourth logical element AND,  moreover, the second input of the first block of gates and the third input of the sixteenth switch are the first input of the block counting residuals,  the outputs of the first block of gates are connected to the first inputs of the third random access memory block,  the outputs of the third random access memory block are connected to the first inputs of the increment circuit,  the outputs of the increment circuit are connected to the first inputs of the first valve block and the first inputs of the third code comparison circuit,  the second inputs of the third code comparison circuit are connected to the constant bus 't',  the output of the third code comparison circuit is connected to the first input of the third logical element AND,  the output of the third element is logical AND is the first output of the block for calculating residuals,  the first inputs of the sixteenth switch are the second inputs of the block counting residuals,  the outputs of the sixteenth switch are connected to the second inputs of the third random access memory block,  the inputs of the fourth register-latch are the third inputs of the block counting residuals,  the outputs of the fourth register-latch are connected to the second inputs of the sixteenth switch and are the second outputs of the block counting residuals,  the first input of the fourth logical element AND is the fourth input of the block for calculating residuals,  the second input of the fourth logical element AND is the fifth input of the block for calculating residuals,  the output of the fourth logical element AND is connected to the second input of the increment circuit and the second input of the third logical element I.

The introduction to the device of the block for sorting the positions of characters allows you to organize in the block search for positions of errors the search for positions of erroneous characters, controlled by the reliability of the characters of the code word, thereby ensuring a quick finding of error positions

The essence of the invention lies in the fact that in the process of searching for erroneous characters beyond the half of the minimum code distance, information about the reliability of the symbols received from the channel is introduced. For this, a table of permutations of the positions of the symbols of the codeword is used, obtained as a result of sorting the symbols by reliability.

For each codeword, a permutation table is formed by a block for sorting the positions of characters in which it is stored for the required time. This table is used to generate memory addresses when recording the results of a discrete Fourier transform block into a block for finding error positions of weight t + 1. The sequential reading of data from the memory in the block for searching for error positions generates a data stream ordered in accordance with the reliability of the codeword symbols. As a result, it is enough to process a small part of this stream to find the positions of erroneous characters. This greatly speeds up the operation of the inventive decoding device.

Figure 1 shows the functional diagram of the proposed device for decoding a PC code. Figure 2 shows a functional block diagram of the sorting of positions of characters; in the following figure 3 is a functional diagram of one of its main blocks: a memory block of sorted positions. Figure 4 shows the functional block diagram of the search for error positions, in the following figures 5-6 - functional diagrams of its main blocks: block calculating residuals (figure 5), block counting residuals (figure 6). In Fig.7 shows a functional diagram of a unit of discrete Fourier transform, in the following Fig.8 is a functional diagram of one of its main blocks: module of a discrete Fourier transform of the polynomial Λ ^(2t) (x). Figure 9 shows a timing diagram of the processing of code words by the proposed decoding device of the PC code. Figure 10 shows a graph with the results of studies of the performance of the inventive device in the channel with additive white Gaussian noise (AWGN) and BPSK modulation.

In the description of the device and in the drawings, the following notation is used:

BVS - block for calculating syndromes;

ACAS - block for sorting character positions;

BDPF - block of discrete Fourier transform;

BPPO - block for finding error positions;

BVZO - block for calculating error values;

BPOP - memory block of sorted items;

Ct2 is a binary counter;

DC - decoder;

Mux - multiplexer (switch);

RAM - random access memory;

Sub - subtractor;

MUU - local control device;

Inv - inverter in the final field;

Rg is the register;

BV - valve block;

BVN - block for calculating residuals;

BPN - block for calculating residuals;

BOD - block memory coefficients;

m is the bit depth of the element of the extended Galois field GF (2 ^m );

n is the number of characters in the code word of the PC code;

k is the number of information symbols in the codeword;

d is the minimum code distance of the PC code, d = r + 1;

;t - the number of guaranteed correctable errors in the codeword

;

α is a primitive element of the Galois field GF (2 ^m );

r (x) = r _n-1 x ^n-1 + r _n-2 x ^n-2 + ... + r ₁ x + r ₀ is the polynomial of the codeword received from the channel;

c (x) = c _n-1 x ^n-1 + c _n-2 x ^n-2 + ... + c ₁ x + c ₀ - polynomial of the corrected codeword;

S (x) is the polynomial of the syndrome;

Λ ^(2t) (x) - polynomial of error locators after 2t iterations of the Berlekamp-Messi algorithm;

B ^(2t) (x) is the auxiliary polynomial after 2t iterations of the Berlekamp-Messi algorithm;

L _2t is the formal degree of the polynomial of error locators Λ ^(2t) (x);

Λ ^{(2t + 2)} (x) is the polynomial of error locators obtained by analytic continuation of the Berlekamp-Messi algorithm for another 2 iterations;

Δ _{2t + 1} and Δ _{2t + 2} are the residuals of the analytic continuation of the Berlekamp-Messi algorithm at 2 iterations;

Λ '(x) is the formal derivative of the polynomial of error locators;

Ω (x) is the polynomial of error values;

{RE} - the set of error positions in the codeword.

The PC code decoding device (FIG. 1) contains: a data buffer 100, a syndrome calculation unit 200, a Galois processor 300, a discrete Fourier transform unit 400, a block for finding error positions of weight t + 1 500, a block for sorting symbol positions 600, a calculation block error values 700, the first adder of the Galois field elements 800.

At the input of the buffer data memory 100, the input of the block for computing syndromes 200, the symbols r _{i of the} codeword received from the channel (signals DIn) are received. The outputs of the data buffer 100 are connected to the first inputs of the first adder of the Galois field elements 800. The outputs of the syndrome calculation unit 200 are connected to the first inputs of the Galois processor 300. The first outputs of the Galois processor 300 (Control signals) are connected to the first inputs of the discrete Fourier transform 400. Second outputs the Galois processor 300 (Λ ^(2t) (x)) is connected to the second inputs of the discrete Fourier transform 400. The third outputs of the Galois processor 300 (B ^(2t) (x)) are connected to the third inputs of the discrete Fourier transform 400. Fourth the outputs of the Galois processor 300 (Control signals) are connected to the fourth inputs of the error position search block 500. The fifth outputs of the Galois processor 300 (Ω (x)) are connected to the first inputs of the error value calculation unit 700. Sixth outputs of the Galois processor 300 (Λ '(x) ) are connected to the second inputs of the error value calculation unit 700. The seventh outputs of the Galois processor 300 ({PE}) are connected to the third inputs of the error value calculation unit 700.

The second outputs of the discrete Fourier transform 400 (State signals) are connected to the third inputs of the Galois processor 300. The third outputs of the discrete Fourier transform 400 ({PE}) are connected to the fourth inputs of the Galois 300 processor. Fourth outputs of the discrete Fourier transform 400 (C _i | D _i) connected to the first inputs of the block search position error 500. The fifth output of the discrete Fourier transform unit 400 (Mskl) connected to the second input of the search position error block 500. The six outputs of the discrete Fourier transform 400 (a _i) connected third inputs block 500 positions troubleshooting.

The first outputs of the error position search unit 500 (State signals) are connected to the fifth inputs of the Galois 300 processor. The second outputs of the error position search unit 500 (Δ) are connected to the sixth inputs of the Galois 300 processor. The third outputs of the error position search unit 500 (A _i1 ) are connected to the seventh inputs of the Galois processor 300. The fourth outputs of the error position search unit 500 (C _i1 | D _i1 ) are connected to the eighth inputs of the Galois processor 300.

The first inputs of the block for sorting symbol positions 600 (SoftIn signals) are inputs of estimates of the reliability of the data symbols of the Reed-Solomon code decoding device. The reliability score is represented by an unsigned fixed-point binary number. A larger value corresponds to a greater reliability of the codeword characters.

The fifth outputs of the error position search block 500 ({PE '}) are connected to the second inputs of the symbol position sorting block 600. The first outputs of the discrete Fourier transform 400 (AddrR1) are connected to the third inputs of the symbol position sorting block 600. The first outputs of the symbol position sorting block 600 ({PE}) are connected to the second inputs of the Galois processor 300. The second outputs of the character position sorting unit 600 (AddrW) are connected to the fifth inputs of the error position search unit 500.

The outputs of the error value calculation unit 700 are connected to the second inputs of the first adder of the Galois field elements 800. The outputs of the first adder of the Galois field elements 800 are data outputs of the Reed-Solomon code decoding device (DOut signals).

The character position sorting unit 600 (FIG. 2) contains a first code comparison scheme 610, a first memory block of sorted positions 620.1, a second memory block of sorted positions 620.2, a third memory block of sorted positions 620.3, a fourth memory block of sorted positions 620.4, a fifth memory block of sorted positions 620.5, first switch 630.1, second switch 630.2, third switch 670.1, fourth switch 670.2, fifth switch 670.3, sixth switch 670.4, seventh switch 670.5, first counter 640, second counter 650.1, third counter 650.2, lane 660.1 th decoder, the second decoder 660.2.

первого блока памяти отсортированных позиций 620.1. Второй выход первого дешифратора 660.1 соединен с третьим входом

второго блока памяти отсортированных позиций 620.2. Третий выход первого дешифратора 660.1 соединен с третьим входом

третьего блока памяти отсортированных позиций 620.3. Четвертый выход первого дешифратора 660.1 соединен с третьим входом

четвертого блока памяти отсортированных позиций 620.4. Пятый выход первого дешифратора 660.1 соединен с третьим входом

пятого блока памяти отсортированных позиций 620.5. Выходы первого блока памяти отсортированных позиций 620.1 соединены со вторыми входами первого коммутатора 630.1 и четвертыми входами второго коммутатора 630.2. Выходы второго блока памяти отсортированных позиций 620.2 соединены с третьими входами первого коммутатора 630.1 и пятыми входами второго коммутатора 630.2. Выходы третьего блока памяти отсортированных позиций 620.3 соединены с четвертыми входами первого коммутатора 630.1 и первыми входами второго коммутатора 630.2. Выходы четвертого блока памяти отсортированных позиций 620.4 соединены с пятыми входами первого коммутатора 630.1 и вторыми входами второго коммутатора 630.2. Выходы пятого блока памяти отсортированных позиций 620.5 соединены с первыми входами первого коммутатора 630.1 и третьими входами второго коммутатора 630.2. Выходы третьего счетчика 650.2 соединены с шестыми входами первого коммутатора 630.1, с шестыми входами второго коммутатора 630.2 и входами второго дешифратора 660.2. Первый выход второго дешифратора 660.2 соединен с третьим входом седьмого коммутатора 670.5, второй выход второго дешифратора 660.2 соединен с третьим входом третьего коммутатора 670.1. Третий выход второго дешифратора 660.2 соединен с третьим входом четвертого коммутатора 670.2. Четвертый выход второго дешифратора 660.2 соединен с третьим входом пятого коммутатора 670.3. Пятый выход второго дешифратора 660.2 соединен с третьим входом шестого коммутатора 670.4. Первые входы третьего 670.1, четвертого 670.2, пятого 670.3, шестого 670.4 и седьмого 670.5 коммутаторов (сигналы AdR1) являются третьими входами блока сортировки позиций символов 600. Вторые входы третьего 670.1, четвертого 670.2, пятого 670.3, шестого 670.4 и седьмого 670.5 коммутаторов (сигналы AdR2) являются вторыми входами блока сортировки позиций символов 600. Выходы третьего коммутатора 670.1 соединены с четвертыми входами Adr первого блока памяти отсортированных позиций 620.1. Выходы четвертого коммутатора 670.2 соединены с четвертыми входами Adr второго блока памяти отсортированных позиций 620.2. Выходы пятого коммутатора 670.3 соединены с четвертыми входами Adr третьего блока памяти отсортированных позиций 620.3. Выходы шестого коммутатора 670.4 соединены с четвертыми входами Adr четвертого блока памяти отсортированных позиций 620.4. Выходы седьмого коммутатора 670.5 соединены с четвертыми входами Adr пятого блока памяти отсортированных позиций 620.5. Выходы первого коммутатора 630.1 (сигналы DOR1) являются вторыми выходами блока сортировки позиций символов. Выходы второго коммутатора 630.2 (сигналы DOR2) являются первыми выходами блока сортировки позиций символов.The first inputs of the first code comparison circuit 610 (SoftIn signals) are the first inputs of the character position sorting unit, and the second inputs of the first code comparison circuit are connected to the Thres constant bus. The output of the first code comparison circuit 610 is connected to the second input of the first memory block of sorted positions 620.1, to the second input of the second memory block of sorted positions 620.2, to the second input of the third memory block of sorted positions 620.3, to the second input of the fourth memory block of sorted positions 620.4 and to the second input the fifth memory block of sorted positions 620.5. The first outputs of the first counter 640 are connected with the first inputs of the first memory block of sorted positions 620.1, with the first inputs of the second memory block of sorted positions 620.2, with the first inputs of the third memory block of sorted positions 620.3, with the first inputs of the fourth memory block of sorted positions 620.4 and with the first inputs of the fifth block memory sorted items 620.5. The second output of the first counter 640 is connected to the input of the second counter 650.1. The outputs of the second counter 650.1 are connected to the inputs of the first decoder 660.1. The first output of the first decoder 660.1 is connected to the third input

the first memory block of sorted positions 620.1. The second output of the first decoder 660.1 is connected to the third input

the second memory block of sorted positions 620.2. The third output of the first decoder 660.1 is connected to the third input

the third memory block of sorted positions 620.3. The fourth output of the first decoder 660.1 is connected to the third input

fourth block of memory of sorted positions 620.4. The fifth output of the first decoder 660.1 is connected to the third input

the fifth memory block of sorted positions 620.5. The outputs of the first memory block of sorted positions 620.1 are connected to the second inputs of the first switch 630.1 and the fourth inputs of the second switch 630.2. The outputs of the second memory block of sorted positions 620.2 are connected to the third inputs of the first switch 630.1 and the fifth inputs of the second switch 630.2. The outputs of the third memory block of sorted positions 620.3 are connected to the fourth inputs of the first switch 630.1 and the first inputs of the second switch 630.2. The outputs of the fourth memory block of sorted positions 620.4 are connected to the fifth inputs of the first switch 630.1 and the second inputs of the second switch 630.2. The outputs of the fifth memory block of sorted positions 620.5 are connected to the first inputs of the first switch 630.1 and the third inputs of the second switch 630.2. The outputs of the third counter 650.2 are connected to the sixth inputs of the first switch 630.1, with the sixth inputs of the second switch 630.2 and the inputs of the second decoder 660.2. The first output of the second decoder 660.2 is connected to the third input of the seventh switch 670.5, the second output of the second decoder 660.2 is connected to the third input of the third switch 670.1. The third output of the second decoder 660.2 is connected to the third input of the fourth switch 670.2. The fourth output of the second decoder 660.2 is connected to the third input of the fifth switch 670.3. The fifth output of the second decoder 660.2 is connected to the third input of the sixth switch 670.4. The first inputs of the third 670.1, fourth 670.2, fifth 670.3, sixth 670.4 and seventh 670.5 switches (AdR1 signals) are the third inputs of the character position sorting block 600. The second inputs of the third 670.1, fourth 670.2, fifth 670.3, sixth 670.4 and seventh 670.5 switches (AdR2 signals ) are the second inputs of the block for sorting positions of symbols 600. The outputs of the third switch 670.1 are connected to the fourth inputs Adr of the first memory block of the sorted positions 620.1. The outputs of the fourth switch 670.2 are connected to the fourth inputs Adr of the second memory block of sorted positions 620.2. The outputs of the fifth switch 670.3 are connected to the fourth inputs Adr of the third memory block of sorted positions 620.3. The outputs of the sixth switch 670.4 are connected to the fourth inputs Adr of the fourth memory block of sorted positions 620.4. The outputs of the seventh switch 670.5 are connected to the fourth inputs Adr of the fifth memory block of sorted positions 620.5. The outputs of the first switch 630.1 (DOR1 signals) are the second outputs of the character position sorting unit. The outputs of the second switch 630.2 (DOR2 signals) are the first outputs of the character position sorting unit.

All counters used in block 600 are binary: counter 640 operates with a conversion factor n, counters 650 operate with a conversion factor of 5.

Decoders 660 have inverse outputs. At the i-outputs of the decoders (i = 1, ..., 5), the values of the logical zero (active level) appear when the values “i-1” are sent to their inputs.

All switches in the block are 600-m-bit. The outputs of the switches 630 are supplied with the values of their “i-x” inputs (i = 1, ..., 5), if the values “i-1” are supplied to their sixth inputs. The outputs of the switches 670 are supplied with the values of their first inputs, if the values of the logical zero are fed to their third inputs.

The sorted position memory block (Fig. 3) contains a first random access memory block 621.1, a second random access memory block 621.2, a first NAND gate 622, a second NAND gate 627, a fourth counter 623.1, a fifth counter 623.2, the eighth switch 624.1, the ninth switch 624.2, the tenth switch 625.1, the eleventh switch 625.2 and the subtractor 626.

блока памяти отсортированных позиций. Второй вход первого логического элемента И-НЕ 622, второй вход второго логического элемента И-НЕ 627 являются вторым входом S блока памяти отсортированных позиций. Выход первого логического элемента И-НЕ 622 соединен со вторым входом

первого блока памяти с произвольным доступом 621.1 и входом четвертого счетчика 623.1. Выходы четвертого счетчика 623.1 соединены с первыми входами восьмого коммутатора 624.1, вторыми входами одиннадцатого коммутатора 625.2 и первыми входами вычитателя 626. Выходы восьмого коммутатора 624.1 соединены с третьими входами А первого блока памяти с произвольным доступом 621.1. Выходы первого блока памяти с произвольным доступом 621.1 соединены с первыми входами десятого коммутатора 625.1. Выход второго логического элемента И-НЕ 627 соединен со вторым входом

второго блока памяти с произвольным доступом 621.2 и входом пятого счетчика 623.2. Выходы пятого счетчика 623.2 соединены с первыми входами девятого коммутатора 624.2. Выходы девятого коммутатора 624.2 соединены с третьими входами А второго блока памяти с произвольным доступом 621.2. Выходы второго блока памяти с произвольным доступом 621.2 соединены со вторыми входами десятого коммутатора 625.1. Вторые входы вычитателя 626 и вторые входы восьмого коммутатора 624.1 (сигналы Adr) являются четвертыми входами блока памяти отсортированных позиций, а старший разряд четвертых входов блока памяти отсортированных позиций соединен с третьим входом одиннадцатого коммутатора 625.2. Первые выходы вычитателя 626 соединены со вторыми входами девятого коммутатора 624.2. Второй выход вычитателя 626 соединен с третьим входом десятого коммутатора 625.1. Выходы десятого коммутатора 625.1 соединены с первыми входами одиннадцатого коммутатора 625.2. Выходы одиннадцатого коммутатора 625.2 являются выходами блока памяти отсортированных позиций.The first inputs of the first random access memory unit 621.1, the first inputs of the second random access memory unit 621.2 are the first inputs DI of the sorted position memory unit. The first input of the first gate AND-622, the first input of the second gate AND 627, the third input of the eighth switch 624.1, the third input of the ninth switch 624.2 are the third input

block memory of sorted items. The second input of the first logical element NAND 622, the second input of the second logical element NAND 627 are the second input S of the memory block of sorted positions. The output of the first logical element AND-622 is connected to the second input

the first random access memory block 621.1 and the input of the fourth counter 623.1. The outputs of the fourth counter 623.1 are connected to the first inputs of the eighth switch 624.1, the second inputs of the eleventh switch 625.2 and the first inputs of the subtractor 626. The outputs of the eighth switch 624.1 are connected to the third inputs A of the first random access memory block 621.1. The outputs of the first random access memory block 621.1 are connected to the first inputs of the tenth switch 625.1. The output of the second logical element AND-627 is connected to the second input

the second random access memory block 621.2 and the input of the fifth counter 623.2. The outputs of the fifth counter 623.2 are connected to the first inputs of the ninth switch 624.2. The outputs of the ninth switch 624.2 are connected to the third inputs A of the second random access memory block 621.2. The outputs of the second random access memory block 621.2 are connected to the second inputs of the tenth switch 625.1. The second inputs of the subtractor 626 and the second inputs of the eighth switch 624.1 (Adr signals) are the fourth inputs of the sorted position memory block, and the highest bit of the fourth inputs of the sorted position memory block is connected to the third input of the eleventh switch 625.2. The first outputs of the subtractor 626 are connected to the second inputs of the ninth switch 624.2. The second output of the subtractor 626 is connected to the third input of the tenth switch 625.1. The outputs of the tenth switch 625.1 are connected to the first inputs of the eleventh switch 625.2. The outputs of the eleventh switch 625.2 are the outputs of the memory block sorted items.

621 random access memory blocks contain n log ₂ n-bit cells. Counters 623 are binary log ₂ n-bit. Switches 624 and 625 have the same bit depth. They carry out switching from two directions, passing the values of their first inputs to the outputs, when a logical zero value is supplied to their third inputs.

Subtractor 626 subtracts the contents of counter 623.1 from the value supplied to the fourth inputs of block 620 (Adr signals). At the second output of the subtractor, a loan signal is generated.

The error position search unit (Fig. 4) contains a first residual calculation unit 510.1, a second residual calculation unit 510.2, a first residual calculation unit 520.1, a second residual calculation unit 520.2, a twelfth switch 530, a first latch register 540, a coefficient memory 550, a first local control device 560.

The first inputs of the first local control device 560 (Control signals) are the fourth inputs of the error position search unit 500. The second inputs of the first local control device 560 and the first inputs of the coefficient memory 550 (AddrW signals) are the fifth inputs of the error position search unit. The third inputs of the error position search block 500 (signals A _i ) are the lower bits of the second inputs of the coefficient memory 550. The first inputs of the error position search block 500 are the middle bits of the second inputs of the coefficient memory 550 (C _i | D _i ). The second input of the error position search block 500 (Msk1) is the highest bit of the second inputs of the coefficient memory block 550 (Mask1). The least significant bits of the first outputs D _R1 of the coefficient memory block 550 (signals A ′ _i ) are connected to the first inputs of the first residual calculation block 510.1 and to the first inputs of the second residual calculation block 510.2. The middle bits of the first outputs D _R1 of the coefficient memory 550 (C ′ _i | D ′ _i ) are connected to the third inputs of the first residual calculation block 510.1 and to the third inputs of the second residual calculation block 510.2. The high-order bit of the first outputs D _R1 of the coefficient memory unit 550 (Msk1 ') is connected to the fifth input of the first residual calculation block 510.1 and to the fifth input of the second residual calculation block 510.2. The low-order bits of the second outputs D _R2 of the coefficient memory unit 550 (A '' _i ) are connected to the second inputs of the first residual calculation block 510.1 and to the second inputs of the second residual calculation block 510.2. The middle bits of the second outputs D _R2 of the coefficient memory 550 (C '' _i | D '' _i ) are connected to the fourth inputs of the first residual calculation block 510.1 and to the fourth inputs of the second residual calculation block 510.2. The senior bit of the second outputs D _R2 of the coefficient memory block 550 (Msk1 '') is connected to the sixth input of the first residual calculation block 510.1 and to the sixth input of the second residual calculation block 510.2.

The first outputs of the first residual calculation block 510.1 (signals (C _i1 | D _i1 ) ₁ ) are connected to the sixth inputs of the twelfth switch 530. The second outputs of the first residual calculation block 510.1 ((A _i1 ) ₁ ) are connected to the fifth inputs of the twelfth switch 530. Third output the first block of calculating residuals 510.1 (¬Msk2 ₁ ) is connected to the fourth input of the first block of calculating residuals 520.1. The fourth outputs of the first block of calculation of residuals 510.1 (Δ ' ₁ ) are connected to the third inputs of the first block of calculation of residuals 520.1. The fifth output of the first residual calculation unit 510.1 (SX _i1 ) is connected to the third input of the local control device 560. The first output of the first residual calculation unit 520.1 (St ₁ ) is connected to the fifth input of the first local residual control device 560. The second outputs of the first residual calculation unit 520.1 (Δ '' ₁ ) connected to the fourth inputs of the twelfth switch 530.

The first outputs of the second residual calculation block 510.1 (signals (C _i1 | D _i1 ) ₂ ) are connected to the first inputs of the twelfth switch 530. The second outputs of the second residual calculation block 510.2 ((A _i1 ) ₂ ) are connected to the second inputs of the twelfth switch 530. Fifth output the second residual computing unit 510.2 (SX _i2 ) is connected to the fourth input of the first local control device 560. The fourth outputs of the second residual computing unit 510.2 (Δ ' ₂ ) are connected to the third inputs of the second residual computing unit 520.2. The third output of the second residuals calculation unit 510.2 (¬Msk2 ₂ ) is connected to the fourth input of the second residuals calculation unit 520.2. The second outputs of the second residuals counting unit 520.2 (Δ '' ₂ ) are connected to the third inputs of the twelfth switch 530. The first output of the second residuals counting unit 520.2 (St ₂ ) is connected to the sixth input of the first local control device 560. The third output of the first local control device 560 ( CMx ₁ ) is connected to the seventh input of the first residual calculation unit 510.1. The fourth output of the first local control device 560 (Ld ₁ ) is connected to the eighth input of the first residual calculation unit 510.1. The fifth output of the first local control device 560 (EM ₁ ) is connected to the ninth input of the first residual calculation unit 510.1. The sixth outputs of the first local control device 560 (AR1) are connected to the fourth inputs A _R1 of the coefficient memory 550. The seventh outputs of the first local control device 560 (AR2) are connected to the third inputs A _R2 of the coefficient memory 550. The eighth outputs of the first local control device 560 ( AI ₁ ) connected to the second inputs of the first block counting residuals 520.1. The ninth output of the first local control device 560 (I ₁ ) is connected to the first input of the first residual counting unit 520.1. The tenth output of the local first control device 560 (E ₁ ) is connected to the fifth input of the first residual counting unit 520.1. The eleventh output of the first local control device 560 (L) is connected to the fourth input of the first register-latch 540. The twelfth outputs of the first local control device 560 (CMx) are connected to the seventh inputs of the twelfth switch 530. The thirteenth output of the first local control device 560 (E ₂ ) is connected with the fifth input of the second residual counting unit 520.2. The fourteenth output of the first local control device 560 (I ₂ ) is connected to the first input of the second residual counting unit 520.2. The fifteenth outputs of the first local control device 560 (AI ₂ ) are connected to the second inputs of the second residual counting unit 520.2. The sixteenth output of the first local control device 560 (EM ₂ ) is connected to the ninth input of the second residual calculation unit 510.2. The seventeenth output of the first local control device 560 (Ld ₂ ) is connected to the eighth input of the second residual calculation unit 510.2. The eighteenth output of the first local control device 560 (CMx ₂ ) is connected to the seventh input of the second residual calculation unit 510.2. The first outputs of the first local control device 560 ({PE '}) are the fifth outputs of the error position search unit 500. The second outputs of the first local control device 560 (State) are the first outputs of the error position search unit 500. The first outputs of the twelfth switch 530 are connected to the first inputs the first register-latch 540. The second outputs of the twelfth switch 530 are connected to the second inputs of the first register-latch 540. The third outputs of the twelfth switch 530 are connected to the third inputs of the first register-latch 540. The second Exit first latch 540 (Δ) are connected to the inputs of the first tenth calculation unit residuals 510.1, decimals inputs of the second calculation unit residuals are 510.2 and second output unit 500. The position error search first outputs of the first latch 540 (A _i1) are third outputs unit for finding error positions 500. The third outputs of the first register-latch 540 (C _i1 | D _i1 ) are the fourth outputs of the unit for searching for error positions 500.

Switch 530 is a three-section bi-directional. The first and sixth inputs of the switch are inputs of the first section, the second and fifth inputs are inputs of the second section, the third and fourth inputs are inputs of the third section.

The residual computing unit (FIG. 5) contains the thirteenth 511.1, fourteenth 511.2 and fifteenth switches 511.0, a second latch register 512.1, a third latch register 512.2, a second adder of Galois field elements 513.1, a third adder of Galois field elements 513.2, a first inverter of Galois field elements 514, the first Galois field element multiplier 515, the second code comparison circuit 516.1, the first Galois field zero element selector 516.2, the first logical element AND 517.2, the second logical element AND 517.1, the logical element OR-NOT 518, D-trigger 519.

The first inputs of the thirteenth switch 511.1 (signal A _i ^' ) are the first inputs of the residual calculation unit. The second inputs of the thirteenth switch 511.1 (A _i '') are the second inputs of the residual calculation unit. The first inputs of the fourteenth switch 511.2 (C ' _i (D' _i )) are the third inputs of the residual calculation unit. The second inputs of the fourteenth switch 511.2 (C '' _i (D '' _i )) are the fourth inputs of the residual calculation unit. The first input of the fifteenth switch 511.0 (Msk1 ') is the fifth input of the residual calculation unit. The second input of the fifteenth switch 511.0 (MSk1 '') is the sixth input of the residual calculation unit.

The third input of the thirteenth switch 511.1, the third input of the fourteenth switch 511.2, the third input of the fifteenth switch 511.0 are the seventh input of the residual computation unit, to which the signal Cmx is supplied. The outputs of the thirteenth switch 511.1 are connected to the first inputs of the second register-latch 512.1 and the second inputs of the second adder of the Galois field elements 513.1. The second input of the second register-latch 512.1, the second input of the third register-latch 512.2, the second input of the D-flip-flop 519 are the eighth input of the residual computation unit to which the signal Ld is supplied. The outputs of the second register-latch 512.1 (signals A _i1 ) are connected to the first inputs of the second adder of the Galois field elements 513.1 and are the second outputs of the residual calculation block. The outputs of the second adder of Galois field elements 513.1 are connected to the inputs of the first inverter of Galois field elements 514. The outputs of the first inverter of Galois field elements 514 are connected to the first inputs of the first Galois field element multiplier 515. The outputs of the first Galois field element multiplier 515 (signals Δ ') are connected to the second the inputs of the second circuit comparison codes 516.1 and are the fourth outputs of the block calculating the residuals. The first inputs of the second code comparison circuit 516.1 are the tenth inputs of the residual computation unit to which the signals Δ are supplied. The output of the second code comparison circuit 516.1 is connected to the first input of the first logical element AND 517.1. The output of the first logical element AND 517.1 (signal SX _i ) is the fifth output of the residual calculation unit. The outputs of the fourteenth switch 511.2 are connected to the first inputs of the third register-latch 512.2 and the second inputs of the third adder of the Galois field elements 513.3. The outputs of the third register-latch 512.2 (C _i1 | D _i1 ) are connected to the first inputs of the third adder of the Galois field elements 513.2 and are the first outputs of the residual calculation unit. The outputs of the third adder of Galois field elements 513.2 are connected to the inputs of the first Galois field element zero selector 516.2 and the second inputs of the first Galois field element multiplier 515. The output of the first Galois field element zero selector 516.2 is connected to the first input of the second AND gate 517.2. The second input of the second logical element AND 517.2 is the ninth input of the residual calculation block, to which the EM signal is supplied. The output of the second AND gate 517.2 is connected to the first input of the OR-NOT gate 518. The output of the fifteenth switch 511.0 is connected to the second input of the OR gate 518 and the first input of the D-trigger 519. The output of the D-trigger 519 is connected to the third input of the logic gate OR NOT 518. The output of the logic element OR NOT 518 (¬Msk2) is connected to the second input of the first logical element AND 517.1 and is the third output of the block for calculating residuals.

Latch registers 512 and D-flip-flop 519 receive information when the Ld signal is active, which is fed to their second inputs.

The residual counting unit (Fig. 6) contains a first block of gates 521, a third random access memory block 522, an increment scheme 523, a third code comparison circuit 524, a third AND gate 525, a sixteenth switch 526, a fourth latch register 527, a fourth logical element And 528.

The second input of the first gate block and the third input of the sixteenth switch are the first input of the residual counting block to which signal I. The outputs of the first gate block are connected to the first inputs DI of the third random access memory block 522. The outputs of the third random access memory block 522 are connected to the first inputs of the increment circuit 523. The outputs of the increment circuit 523 are connected to the first inputs of the first valve block 521 and the first inputs of the third code comparison circuit 524. The second inputs of the third code comparison circuit 524 connected to the 't' constant bus. The output of the third code comparison circuit 524 is connected to the first input of the third logical element And 525. The output of the third logical element And 525 is the first output of the residual counting block on which the signal St. The first inputs of the sixteenth switch 526 are the second inputs of the residual counting unit to which the AI signals are supplied. The outputs of the sixteenth switch 526 are connected to the second inputs A of the third random access memory block 522. The inputs of the fourth latch register 527 are the third inputs of the residual counting unit to which the signals Δ 'are supplied. The outputs of the fourth register-latch 527 (signals Δ '' _n ) are connected to the second inputs of the sixteenth switch 526 and are the second outputs of the residual counting unit. The first input of the fourth logical element AND 528 is the fourth input of the residual counting unit, to which the signal ¬Msk2 is supplied. The second input of the fourth AND gate 528 is the fifth input of the residual counting unit to which signal E. The output of the fourth AND gate 528 is connected to the second input of the increment circuit 523 and the second input of the third AND gate 525.

The valve block 521 transmits information from the first inputs to the outputs when a logical zero is supplied to its second input, otherwise zeros are formed at its outputs.

The discrete Fourier transform block (Fig. 7) contains a second local control device 410, a first discrete Fourier transform module of the polynomial Λ ^(2t) (x) 420.1, a second discrete Fourier transform module of the polynomial B ^(2t) (x) 420.2, seventeenth switch 430, the second inverter of the Galois field elements 440, the second multiplier of two elements of the Galois field 450, the eighteenth two-input switch 460, the multiplier by α 470, the fifth register-latch 480 operating along the front of the clock signal; the sixth binary counter of the position numbers of the received word 490 with the conversion factor n.

The first inputs of the second local control device 410 are the first inputs of the discrete Fourier transform 400, to which Control signals are supplied. The first outputs of the second local control device 400 are the second outputs of the discrete Fourier transform 400, to which State signals are output. The second outputs of the second local control device 410 are the third outputs of the discrete Fourier transform 400, to which signals {PE} are issued. The third outputs of the second local control device 410 are connected to the second inputs of the first discrete Fourier transform module 420.1 and to the second inputs of the second discrete Fourier transform module 420.2. The fourth output of the second local control device 410 is connected to the third input of the seventeenth switch 430 and to the third input of the eighteenth switch 460. The first inputs of the first discrete Fourier transform module 420.1 and the second discrete Fourier transform module 420.2 are the second and third inputs of the discrete Fourier transform 400 signals Λ (x), B (x) are given. The first outputs of the first discrete Fourier transform module 420.1 (signals Λ (α ^-1 )) are connected to the first inputs of the seventeenth switch 430. The second output of the first discrete Fourier transform module 420.1 (sel0) is connected to the third input of the second local control device 410 and the first input of the eighteenth switch 460. The first module outputs a second discrete Fourier transform 420.2 (C (α ^-1)) are connected to second inputs of the seventeenth switch 430. The second output of the second module of the Fourier discrete transform 420.2 (sel0) connected to the second the input of the eighteenth switch 460. The first outputs of the seventeenth switch 430 are connected to the inputs of the second inverter of the elements of the Galois field 440. The second outputs of the seventeenth switch are connected to the second inputs of the second multiplier of the elements of the Galois field 450. The outputs of the second inverter of the elements of the Galois field 440 are connected to the first inputs of the second multiplier of the field elements Galois 450. The outputs of the second multiplier of the Galois field elements are the fourth outputs of the discrete Fourier transform 400, to which signals (C _i | D _i ) are issued . The output of the eighteenth switch 460 is the fifth output of the discrete Fourier transform 400, to which the signal Msk1 is output. The outputs of the sixth binary counter 490 are connected to the second inputs of the second local control device 410 and are the first outputs of the discrete Fourier transform 400, to which AddrR1 signals are output. The outputs of the multiplier by α 470 are connected to the inputs of the fifth register-latch 480. The outputs of the fifth register-latch 480 are connected to the inputs of the multiplier by α 470 and are the sixth outputs of the discrete Fourier transform 400, to which signals A _i are output.

The seventeenth switch 430 is a crossover. When the signal at the third input is active, the switch operates in the cross-transmission mode: the values of its first inputs are fed to the second outputs, the values of its second inputs are fed to the first outputs. With an inactive signal at the third input, the switch operates in direct transmission mode.

The discrete Fourier transform module (Fig. 8) contains the second block of gates 421, sixth, seventh, eighth, ..., t + 7 latch registers operating along the front of the clock pulse, 422.0 - 422.t + 1, the fourth adder of Galois field elements t + 2 inputs 423, the second selector of the zero element of the Galois field 424, the first, second, ..., t + 1 multipliers by constant coefficients in the Galois field 425.1 - 425.t + 1, the first, second, ..., t + 1 blocks of logic elements OR 426.1-426.t + 1.

The first inputs of the second block of gates 421 are the first inputs of the discrete Fourier transform module, to which signals Λ (x) are supplied. The second input of the second block of valves 421 (enable signal) is connected to the loc_contr bus, which represents the second inputs of the BDPF 400. The outputs of the second block of valves 421 are connected to the first inputs of the sixth register-latch 422.0, the second inputs of the first, second, ..., t + 1 blocks of logic elements OR 426.1, ..., 426.t + 1. The second inputs of the sixth, seventh, eighth, ..., t + 7 latch registers are connected to the loc_contr bus (signals c ₀ ... c _{t + 1} ). The third inputs of the sixth, seventh, eighth, ..., t + 7 latch registers are connected to the loc_contr bus (clear signal). The outputs of the first, second, ..., t + 1 blocks of logic gates OR 426.1, ..., 426.t + 1 are connected to the first inputs of the seventh, eighth, ..., t + 7 latch registers 422.1, ..., 425.t + 1, respectively. The outputs of the sixth register-latch 422.0 are connected to the first inputs of the fourth adder of the Galois field elements 423. The outputs of the seventh, eighth, ..., t + 7 register-latches 422.1, ..., 425.t + 1 are connected respectively to the second, third, ..., t + 2 inputs of the fourth adder of the elements of the Galois field 423 and the inputs of the first, second, ..., t + 1 multipliers by constant coefficients in the Galois field 425.1, ..., 425.t + 1, respectively. The outputs of the first, second, ..., t + 1 constant factor multipliers in the Galois field 425.1 ... 425.t + 1 are connected to the first inputs of the first, second, ..., t + 1 logic elements blocks OR 426.1, ..., 426.t + 1 respectively. The outputs of the fourth adder of Galois field elements 423 are connected to the inputs of the second selector of the zero element of the Galois field 424 and are the first outputs of the discrete Fourier transform module, to which signals Λ (w) are output. The output of the second Galois field element zero selector 424 is the second output of the discrete Fourier transform module, to which the signal sel0 is output.

All communication lines connecting the blocks of FIGS. 1-8, through which data in the form of Galois field elements are transmitted, are m-bit.

All used triggers, registers and counters operate on the leading edge of the clock signal, which is not shown in Figs. 1-7, but is implied.

Adders of field elements, multipliers by constant coefficients and blocks for finding the inverse field element can be implemented in a known manner, in particular, adders can be implemented on m two-input EXCLUSIVE-OR elements (adders modulo 2), multipliers by constant coefficients can be implemented on multi-input Exclusive-OR elements, blocks for finding the inverse element can be implemented in a tabular manner.

The decoding procedure performed by the claimed device provides the correction of t + 1 errors in the PC code code with a minimum code distance d = 2t + 1 by analytically continuing the Berlekamp-Messi algorithm for two more iterations. This continuation gives:

where δ _k = 1 if Δ _k ≠ 0 and 2L _k-1 ≤k-1, or δ _k = 0 otherwise. L _k is the formal degree of the error locator polynomial Λ ^(k) (x), B ^(k) (x) is the auxiliary polynomial.

To each pair of unknown residuals Δ _{2 + t1} and Δ _{2t + 2} . corresponds to the polynomial Λ ^{(2t + 2)} (x). By definition, the polynomial of error locators Λ (x) vanishes when x takes values that are inverse to the locators of erroneous symbols. Of interest are such polynomials Λ ^{(2t + 2)} (x) that have degree t + 1 and have exactly t + 1 root in GF (q). The set of admissible roots of the polynomial Λ ^{(2t + 2)} (x) is {α ⁰ , α ^-1 , α ^-2 , ..., α ^{- (n-2)} , α ^{- (n-1)} } (α is a primitive element of the field GF (q)). Substituting this set into equation (1), we can obtain the following:

where Λ ^(2t) (α ^-i ) and B ^(2t) (α ^-i ) are the components of the discrete Fourier transform of the polynomials Λ ^(2t) (x) and B ^(2t) (x).

If the codeword contains a configuration of errors of weight t + 1 exactly t + 1 right-hand sides of the equations of system (2) for some value of the pair of residuals, Δ _{2t + 1} and Δ _{2t + 2} turn to 0. To determine the positions of these erroneous symbols, it is necessary to find the corresponding pair of residuals and fix the numbers i of the equations of system (2) with the right-hand sides vanishing.

Equating the left-hand sides of the equations of system (2) to zero, we can obtain the following system of equations from two unknowns Δ _{2t + 1} and Δ _{2t + 2} :

The subsets of exactly t + 1 joint equations of system (3) will correspond to the desired combinations of errors of weight t + 1, the values of the numbers of equations i will give the positions of errors in the codeword.

. Затем к первому уравнению последовательно присоединяются другие оставшиеся уравнения. Для всех таких пар уравнений также вычисляются возможные значения невязки

. Если среди всех полученных значений невязки есть t одинаковых, равных Δ_2t+1, это говорит о том, что зафиксированное уравнение с номером i входит в искомое подмножество уравнений (и определяет позицию первой ошибки). Значения j, соответствующие условию

, дадут позиции еще t ошибок. В процессе поиска перебираются все возможные значения i.These subsets can be found as follows [3, 4]. One of the equations of system (3) is fixed (we denote its number i). One of the remaining equations joins it (let its number be j). For these two equations with two unknowns, the possible value of the discrepancy is found

. Then, the remaining remaining equations are sequentially connected to the first equation. For all such pairs of equations, the possible residuals are also calculated

. If among all the obtained residual values there are t identical, equal to Δ _{2t + 1} , this indicates that the fixed equation with number i is included in the desired subset of equations (and determines the position of the first error). Values of j corresponding to the condition

, will give the position another t errors. In the search process, all possible values of i are sorted.

The formal description of the decoding procedure is based on the following Theorem, Corollary and Statement [3, 4], given below without proof.

Theorem: Let Λ ^(2t) (x), B ^(2t) (x), and L _{2t be} obtained after 2t iterations of the Berlekamp-Messi algorithm. If L _2t <t or L _2t > t + 1, then there can be no t + 1 errors in the received word.

If L _2t = t, then unknown residuals corresponding to t + 1 errors can be found from the following system of equations:

Where

If L _2t = t + 1, then the residuals can be found from the system:

Where

Corollary: If L _2t = t, then the sequence of values Δ _2t +1 obtained for all pairs i and j of equations of system (4) will have the following form:

If L _2t = t + 1, then the sequence of Δ _{2t + 1} values obtained from system (6) will have the following form:

Let Cnt (S) denote the operator of counting the various values of the elements of the sequence S in the field GF (q). This operator forms a vector W of dimension q: the i-th component of the vector (i = 0 ..., q-2) corresponds to the element of the field α ⁱ ∈GF (q), the last component (i = q-1) corresponds to the zero element of the field GF (q ) Then the following statement is true.

Statement: Let Δ be the set of values of Δ _{2t + 1} such that the polynomial Λ ^{(2t + 2)} (x) has exactly t + 1 admissible roots in the field GF (q). Let W _i = Cnt (S _i ); i = 0, ..., n-1-t; P (α ^-i ) ≠ 0. Then the set Δ consists of all values of α ⁱ satisfying the condition w _{i, j} = t for all i = 0, ..., n-1-t, P (α ^-i ) ≠ 0 and l = 0, ..., q-2 .

дают позиции (j₁, j₂, …, j_t) остальных ошибок. Тогда локатор первой ошибки будет

, и локаторы остальных ошибок будут

,

…,

.The value of i for the discrepancy Δ _{2t + 1} gives the position (i ₁ = i) of the first error. Values of j satisfying the condition

give the position (j ₁ , j ₂ , ..., j _t ) of the remaining errors. Then the first error locator will be

, and the locators of the remaining errors will be

,

...

.

After finding the residual Δ _{2t + 1, the} residual Δ _{2t + 2} can be easily calculated using (4)

or (6)

A distinctive feature of the decoding procedure used in the claimed device is the control of the process of searching for t + 1 error positions by information about the reliability of characters. The decoding procedure consists of the following steps:

1) Calculation of the polynomial syndromes S (x).

2) Obtaining the locator polynomial Λ ^(2t) (x), the auxiliary polynomial B ^(2t) (x), and the formal degree of the locator polynomial L _2t using the Berlekamp-Messi algorithm.

3) Calculation of the Fourier transform of the polynomials Λ ^(2t) (x) and B ^(2t) (x) when L _2t = t or L _2t = t + 1.

4a) Calculation of the coefficients C _i = B ^(2t) (α ^-i ) / Λ ^(2t) (α ^-i ) when L _2t = t, or D _i = Λ ^(2t) (α ^-i ) / (В ^{( 2t)} (α ^-i ) · α ^-2i ) when L _2t = t + 1.

невязки Δ_2t+1 для каждого значения i∈{0,…,n-1-t} (j=i+1,…,n-1), подсчет значений W_i для каждой последовательности и фиксация значения Δ_2t+1, которое встречается точно t раз в какой-то из этих последовательностей (w_i,l=t), где4b) Calculation of sequences S _{i of} possible values

residuals Δ _{2t + 1} for each value i∈ {0, ..., n-1-t} (j = i + 1, ..., n-1), counting the values of W _i for each sequence and fixing the value Δ _{2t + 1} , which occurs exactly t times in any of these sequences (w _{i, l} = t), where

when L _2t = t, or

when L _2t = t + 1 (L is an array of character position numbers of the received codeword, ordered (maybe partially) by increasing character reliability, n _c ≤n-1-t).

.4c) Recalculation of the sequences S _i for the found value of i and fixing the positions of errors at the moments of time of equality of the residual Δ _{2t + 1 to the} values

.

5) Obtaining the polynomial Λ ^{(2t + 2)} (x), calculating the error values and correcting them.

находится при малых значениях i.With such an organization of enumeration (12, 13), an unknown discrepancy

is found at small values of i.

, соответствующая этому вектору находится первой.The proposed decoding procedure simultaneously with an increase in speed allows us to solve the problem of choosing the most probable error vector from the list. In most cases, the discrepancy

corresponding to this vector is first.

The inventive device for decoding PC codes contains: a buffer data memory 100, a block for computing syndromes 200, a Galois processor 300, a block for discrete Fourier transform 400, a block for finding error positions of weight t + 1,500, a block for sorting positions of characters 600, a block for calculating error values 700, The first adder of the elements of the Galois field 800.

The device processes the input data, which is a sequence of n m-bit characters of the code word {r _i } received from the channel, which are accompanied by the values of their reliability {rel _i }. At the same time, it performs the decoding procedure described above. The output device is a sequence of n m-bit characters of the code word with the corrected errors {c _i }.

The buffer data memory 100 (FIG. 1) is intended for temporary storage of symbols of corrected code words received from the channel. It can be implemented in a known manner based on dual-port RAM.

The unit for computing syndromes 200 performs the 1st stage of the decoding procedure, which consists in calculating the polynomial of the syndrome S (x) of the received codeword, which can be implemented in a known manner according to the Horner scheme [4, 5].

The character position sorting unit 600 sorts the character positions of the codeword received from the channel in accordance with their reliability, thereby forming a permutation table L.

Galois processor 300 - a specialized processor that performs operations in the final Galois field, can be implemented in a known manner based on the RISC architecture.

The Galois 300 processor implements the Berlekamp-Messi algorithm [4, 5], calculating in accordance with it the polynomials Λ ^(2t) (x) and B ^(2t) (x) in 2t iterations (the second stage of the decoding procedure).

или Δ=Δ_2t+1),

или

он вычисляет значение Δ_2t+2 по формуле (10) или (11) и затем Λ^(2t+2)(x) (выполнив еще две итерации алгоритма Берлекэмпа-Месси с невязками Δ_2t+1 и Δ_2t+2). Используя многочлены Λ(х)=Λ^(2t+2)(х) и S(x), процессор Галуа 300 вычисляет многочлен значений ошибок Ω(х)=Λ(x)·S(x)modx^d-1 и формальную производную Λ'(х) многочлена локаторов Λ(х) с последующей загрузкой полученных многочленов вместе с найденными позициями ошибок {РЕ} в блок вычисления значений ошибок 700. Таким образом, выполняется начало 5-го этапа процедуры декодирования.In addition, based on the information received from the search unit for error positions of weight t + 1 500 (i ₁ ∈ {PE}, Δ (

or Δ = Δ _{2t + 1} ),

or

he calculates the value of Δ _{2t + 2} by the formula (10) or (11) and then Λ ^{(2t + 2)} (x) (after completing two more iterations of the Berlekamp-Messi algorithm with residuals Δ _{2t + 1} and Δ _{2t + 2} ). Using the polynomials Λ (x) = Λ ^{(2t + 2)} (x) and S (x), the Galois 300 processor calculates the polynomial of error values Ω (x) = Λ (x) · S (x) modx ^d-1 and the formal derivative Λ '(x) of the locator polynomial Λ (x) followed by loading the obtained polynomials together with the found error positions {PE} into the error value calculation unit 700. Thus, the beginning of the 5th stage of the decoding procedure is performed.

In addition, the Galois 300 processor controls the BDPF 400 and the BPPO 500 (using Control signals). The Galois processor sets the BDPF 400 operating mode, it also loads the coefficients of the polynomials Λ ^(2t) (x) and B ^(2t) (x) into it. The Galois processor monitors the state of the FFT (State signals) and unloads from it the values of error positions of weight less than or equal to t. Also, the Galois processor monitors the state of the BPPO (State state signals) and unloads from it the values of error positions of weight t + 1 (passing them through the permutation table L of ACAS 600 first).

The DFT 400 computes the Fourier transform of the polynomials Λ ^(2t) (x) and B ^(2t) (x) (3rd stage of the decoding procedure). In addition, depending on the operating mode, it calculates the coefficients C _i or D _i , as well as the coefficients A _i = α ⁱ (step 4a of the decoding procedure). These coefficients are loaded into the memory of the BPPO 500 block, addressed using the permutation table L of the ACAS 600 block. The DFT block also calculates the quantities inverse to the roots of the polynomial Λ ^(2t) (x) and controls their number if L _2t ≤t.

,

или

. Таким образом выполняются этапы 4b и 4с процедуры декодирования.The search unit for error positions of weight t + 1 500, depending on the operating mode, analyzes system (4) with coefficients C _i or system (6) with coefficients D _i . He finds the error positions of weight t + 1 and the corresponding Δ values,

,

or

. Thus, steps 4b and 4c of the decoding procedure are performed.

The error value calculation unit 700, using the polynomials Ω (x) and Λ '(x), calculates the error values at the found error positions {PE}. It can be implemented in a known manner using Forney's formula [4, 5]. The error values are summed using the adder 800 with the corresponding characters of the codeword read from the data buffer memory. This corrects erroneous codeword characters. Thus, the main part of the 5th stage of the decoding procedure is performed.

The presented decoder works according to the conveyor principle: all its main modules work in parallel, processing various codewords sequentially received from the channel. The conveyor principle of operation of the decoder is illustrated in Fig.9.

Consider, for example, the processing by the decoder of the kth codeword in which t + 1 errors occurred.

First, in the 1st frame (the frame corresponds to the time of arrival of one codeword), the k-oe word is written to the data buffer 100 and at the same time, at the rate of arrival at the decoder, it is processed by the syndrome calculation unit 200 and the character position sorting unit 600.

Then, in the first half of the 2nd frame, the Galois 300 processor implements the Berlekamp-Messi algorithm for the calculated syndrome, analyzes L _2t and at the beginning of the second half of the 2nd frame loads the coefficients of the polynomials Λ ^(2t) (x) and B ^(2t) (x) in the block DFT 400 (Low level on the line "BDPF" Fig.9).

During the second half of the 2nd frame and the first half of the 3rd frame, the DFT 400 performs the Fourier transform of the polynomials Λ ^(2t) (x) and B ^(2t) (x) of the k-th code word (high level on the 'BDPF' line ) In addition, depending on the operating mode, it calculates the coefficients C _i or D _i and A _i , which are loaded into the BPOA memory, addressed using the permutation table L of the ACAS unit. If L _2t ≤t, the DFT 400 block also calculates the quantities inverse to the roots of the polynomial Λ ^(2t) (x) and controls their number.

(или Δ=Δ_2t+1) k-го кодового слова, их подсчет и фиксацию тех их значений, которые встретились в цикле сканирования ровно t раз.During the second half of the 3rd frame and the first half of the 4th frame, the error position search block of weight t + 1 500 performs the calculation of the values

(or Δ = Δ _{2t + 1} ) of the k-th codeword, their calculation and fixing of those values that occurred exactly t times in the scan cycle.

During the second half of the 4th frame and the first half of the 5th frame, the block for searching for error positions of weight t + 1 500 using the fixed value Δ determines the positions t + 1 of the erroneous characters of the k-th code word. The values of these positions are adjusted using table L during their transfer to the Galois processor.

During the second half of the 5th frame, the Galois processor 300 calculates the polynomials Ω (x) and Λ '(x) and loads them into the error value calculation unit 700.

During the 6th frame, the error value calculation unit 700 calculates the error values for the corresponding positions of the k-th codeword, unloaded from the data buffer 100 and corrects them using the adder 800.

Similarly, processing is carried out k + 1, k + 2, etc. codewords received from the channel.

We present in accordance with the invention a description of the device and the operation of the main non-trivial blocks of the decoder.

Character Sort Block 600

The functional diagram of the block character position sorting (ACAS) 600 is shown in figure 2. The block contains: a code comparison scheme 610; five memory blocks of sorted positions (BPOP) 620.1-620.5; two five-input switches 630.1, 630.2; binary counter at n 640; two binary counters on 5 650.1, 650.2; two decoders for 5 states 660.1, 660.2; five two-input switches 670.1-670.5.

ACAS sorts the positions of the symbols of the codeword received from the channel in accordance with their reliability. Sorting is carried out when the characters arrive at the decoder, and a permutation table L is formed. The table consists of two parts: the positions of unreliable characters (for which the reliability is less than a specified threshold) are located at the lowest addresses, and the positions of the remaining characters are located at the senior addresses. A symbol reliability comparison with a threshold is carried out by a code comparison scheme 610, at the output of which a logical “1” is generated if the reliability value supplied to the first inputs of ACAS SoftIn is greater than the “Thres” threshold value.

Permutation tables are generated and then stored in each of the BPOPS 620 blocks. Five blocks are necessary for organizing the pipeline operation of the decoder, taking into account the fact that the generated table L for the codeword will be used with a delay.

The amount of delay is visible on the timing diagrams of the decoder (Fig.9). So, for the k-th codeword, a permutation table is formed in the 1st frame, used in the 2nd half of the 2nd and 1st half of the 3rd frame, and again in the 2nd half of the 4th and 1st half of the 5th frame.

Five BPOPS 620 blocks make it possible to create a table L for symbols of a codeword arriving at a decoder and at the same time use permutation tables to process two other codewords received at a decoder earlier.

которого подается логический "0" (активный уровень) с выхода дешифратора 660.1.To organize simultaneous access to three of the five BPPO blocks, counters 640, 650.1, 650.2 are used; decoders 660.1, 660.2 and switches 630.1, 630.2, 670.1-670.5. The counters 640, 650.1 and the decoder 660.1 are designed to control the recording in the BPOP when forming the permutation table. Counter 640 stores the position of the current symbol, which is fed to the input of the DI data of all the BOPs simultaneously with the supply of the reliability flag generated by the code comparison circuit 610 to the B SOP input S. Recording will be done in that BPOP, at the entrance

which serves a logical "0" (active level) from the output of the decoder 660.1.

The counter 650.2, the decoder 660.2 and the switches are designed to control reading from the BPOP when accessing the permutation table. Moreover, the switches 630.1, 630.2 are designed to connect the DO BPO outputs to the second (DOR1) or first (DOR2) outputs of the ACAS unit 600. Switches 670.1-670.5 are designed to connect the Adr BPOP address inputs to the third (AdR1) or second (AdR2) ACAS inputs. The direction of data transfer by the switches is determined by the counter 650.2.

Functional diagram of BPOP 620 is shown in Fig.3. BPOP contains: two memory blocks with random access 621.1, 621.2; two logical elements NAND 622, 627; two binary counters 623.1, 623.2; four switches 624.1, 624.2, 625.1, 625.2; subtractor 626.

The memory 621.1 is intended for storing positions of unreliable characters of the codeword of the permutation table L, the positions of the reliable characters are stored in memory 621.2.

BPOP operates in two modes:

1) the mode of writing to the memory the position of the symbol of the code word;

2) reading mode from the permutation table.

Если

БПОП работает в режиме чтения таблицы перестановок.The first mode is used to form a permutation table; in this mode, a logical zero is supplied to the third input of the BPOA

If

BPOP works in the reading mode of the permutation table.

, подаваемому на третий вход БПОП, коммутаторы 624 подают на третьи (адресные входы) блоков памяти 621 содержимое счетчиков 623, которые содержат адреса следующих незаписанных ячеек памяти. Если на второй вход БПОП подается сигнал sel=0 (для ненадежного символа), по сигналу

осуществляется запись позиции символа с первых входов БПОП (DI) в память 621.1 и по завершению записи содержимое счетчика 623.1 инкрементируется. Если сигнал sel=1 (для надежного символа), осуществляется запись в память 621.2 и инкремент счетчика 623.2.BPOP in the first mode works as follows. By active signal

supplied to the third input of the BPOA, the switches 624 provide the third (address inputs) of the memory blocks 621 with the contents of the counters 623, which contain the addresses of the following unrecorded memory cells. If the signal sel = 0 (for an unreliable symbol) is supplied to the second input of the BPOA, the signal

the position of the symbol is recorded from the first inputs of the BPOE (DI) into the memory 621.1, and upon completion of recording, the contents of the counter 623.1 are incremented. If the signal sel = 1 (for a reliable character), it is written to the memory 621.2 and the increment of the counter 623.2.

In the second mode of operation of the BPOA, the following information is output to the outputs of the BPOA (DO):

1) the number of positions of unreliable characters stored in memory 621.1 (the contents of the counter 623.1) needed to determine the variable n _C in formulas (12, 13);

2) the contents of the permutation table L at the address supplied to the fourth inputs of the BPOE (Adr) (contents of memory cell 621.1 or 621.2).

If the most significant bit of the Adr input bus is “1”, then through the switch 625.2 the contents of the counter 623.1 are fed to the outputs of the BPOA (DO). Otherwise, the outputs through the switches 625 serves the contents of one of the memory blocks 621.

If the contents of the Adr bus will be less than the contents of the counter 623.1 (there is no loan at the second output of the subtractor 626 that controls the switch 625.1), then the contents of the memory cell 621.1 addressed directly to the contents of the bus of the Adr address will be sent to the BPOA outputs. Otherwise, the contents of the memory cell 621.2, addressed by the difference between the contents of the bus of the address Adr and the contents of the counter 623.1, will be fed to the outputs of the BPOA.

Discrete Fourier Transform 400

The functional block diagram of the discrete Fourier transform 400 is shown in Fig.7. The block contains: local control device (MUU) 410; the module of the discrete Fourier transform of the polynomial Λ ^(2t) (x) 420.1; module of the discrete Fourier transform of the polynomial B ^(2t) (x) 420.2; cross switch 430; inverter of Galois field elements 440; a multiplier of two elements of the Galois field 450; two-input switch 460, multiplier by α 470; register latch 480, working on the front of the clock signal; binary counter of position numbers of the received word 490 with a conversion factor n.

The local control device 410 is designed to interact with the Galois processor 300 and to control the DFT 400. It also accumulates possible error positions of a weight less than t + 1, remembering the values of i at the moment the polynomial Λ ^(2t) (α ^-i ) vanishes (signal sel0) and counting their number.

Binary counter 490 is designed to generate the value of i.

Register 480 and the multiplier by α 470 provide the formation of the value A _i = α ⁱ .

Block DPF 400 - can operate in three modes.

Zero mode. In this mode, the DFT 400 operates when L _2t <t. In this case, only the coefficients of the polynomial Λ ^(2t) (x) are loaded into it and the positions of errors of weight less than t are searched. The values of the signals at the first, fourth to sixth outputs of the B DFT (AddR1, C _i | D _i , Mskl, A _i ) are ignored.

. Для их вычисления перекрестный коммутатор 430 работает в прямом направлении, подавая на вход инвертора 440 коэффициенты Λ(α^-i). На пятом выходе БППФ значение Msk1 (исключение уравнений из системы) формируется путем подачи через коммутатор 460 сигнала со второго выхода модуля дискретного преобразования Фурье 420.1, который имеет единичный уровень, когда Λ(α^-i)=0.First mode. In this mode, the DFT 400 operates when L _2t = t. The coefficients of both polynomials Λ ^(2t) (x) and B ^(2t) (x) are loaded into it. Searches for positions of errors of weight t. Odds are calculated

. To calculate them, the cross switch 430 works in the forward direction, applying the coefficients Λ (α ^-i ) to the input of the inverter 440. At the fifth output of the FFT, the value of Msk1 (elimination of equations from the system) is formed by applying a signal from the second output of the discrete Fourier transform module 420.1 through switch 460, which has a unit level when Λ (α ^-i ) = 0.

. Для их вычисления перекрестный коммутатор 430 работает в перекрестном режиме, подавая на вход инвертора 440 значения α^-2iB(α^-i). На пятом выходе БППФ значение Msk1 формируется путем подачи через коммутатор 460 сигнала со второго выхода модуля дискретного преобразования Фурье 420.2, который имеет единичный уровень, когда В(α^-i)=0.The second mode. In this mode, the DFT 400 operates when L _2t = t + 1. The values of the coefficients of the polynomials Λ ^(2t) (x) and x ² · B ^(2t) (x) are loaded into it. Odds are calculated

. To calculate them, the cross switch 430 operates in a cross mode, feeding the values of α ^-2i B (α ^-i ) to the input of inverter 440. At the fifth output of the FFT, the value of Msk1 is formed by supplying through the switch 460 a signal from the second output of the discrete Fourier transform module 420.2, which has a unit level when B (α ^-i ) = 0.

In each clock cycle of the DFT 400, at the first outputs of the discrete Fourier transform module of the polynomial Λ (x) 420.1, the value Λ (α ^-i ) appears, at the first outputs of the discrete Fourier transform of the polynomial B (x) 420.2 the value B (α ^-i ) appears (or α ^-2i B (α ^-i )), the value of A _i is generated at the output of register 480. During the cycle of operation of the DFT 400 i block, it runs through the values 0, ..., n-1.

In the first and second modes, A _i , C _i | D _i and Msk1 are written into the buffer memory 550 of the block for searching for positions of errors of weight t + 1 500. To generate memory addresses 550, the counter 490 is used for writing when the value is supplied to the input of the permutation table L, stored in the block sorting character positions 600.

Functional diagram of the module of the discrete Fourier transform of the polynomial Λ ^(2t) (x) 420.1 (the module of the discrete Fourier transform of the polynomial B ^(2t) (x) 420.2 is implemented in exactly the same way) is shown in Fig. 8.

Module 420 contains a block of valves 421, register-latches operating along the front of a clock pulse, 422.0 - 422.t + 1, an adder of elements of the Galois field by t + 2 inputs 423, a selector of the zero element of the Galois field 424, multipliers by constant coefficients in the Galois field 425.1 - 425.t + 1, blocks of logical elements OR 426.1 - 426.t + 1.

Before starting the operation of the DFT 400 block, the registers 422.0 - 422.t + 1 are reset. Then, the Galois processor 300, using the local control device 410, loads into these registers through the block of gates 421 and logic blocks OR 426.1 - 426.t + 1 the coefficients of the polynomial Λ ^(2t) (x) (B ^(2t) (x), x ² B ^(2t) (x)). The sum of all the registers 422.0-422.t + 1

immediately gives the value of the polynomial at the point x = α ⁰ at the outputs of the adder of the elements of the Galois field 423.

Then the contents of each register 422.k (k = 1, ..., t + 1) are respectively multiplied by α ^-k using the multiplier by constant coefficients 425.k, where k corresponds to the degree unknown for the polynomial coefficient being processed in the register. After that, the sum of all the registers 422.0 - 422.t + 1 will give the polynomial value at the point x = α ^-1 .

The process is repeated until the polynomial value at the point x = α ^{- (n-1)} is calculated. All this time, the zero element selector of the field 424 activates the sel0 signal when a polynomial zero value is detected at the outputs of the adder 423.

Block for searching for positions of errors of weight t + 1 500

.To reduce the hardware complexity, it is desirable that the block for searching for error positions of weight t + 1 (BPPO) 500 perform the calculations as similarly as possible with the coefficients C _i in cases where L _2t = t, and with the coefficients D _i in cases where L _2t = t +1 For this, in the first case, the values of not the residuals Δ _{2t + 1} , but the values inverse to it, are calculated

.

или Δ'=Δ_2t+1) 510.1, 510.2; два блока подсчета невязок Δ' (БПН) 520.1, 520.2; коммутатор 530; регистр-защелку 540; блок памяти коэффициентов (БПК) 550, местное устройство управления (МУУ) 560.The functional block diagram of the search for positions of errors of weight t + 1 500 is shown in Fig.4. BPPO contains: two blocks for calculating the residual Δ '(BVN) (

or Δ '= Δ _{2t + 1} ) 510.1, 510.2; two blocks for calculating residuals Δ '(BPN) 520.1, 520.2; switch 530; latch register 540; coefficient memory unit (BOD) 550, local control device (MUU) 560.

Blocks 510.1, 510.2 perform Δ 'calculations in accordance with formulas (12) or (13) depending on the value of L _2t .

Blocks 520.1, 520.2 carry out the calculation of various values of Δ 'in the Galois field (w _{i, l} ) and fix the situation of equality t of the quantity of some value Δ'.

и

поступают из соответствующей пары блоков 510 и 520 через коммутатор 530 на входы регистра 540 и запоминаются в нем.The Δ '' values defined for this situation,

and

come from the corresponding pair of blocks 510 and 520 through the switch 530 to the inputs of the register 540 and are stored in it.

The coefficient memory unit 550 is intended for temporary storage of the values of A _i , C _i (or D _i ) and bit Msk1. It contains 3 sections, the operations with which are performed simultaneously. In one section, the values of A _i , C _i (or D _i ) and bits Msk1 come from the DFT 400 block, from the other section they are read out by one frame and enter blocks 510.1-510.2 to calculate Δ ', from the next section, these values, delayed by another frame, are read and used to recalculate the sequence Δ 'necessary to fix the positions of erroneous characters. BOD 550 can be implemented in a known manner based on three-port RAM.

The local control device 560 is designed to interact with the Galois 300 processor and control the BPPO unit. In particular, it calculates the sequence of read addresses of the memory block of coefficients 550. It also accumulates error configuration positions of weight t + 1, writing AR2 values onto the stack at the moment of equal values of Δ 'and Δ (signal SX _i ).

Two pairs of BVN + BPN blocks 510 and 520 are necessary to ensure the conveyor operation mode of the error position search block. Each pair of blocks 510 and 520 processes the coefficients C _i (or D _i ) of one codeword for two frames (see Fig. 9). In each frame, one pair performs Δ 'calculations and counts their values, the I / O of the other pair performs Δ' calculations to fix the positions of erroneous characters in the previous code word, and the BPN memory of the same pair is simultaneously cleared.

In Fig. 4, a pair of blocks 510.1 + 520.1 counts different Δ 'values for the k-th codeword in the second half of the 3rd frame and the first half of the 4th. The positions of erroneous characters for the k-th word are fixed in the second half of the 4th frame and the first half of the 5th using block 510.1, at the same time, the memory of BPN 520.1 is written in zeros. In a similar way, a pair of blocks 510.2 + 520.2 works, processing t + 1 codeword with an offset per frame.

Consider the device and the operation of the main BPPO blocks.

The functional diagram of the unit for calculating residuals Δ '(BVN) 510 is shown in Fig.5. BVN contains: three switches from two directions 511.0, 511.1 and 511.2; two register-latches operating along the front of the clock signal 512.1 and 512.2; two adders of Galois field elements 513.1 and 513.2; Galois field element inverter 514; a multiplier of the elements of the Galois field 515; code comparison scheme (logical “1” at the output, if the codes at the inputs are equal) 516.1; Galois field zero element selector 516.2; two logical elements AND 517.1 and 517.2; logical element OR NOT 518; D-trigger, working on the edge of the clock signal 519.

BVN works in 2 modes.

In the first (main) mode, the BVN calculates the value Δ 'by the formula (12) or (13) and generates an inverse masking bit for the residual counting unit 520.

(или

для L_2t=2t+1). С помощью бита маскирования Msk2, формируемого логическим элементом ИЛИ-НЕ 518, из подсчета убираются Δ', для которых Λ^(2t)(α^-i)=0 (или В^(2t)(α^-i)=0 для L_2t=2t+1). Кроме того, из подсчета убираются нулевые значения Δ' с помощью селектора нулевого элемента поля 516.2 и логического элемента И 517.2.At the beginning of the scan cycle, according to the signal Ld (see Fig. 5) supplied to the eighth input of the IOS, the coefficient A ' _{l (i) is} latched into the register 512.1 through the switch 511.1 (the read data address AR1 of the BOD 550 is i), to the register 512.2 coefficient C ' _{L (i)} (D' _{L (i)} ) is latched through switch 511.2, mask bit Msk1 'is latched into trigger 519. In the following clock cycles, the coefficients A ' _{l (j)} , C' _{L (j)} (d ' _{l (j)} ) are read from the BOD 550 together with the corresponding bit of the mask (in this case, the read addresses of the BOD will run through the values j = i + 1, ..., n-1). At the outputs of the adder of the elements of field 513.1, the sums A ' _{L (i)} + A' _{l (j) are formed} (in the Galois field of characteristic 2, the subtraction coincides with the addition). Inverter 514 finds the reciprocal of the sum obtained in the Galois field. At the outputs of the adder of the elements of field 513.2, the sums C ' _{l (i)} + C' _{l (j)} (D ' _{l (i)} + D' _{l (j)} ) are formed, at the outputs of the multiplier 515 the quantities

(or

for L _2t = 2t + 1). Using the masking bit Msk2, formed by the OR-NOT 518 logic element, Δ 'for which Λ ^(2t) (α ^-i ) = 0 (or В ^(2t) (α ^-i ) = 0 for L _2t = 2t + 1). In addition, the zero values Δ 'are removed from the calculation using the selector of the zero element of the field 516.2 and the logical element AND 517.2.

In the second mode, the values of t positions of erroneous symbols are determined (the position value of the first error is determined in the local control device 560 when exactly t values Δ 'are detected). To do this, repeat the calculation cycle Δ ', on which a set of t identical values of Δ' was found, using the values A '' _{L (i)} , C '' _{L (j)} (D '' _{l (j)} , Msk1 '' with the second inputs of the coefficient memory unit 550. In this case, the sequence Δ 'is compared by a circuit for comparing codes 516.1 with the value Δ''stored in the register 540. Each time, when comparing, the signal SX _i takes the value logical 1, and at this moment the value AR2 is taken as the value of the position PE 'erroneous character (excluding permutation).

The block of residual counting (BPN) 520 contains (see Fig. 6): a block of valves 521, a random-access memory block 522 with a latch of output data at the output along the clock edge, an increment scheme 523, a code comparison circuit 524, a two-way switch 526, register-latch 527, logical elements And 525 and 528.

The BPN is based on memory 522, which contains 2 ^m words (2 ^m is the number of elements of a finite Galois field) with a width of log ₂ t. The memory word stores the counter value of the corresponding value Δ '(w _{i, l} ).

The residual counting unit operates in two modes.

In the first mode, various Δ 'values are counted. The Δ 'values arriving at the block input are latched into register 527. The contents of memory cell 522 (counter w _{i, l} ) corresponding to this Δ' value are increased by 1 using the increment scheme 523 and written to the same memory cell through the open valve block 521. The code comparison circuit 524 checks if the counter value t has not reached, and if it does, it generates a signal for detecting the residual value Δ 'corresponding to the error configuration of weight t + 1.

The logic zero level at the output of element 528, which is formed when the active signal Msk2 or inactive signal permits work E, blocks the increment of the number Δ 'located on the output of the memory.

In the second operation mode of the on-load tap-changer (initialization mode) specified by the signal I at the first input of the on-load tap-changer, zero words are written to all memory cells 522. The addresses of the memory cells 522 in this mode are received through the switch 526 from the local control device 560. Zero words at the input of the memory 522 are obtained using the block of valves 521.

The proposed device for decoding Reed-Solomon codes is a synchronous stream decoder that processes the input data at the rate of their arrival. The output is clocked by the frequency of the input, and therefore output at the same rate. The data delay in the device is equal to the arrival time of five code words. The size of the buffer memory data 100 will be equal to 5n characters.

The inventive device consists of simple in its functional purpose elements and therefore can easily be implemented on FPGA or specialized LSI.

составляющих его бит.The results of the study of the performance of the inventive decoder in the channel with additive white Gaussian noise (AWGN) and BPSK modulation are shown in Fig.10. As a measure of the reliability of the word symbol of the PC code, the minimum value of the soft decision modules was used

its constituent bits.

невязок декодером при исправлении t+1 ошибок.By simulation, we studied PC codes with d = 13, defined over a finite field GF (2 ⁸ ), n _c = 30. Channel model - BPSK, AWGN, E _b / No = 7 db. On the graph, ξ denotes a coefficient for increasing the speed of searching for unknown residuals, equal to the ratio of n _s · n _w (n _w is the number of processed code words in the modeling process) to the real number of calculations

discrepancies by the decoder when correcting t + 1 errors.

Curve 1 corresponds to the case of decoding code words with t + 1 error according to the algorithm [3] (characterizes the possibility of increasing the speed of the prototype decoder by averaging the decoding time of code words), curve 2 - to the case of controlling the search for discrepancies with information about the reliability of symbols received from the channel. To obtain the value of ξ, n _w = 10 ⁷ codewords were processed at one point. The graph shows that the performance gain in a controlled search is approximately two decimal orders.

The use of information about the reliability of the codeword symbols received from the channel in the process of searching for unknown residuals provides significantly greater performance of the inventive decoding device compared to the prototype.

Information sources

1. US patent 6631172. IPC ⁷ H03D 1/00. Efficient List Decoding Of Reed-Solomon Codes For Message Recovery In The Presence Of High Noise Levels. / Mohammad Amin Shokrollahi, Vadim Olshevsky - 05/01/2000 N09 / 563602; publ. 10/07/2003.

2. U.S. Patent 6,634,007. IPC ⁷ Н03М 13/00. Algebraic Soft-Decision Decoding of Reed-Solomon codes. / Ralf Koetter, Alexander Vardy - Declared 1/23/2000 N09 / 602914; publ. 10/14/2003.

3. Egorov S., Markarian G., Pickavance K. A Modified Blahut Algorithm for Decoding Reed-Solomon Codes Beyond Half the Minimum Distance // IEEE Trans. on Commun., vol. 52, no.12, December. 2004, pp. 2052-2056.

4. Egorov S.I. Error correction in the information channels of computer peripherals. Monograph. Kursk: Kursk, state. tech. Univ., 2008 .-- 252 p.

5. Bleikhut R. Theory and practice of error control codes: Per. from English - M.: Mir, 1986 .-- 576 p.

Claims (6)

1. A Reed-Solomon code decoding device comprising a data buffer, a syndrome calculation unit, a Galois processor, a discrete Fourier transform unit, an error position search unit, an error value calculation unit, a first adder of Galois field elements, the inputs of the data buffer memory and the inputs of the block syndrome calculations are inputs of data symbols of a Reed-Solomon code decoding device, outputs of the data buffer memory are connected to the first inputs of the first adder of Galois field elements, outputs of the calculation unit with ndromes are connected to the first inputs of the Galois processor, the first outputs of the Galois processor are connected to the first inputs of the discrete Fourier transform block, the second outputs of the Galois processor are connected to the second inputs of the discrete Fourier transform block, the third outputs of the Galois processor are connected to the third inputs of the discrete Fourier transform block, fourth outputs of the processor Galois connected to the fourth inputs of the error position search unit, fifth outputs of the Galois processor connected to the first inputs of the error value calculation unit ok, the sixth outputs of the Galois processor are connected to the second inputs of the error value calculation unit, the seventh outputs of the Galois processor are connected to the third inputs of the error value calculation unit, the second outputs of the discrete Fourier transform unit are connected to the third inputs of the Galois processor, the third outputs of the discrete Fourier transform unit are connected to the fourth Galois processor inputs, the fourth outputs of the discrete Fourier transform block are connected to the first inputs of the error position search block, the fifth output of the discrete Fourier transform Fourier transform is connected to the second input of the error position search unit, the sixth outputs of the discrete Fourier transform unit are connected to the third inputs of the error position search unit, the first outputs of the error position search unit are connected to the fifth inputs of the Galois processor, the second outputs of the error position search unit are connected to sixth inputs Galois processor, the third outputs of the error position search unit are connected to the seventh inputs of the Galois processor, the fourth outputs of the error position search unit are connected to the eighth inputs of the processor alua, the outputs of the error value calculation unit are connected to the second inputs of the first adder of the Galois field elements, the outputs of the first adder of the Galois field elements are data outputs of a Reed-Solomon code decoding device, characterized in that a unit for sorting character positions is introduced into the device, the first inputs of the sorting unit the positions of the symbols are inputs of the estimates of the reliability of the data symbols of the Reed-Solomon code decoding device, the fifth outputs of the error position search unit are connected to the second inputs of rtirovki character positions, the first outputs of the discrete Fourier transform unit connected to a third input block sort of character positions, the first unit outputs the sort of character positions are connected to second inputs of the processor Galois second sorting unit outputs character positions are connected to inputs of the fifth block search position errors. 2. The device according to claim 1, characterized in that the character position sorting unit comprises a first code comparison scheme, a first sorted position memory block, a second sorted position memory block, a third sorted position memory block, a fourth sorted position memory block, and a fifth sorted memory block positions, first switch, second switch, third switch, fourth switch, fifth switch, sixth switch, seventh switch, first counter, second counter, third counter, first decoder, w a second decoder, the first inputs of the first code comparison circuit being the first inputs of the character position sorting block, the second inputs of the first code comparison circuit connected to the Thres constant bus, the output of the first code comparison circuit connected to the second input of the first memory block of sorted positions, with the second input of the second block memory of sorted positions, with the second input of the third memory block of sorted positions, with the second input of the fourth memory block of sorted positions and with the second input of the fifth memory block of sorted positions, the first outputs of the first counter are connected to the first inputs of the first memory block of sorted positions, with the first inputs of the second memory block of sorted positions, with the first inputs of the third memory block of sorted positions, with the first inputs of the fourth memory block of sorted positions and with the first inputs of the fifth memory block sorted items, the second output of the first counter is connected to the input of the second counter, the outputs of the second counter are connected to the inputs of the first decoder, the first output is not of the second decoder is connected to the third input of the first memory block of the sorted positions, the second output of the first decoder is connected to the third input of the third memory block of the sorted positions, the fourth output of the first decoder is connected to the third input of the fourth block memory of sorted positions, the fifth output of the first decoder is connected to the third input of the fifth memory block of sorted positions, the outputs of the first block the memory of the sorted positions are connected to the second inputs of the first switch and the fourth inputs of the second switch, the outputs of the second block of memory of the sorted positions are connected to the third inputs of the first switch and fifth inputs of the second switch, the outputs of the third memory block of the sorted positions are connected to the fourth inputs of the first switch and the first inputs of the second switch , the outputs of the fourth memory block of sorted positions are connected to the fifth inputs of the first switch and the second inputs of the second to mmutator, the outputs of the fifth memory block of sorted positions are connected to the first inputs of the first switch and the third inputs of the second switch, the outputs of the third counter are connected to the sixth inputs of the first switch, with the sixth inputs of the second switch and the inputs of the second decoder, the first output of the second decoder is connected to the third input of the seventh switch , the second output of the second decoder is connected to the third input of the third switch, the third output of the second decoder is connected to the third input of the fourth switch a, the fourth output of the second decoder is connected to the third input of the fifth switch, the fifth output of the second decoder is connected to the third input of the sixth switch, the first inputs of the third, fourth, fifth, sixth and seventh switches are the third inputs of the block for sorting character positions, the second inputs of the third, fourth, of the fifth, sixth and seventh switches are the second inputs of the block for sorting character positions, the outputs of the third switch are connected to the fourth inputs of the first memory block of sorted positions , the outputs of the fourth switch are connected to the fourth inputs of the second memory block of sorted positions, the outputs of the fifth switch are connected to the fourth inputs of the third memory block of sorted positions, the outputs of the sixth switch are connected to the fourth inputs of the fourth memory block of sorted positions, the outputs of the seventh switch are connected to the fourth inputs of the fifth memory block sorted positions, the outputs of the first switch are the second outputs of the block for sorting the positions of characters, the outputs of the second comm Ators are the first outputs of the block for sorting character positions. 3. The device according to claim 2, characterized in that the memory block of sorted items contains a first random access memory block, a second random access memory block, a first NAND gate, a second NAND gate, a fourth counter, and a fifth counter , the eighth switch, the ninth switch, the tenth switch, the eleventh switch and the subtracter, the first inputs of the first random access memory block, the first inputs of the second random access memory block are the first inputs of the sorting memory block positions, the first input of the first logical element AND-NOT, the first input of the second logical element AND-HE, the third input of the eighth switch, the third input of the ninth switch are the third input of the memory block of sorted positions, the second input of the first logical element AND, NOT, the second input of the second logical AND-NOT gates are the second input of the memory block of sorted positions, the output of the first logical AND gate NOT connected to the second input of the first random access memory block and the fourth counter input, outputs the fourth counter is connected to the first inputs of the eighth switch, the second inputs of the eleventh switch and the first inputs of the subtracter, the outputs of the eighth switch are connected to the third inputs of the first memory block with random access, the outputs of the first memory block with random access are connected to the first inputs of the tenth switch, the output of the second logic element AND NOT connected to the second input of the second random access memory unit and the input of the fifth counter, the outputs of the fifth counter are connected to the first inputs of of the ninth switch, the outputs of the ninth switch are connected to the third inputs of the second random access memory block, the outputs of the second random access memory are connected to the second inputs of the tenth switch, the second inputs of the subtractor and the second inputs of the eighth switch are the fourth inputs of the memory block of sorted positions, and the senior bit the fourth inputs of the memory block of sorted items is connected to the third input of the eleventh switch, the first outputs of the subtractor are connected to the second inputs of the ninth nth switch, the second output of the subtractor is connected to the third input of the tenth switch, the outputs of the tenth switch are connected to the first inputs of the eleventh switch, the outputs of the eleventh switch are the outputs of the memory block of sorted positions. 4. The device according to claim 1, characterized in that the error position search unit comprises a first residual calculation unit, a second residual calculation unit, a first residual calculation unit, a second residual calculation unit, a twelfth switch, a first latch register, a coefficient memory unit, a first a local control device, the first inputs of the first local control device being the fourth inputs of the error position search unit, the second inputs of the first local control device and the first inputs of the coefficient memory unit and the inputs of the error position search block, the third inputs of the error position search block are the lower bits of the second inputs of the coefficient memory block, the first inputs of the error position search block are the middle bits of the second inputs of the coefficient memory block, the second input of the error position search block is the highest bit of the second inputs of the memory block coefficients, the least significant bits of the first outputs of the coefficient memory block are connected to the first inputs of the first block for calculating the residuals and to the first inputs of the second block for calculating the blind short, the middle digits of the first outputs of the coefficient memory block are connected to the third inputs of the first residual calculation block and to the third inputs of the second residual calculation block, the highest bit of the first outputs of the coefficient memory block is connected to the fifth input of the first residual calculation block and to the fifth input of the second residual calculation block, the least significant bits of the second outputs of the coefficient memory block are connected to the second inputs of the first residual calculating unit and with the second inputs of the second residual computing unit, the middle bits are of the other outputs of the coefficient memory block are connected to the fourth inputs of the first residual calculation block and to the fourth inputs of the second residual calculation block, the highest bit of the second outputs of the coefficient memory block is connected to the sixth input of the first residual calculation block and to the sixth input of the second residual calculation block, the first outputs of the first block residual computations are connected to the sixth inputs of the twelfth switch, the second outputs of the first residual computation unit are connected to the fifth inputs of the twelfth switch, the third the output of the first residual calculation block is connected to the fourth input of the first residual counting block, the fourth outputs of the first residual calculation block are connected to the third inputs of the first residual counting block, the fifth output of the first residual calculation block is connected to the third input of the first local control device, the first output of the first residual counting block connected to the fifth input of the first local control device, the second outputs of the first residual counting unit are connected to the fourth inputs of the twelfth switch, the first the outputs of the second residual calculation block are connected to the first inputs of the twelfth switch, the second outputs of the second residual calculation block are connected to the second inputs of the twelfth switch, the fifth output of the second residual calculation block is connected to the fourth input of the first local control device, the fourth outputs of the second residual calculation block are connected to third inputs the second block of calculation of residuals, the third output of the second block of calculation of residuals is connected to the fourth input of the second block of calculation of residuals, the second the moves of the second residual counting unit are connected to the third inputs of the twelfth switch, the first output of the second residual counting unit is connected to the sixth input of the first local control device, the third output of the first local control device is connected to the seventh input of the first residual calculation unit, the fourth output of the first local control device is connected to the eighth input of the first residual computing unit, the fifth output of the first local control device is connected to the ninth input of the first residual computing unit k, the sixth outputs of the first local control device are connected to the fourth inputs of the coefficient memory unit, the seventh outputs of the first local control device are connected to the third inputs of the coefficient memory unit, the eighth outputs of the first local control device are connected to the second inputs of the first residual counting unit, the ninth output of the first local device control is connected to the first input of the first block of residual counting, the tenth output of the first local control device is connected to the fifth input of the first residual counting unit, the eleventh output of the first local control device is connected to the fourth input of the first register-latch, the twelfth outputs of the first local control device is connected to the seventh inputs of the twelfth switch, the thirteenth output of the first local control device is connected to the fifth input of the second residual counting unit, the fourteenth output of the first the local control device is connected to the first input of the second residual counting unit, the fifteenth outputs of the first local control device the connections are connected to the second inputs of the second block of residuals, the sixteenth output of the first local control device is connected to the ninth input of the second block of residuals, the seventeenth output of the first local control device is connected to the eighth input of the second block of residuals, the eighteenth output of the first local control device is connected to the seventh input of the second block for calculating residuals, the first outputs of the first local control device are the fifth outputs of the block for searching for error positions, the second the moves of the first local control device are the first outputs of the error position search unit, the first outputs of the twelfth switch are connected to the first inputs of the first register-latch, the second outputs of the twelfth switch are connected to the second inputs of the first register-latch, the third outputs of the twelfth switch are connected to the third inputs of the first register latches, the second outputs of the first register-latches are connected to the tenth inputs of the first block of residual calculation, the tenth inputs of the second block of residual calculation and I are the second outputs of the error position search unit, the first outputs of the first latch register are the third outputs of the error position search unit, the third outputs of the first latch register are the fourth outputs of the error position search unit. 5. The device according to claim 4, characterized in that the residual calculating unit comprises thirteenth, fourteenth and fifteenth switches, a second latch register, a third latch register, a second adder of Galois field elements, a third adder of Galois field elements, a first Galois field element inverter , the first multiplier of the Galois field elements, the second code comparison scheme, the first selector of the zero Galois field element, the first logical element AND, the second logical element AND, the logical element OR-NOT, D-trigger, with the first inputs of the thirteenth comm the tator are the first inputs of the residual calculation block, the second inputs of the thirteenth switch are the second inputs of the residual calculation block, the first inputs of the fourteenth switch are the third inputs of the residual calculation block, the second inputs of the fourteenth switch are the fourth inputs of the residual calculation block, the first input of the fifteenth switch is the fifth input of the calculation block residuals, the second input of the fifteenth switch is the sixth input of the residual calculation unit, the third input of the thirteenth utator, the third input of the fourteenth switch, the third input of the fifteenth switch are the seventh input of the residual calculation unit, the outputs of the thirteenth switch are connected to the first inputs of the second register-latch and the second inputs of the second adder of the Galois field elements, the second input of the second register-latch, the second input of the third register latches, the second input of the D-flip-flop is the eighth input of the residual calculation unit, the outputs of the second register-latch are connected to the first inputs of the second adder of the Galois field elements and are by the second outputs of the residual calculation block, the outputs of the second adder of Galois field elements are connected to the inputs of the first inverter of Galois field elements, the outputs of the first inverter of Galois field elements are connected to the first inputs of the first Galois field element multiplier, the outputs of the first Galois field element multiplier are connected to the second inputs of the second circuit code comparisons are the fourth outputs of the residual computation unit, the first inputs of the second code comparison circuit are the tenth inputs of the residual computation unit, w output A second code comparison circuit is connected to the first input of the first logical element And, the output of the first logical element And is the fifth output of the residual calculation block, the outputs of the fourteenth switch are connected to the first inputs of the third register-latch and the second inputs of the third adder of the Galois field elements, the outputs of the third register-latch connected to the first inputs of the third adder of the elements of the Galois field and are the first outputs of the block for calculating the residuals, the outputs of the third adder of the elements of the Galois field are connected to the input by the first selector of the zero element of the Galois field and the second inputs of the first multiplier of the elements of the Galois field, the output of the first selector of the zero element of the Galois field is connected to the first input of the second logical element And, the second input of the second logical element And is the ninth input of the residual calculation block, the output of the second logical element And connected to the first input of the OR-NOT logical element, the output of the fifteenth switch is connected to the second input of the logical element OR-NOT and the first input of the D-trigger, the output of the D-trigger is connected inen with the third input of the OR-NOT logical element, the output of the OR-NOT logical element is connected to the second input of the first AND logical element and is the third output of the residual calculation block. 6. The device according to claim 4, characterized in that the residual counting unit comprises a first valve block, a third random access memory block, an increment circuit, a third code comparison circuit, a sixteenth switch, a fourth latch register, a third logical element And, a fourth logical element And, with the second input of the first block of gates and the third input of the sixteenth switch being the first input of the block of counting residuals, the outputs of the first block of gates are connected to the first inputs of the third block of memory with random access, outputs the third random access memory block are connected to the first inputs of the increment circuit, the outputs of the increment circuit are connected to the first inputs of the first valve block and the first inputs of the third code comparison circuit, the second inputs of the third code comparison circuit are connected to the constant bus 't', the output of the third code comparison circuit connected to the first input of the third logical element AND, the output of the third element logical AND is the first output of the block of residuals, the first inputs of the sixteenth switch are the second inputs of the block residual counting, the outputs of the sixteenth switch are connected to the second inputs of the third random access memory block, the inputs of the fourth latch register are the third inputs of the residual counting unit, the outputs of the fourth latch register are connected to the second inputs of the sixteenth switch and are the second outputs of the residual counting unit, the first input the fourth logical element And is the fourth input of the block counting residuals, the second input of the fourth logical element And is the fifth input of the block counting not yazok, the output of the fourth AND gate is connected to a second input increment circuit and a second input of the third logic element I.

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