RU2377644C1 - Method of processing quasi-optimal signals and device for realising said method - Google Patents

Abstract

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to devices for optimal reception of pseudonoise signals using matched filters. The method involves converting radio-frequency oscillation to a time and amplitude sampled signal. The obtained code is recorded in an n bit shift register. In each i^th section of a multisection digital filter, separately for the input i^th program code "1" and for program code "0", autocorrelation functions are formed by taking off the constant component from the results of summing output signals, and compared with corresponding thresholds. If the thresholds are exceeded, the other permitted signal is blocked for a time. The device for processing composite quasi-optimal signals includes a sampling device, n stages of a multisection digital/matched filter. Each stage includes shift registers for direct and inverse codes, first and second adders, first and second device for taking off the constant component, first and second threshold devices, gate circuits "1" and "0", first and second timers.

EFFECT: increased noise immunity of signals, easier and more reliable error-correction decoding.

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Description

The proposed technical solution is intended for use in radio engineering, namely in devices for optimal reception of pseudo-noise signals using matched filters. It is preferable to use the proposed group of inventions in space command radio links.

At present, noise-like signals of various types are known (Barker codes, M-sequences, Gold codes, additional codes, etc.) with good autocorrelation and cross-correlation properties, which are widely described in the technical literature (L.E. Varakin “Theory of complex signals” , Soviet Radio, Moscow, 1970; Alekseev A.I. et al., “Theory and Application of Pseudorandom Signals”, Nauka, Moscow, 1969). Such signals are widely used in space command and measuring systems with optimal correlation reception, requiring significant time spent on the mandatory stage of the signal entering synchronism.

Also widely known are methods for generating noise-like signals using multi-cycle linear filters (V.D. Kolesnik, E.T. Mironchikov, “Decoding of cyclic codes”, Communication, Moscow, 1968, Fig. 3.3, p. 64; A.I. Alekseev et al., “Theory and Application of Pseudorandom Signals,” Nauka, Moscow, 1969, §4.3; W. Peterson, E. Weldon, “Codes Correcting Errors,” Mir, Moscow, 1976, Chapter 7).

When using noise-like signals decoded by known methods in space command radio links processed using matched filters, and taking into account the operating conditions at high radial velocities, developers encounter great difficulties associated with a mismatch between the received signal and the impulse response of the matched filter. To reduce losses, it is necessary to expand the uncertainty function along the frequency axis, which leads to a reduction in the duration of the pseudo-noise signal and, as a result, to a reduction in the value of its base. Even with a very accurate prediction of the orbit of the spacecraft, the need to form complex composite quasi-optimal signals leads to minimization of hardware during signal addition using matched filters compared to pseudo-random signals. For identical values of the code distance of the optimal and quasi-optimal signals, assuming that

иwhere N _i

and

hardware costs can be represented as

where i is the number of steps of the proposed complex quasi-optimal signal, k is the coefficient of complexity of the implementation of hardware. As the closest analogue for the proposed technical solutions, the well-known from the application “A method for processing a pseudo-noise signal and a device for its implementation (options)” (author Lyubchikov G.S., registration No. 2006141281, Decision on the grant of a patent for an invention dated 02.21.08) was selected

The technical result expected from the use of the proposed technical solution is to create a noise-tolerant signal that allows optimal processing using matched filters, for which it is proposed to form a complex composite quasi-optimal signal, built on the principle of "one in one". Also, the proposed technical solution will ensure the selection of the ACF in a discrete matched filter not only at the stage of processing the signal stage of a complex signal, but also at the stage of decoding subsequent stages, thereby increasing simplicity of execution and, therefore, reliability relative to the usual decoding operation with error correction. In general, the technical solution will ensure the use of complex pseudo-noise signals for transmitting information in space radio links, with optimal processing using matched filters, which allows them to be used in space command radio links with feedback as well as with delayed OS and without OS.

The expected technical result is achieved by the fact that the proposed method and device for processing complex quasi-optimal signals.

A method for processing complex quasi-optimal signals, according to which the radio frequency oscillation is converted into a signal sampled by time and amplitude, the resulting code is written into an n-bit shift register of a discrete matched filter, characterized in that the signal is processed in a multi-link matched filter, in each link of which there is a record perform for a discrete filter, consistent with direct and inverse codes, separately for the input i-th PN code "1" and for the PN code "0", form autocorrelation The functions of these signals by removing the constant component from the summation of the output signals of the indicated discrete matched filters are compared with the corresponding thresholds, when exceeded, they block another allowed signal for the duration of the output, as a result, a code is generated at the output of each link for optimal processing of the next link in the discrete matched filter , or the output signal for the last stage of a multi-link matched filter. This method of processing complex quasi-optimal signals is universal for both non-synchronous and synchronous processing, which is determined by the specific requirements and the method of generating clock signals.

The decoding device for complex quasi-optimal signals includes a sampling device, the input of which is connected to the output of the linear part of the receiving device, as well as successive n steps of optimal processing, each of which includes direct and inverse code shift registers, the first and second summing devices, the first and second removal devices DC component, first and second threshold devices, key circuits “1” and “0”, first and second timers. The inputs of the shift registers of the forward and inverse codes are connected to the pulse outputs “1” and “0”, or a sampling device, or a previous decoding stage, as well as to clock sources with frequencies selected for each decoding stage. The first group of outputs of the shift registers of direct and inverse codes is connected to series-connected: the first adder, the first device for removing the DC component, the first threshold device and the key circuit "1". The second group of outputs of the shift registers of the direct and inverse codes is connected to series-connected: the second summing device, the second device for removing the DC component, the second threshold device and the key circuit "0". The output of the key circuit "1" is the pulse output "1" of the stage of a multi-link discrete optimal filter and, in the presence of subsequent stages, is connected to the information input "1", and simultaneously through the first timer it is connected to the prohibitive control input of the key circuit "0". The output of the key circuit “0” is the pulse output “0” of the decoding stage. In the presence of subsequent steps, the output of the key circuit "0" is connected to the information input "0", and simultaneously through the second timer it is connected to the prohibitive control input of the key circuit "1".

The proposed technical solution is illustrated by drawings:

Figure 1 - Block diagram of a device for processing complex quasi-optimal signals;

Figure 2 - Timing diagram of a device for processing complex quasi-optimal signals.

The block diagram of the complex quasi-optimal signal processing device is shown in FIG. 1, the processing of the complex quasi-optimal signal is illustrated by the time diagram shown in FIG. 2 and illustrating the type of code combinations at the input of the signal conditioning device, as well as at the output of the optimal processing steps.

A device for processing complex quasi-optimal signals includes a sampling device for an input analog pseudo-noise signal 1, the inputs of which are supplied with a complex quasi-optimal signal and clock pulses T ₁ ,. The pulse outputs "1" and "0" of the sampling device 1 are connected to the corresponding inputs of the shift registers of direct 2 and inverse 3 codes of the first stage, the inputs of which are also supplied with clock pulses T ₁ . The first group of outputs of the shift registers direct 2 and inverse 3 codes of the first stage is connected to the inputs of the first adder 4 of the first stage. The second group of outputs of the shift registers 2 and 3 of the first stage is connected to the inputs of the second summing device 5 of the first stage. The output of the first adder 4 is connected in series: the first DC device 6, the first threshold device 8 and the key circuit "1" 10. The output of the key circuit "1" 10 is the output "1" of the first decoding stage and is simultaneously connected to the input of the first a timer 12, the output of which is connected to the inhibitory input of the key circuit "0" 11. The output of the second summing device is connected to series-connected: the second device for removing the DC component 7, the second threshold device the twom 9 and the key circuit “0” 11. The output of the key circuit “0” 11 is the output “0” of the first decoding stage and is simultaneously connected to the input of the second timer 13, the output of which is connected to the inhibitory input of the key circuit “1” 10. The output buses “ 1 ”and“ 0 ”of the first decoding stage are connected to the inputs“ 1 ”and“ 0 ”of the second stage, where they are connected respectively to the inputs of the shift registers of direct 14 and 15 inverse codes.

The second and subsequent steps of the device for decoding complex quasi-optimal signals are constructed according to a similar scheme. The inputs "1" and "0" of the second and subsequent stages are connected to the inputs of the shift registers direct 14, 26 and inverse 15, 27 codes. The first group of outputs of the shift registers direct 14, 26 and inverse 15, 27 codes is connected to the inputs of the first adders 16, 28. The second group of outputs of the shift registers 14, 26 and 15, 27 is connected to the inputs of the second adders 17, 29. The outputs of the first adders devices 16, 28 are connected to series-connected: the first devices for removing the DC component 18, 30, the first threshold devices 21, 31 and the key circuits “1” 22, 34. The output of the key circuits “1” 22, 34 is the output “1” of the second and subsequent decoding steps and at the same time but it is connected to the input of the first timers 24, 36 whose outputs are connected to the inhibitory inputs of the key circuits “0” 23, 35. The outputs of the second summing devices are connected to serially connected: second devices for removing the DC component 19, 31, second threshold devices 20, 32 and key circuits “0” 23, 35. The outputs of the key circuits “0” 23, 35 are the outputs “0” of the second and subsequent decoding stages and are simultaneously connected to the inputs of the second timers 25, 37, the outputs of which are connected to the inhibit inputs of the key circuits “1” 22, 34. Weekend e buses "1" and "0" of the second and subsequent stages of decoding are connected to the inputs "1" and "0" of the next stages, where they are connected respectively to the inputs of the shift registers of the forward and inverse codes. For the last stage, the outputs "1" and "0" are the outputs of the signal processing device. Moreover, when processing the i-th stage T _i correspond to the clock pulses T (n-i + 1) during the formation of a complex quasi-optimal signal.

During operation of the device for processing complex quasi-optimal signals, the radio-frequency oscillation is converted into a signal sampled in time and amplitude. The components of the signal are optimally processed in successive n steps. In the first, second and subsequent steps, the active "1" and "0" are formed binary code. Signals “1” or “0” are sent to the shift registers of direct 2, 14, 26 and inverse 3, 15, 27 codes together with clock pulses T ₁ , T ₂ , T _n . With the input code of the subsequent decoding stages “1” or “0”, the peak of the autocorrelation function is highlighted in the first 4, 16, 28 and second 5, 17, 29 adders. The constant components of the signal are removed on the first 6, 18, 30 and second 7, 19, 31 stage devices. At the first 8, 20, 32 and second 9, 21, 33 threshold stage devices, the signal amplitude is compared with threshold values, above which pulse signals “1” or “0” are generated. Pulse signals, passing the key circuit "1" 10, 22, 34 or key circuit "0" 11, 23, 35, are the output signals. The signal from the output “1” starts the first timers 12, 24, 36 for the duration of which the key circuits “0” 11, 23, 35 are closed. The signal from the output “0” starts the second timers 13, 25, 37 for the duration of which the key closes circuits “1” 10, 22, 34. For the last stage, the pulse signal “1” or “0”, having passed the key circuits, is the output signal of the information code that starts the corresponding timer, protecting unauthorized output of a signal of the opposite value. Alternatively, at each decoding stage, it is permissible to use one shift register and remove two groups of direct and inverse codes from it, which are connected to the inputs of the corresponding adders.

Thus, the proposed technical solution provides the processing of complex pseudo-optimal signals using discrete matched filters and provides the possibility of their use for transmitting information in space radio links with both feedback and delayed OS, excluding the period of entering into communication by a signal and increasing, thus , noise immunity of the system as a whole.

Claims (2)

1. A method for processing complex quasi-optimal signals, according to which the radio-frequency oscillation is converted into a signal sampled by time and amplitude, the resulting code is recorded in an n-bit shift register of a discrete matched filter, characterized in that the signal is processed in a multi-link matched filter, where the input is recorded complex quasi-optimal signal to the sampling device is carried out according to the clock pulses T ₁ , and in each i-th link of a multi-link matched filter, recording they are derived from the clock pulses, respectively, T ₁ , T ₂ , ... T _n for a discrete filter, consistent with direct and inverse codes, separately for the input i-th PN code "1" and for the PN code "0", form the autocorrelation functions of these signals by removal of the constant component from the summation of the output signals of the indicated discrete matched filters, is compared with the corresponding thresholds, when exceeded, they block another allowed signal for the duration of the output, as a result, a code is generated at the output of each link for optimal th matched filter processing in the subsequent unit, or an output signal for the last stage of the multi-matched filter. 2. A device for processing complex quasi-optimal signals, including a sampling device, the input of which is connected to the output of the linear part of the receiving device, as well as sequentially located n-steps of a multi-link discrete / matched filter, each of which includes shift registers of direct and inverse codes, the first and second summing devices, the first and second device for removing the DC component, the first and second threshold devices, key circuits "1" and "0", the first and second timers; the inputs of the shift registers of the direct and inverse codes are connected to the pulse outputs “1” and “0”, or a sampling device, or the previous decoding stage, as well as to clock sources with frequencies selected for each decoding stage; the first group of outputs of the shift registers of direct and inverse codes is connected to serially connected: the first adder, the first device for removing the DC component, the first threshold device and the key circuit "1"; the second group of outputs of the shift registers of the direct and inverse codes is connected to series-connected: the second adder, the second device for removing the DC component, the second threshold device and the key circuit "0"; the output of the key circuit "1" is the pulse output "1" of the stage of a multi-link discrete matched filter and, in the presence of subsequent stages, is connected to the information input "1", and simultaneously through the first timer it is connected to the prohibitive control input of the key circuit "0"; the output of the key circuit "0" is the pulse output "0" of the decoding stage, and, if there are subsequent stages, it is connected to the information input "0", and simultaneously through the second timer it is connected to the prohibitive control input of the key circuit "1".

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