RU2335824C1 - Lockable thyristor and method of its operation - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: lockable thyristor incorporates, at least, one silicon chip made up of a set of p⁺n'Np'n⁺ cells connected in parallel. The lockable thyristor emitter junction represents a p⁺n'-transition in a thin n'-buffer layer 2 introduced into wide N-base 3 containing electronic traps with (5·10¹⁰÷5·10¹²) cm^-3 arranged at the center of silicon inhibited zone. The collector p'N-junction is effected by diffusion of aluminum with surface concentration of (10¹⁶÷10¹⁷) cm^-3 and arranged at the depth of (50÷120) mcm. The lockable thyristor cutting in is effected by sending the overvoltage pulse into power circuit in the locking, for the collector p'N-junction at the uprise rate of not less than 1.0 kV/ns, and cutting out is made by passing the current pulse via the control circuit in the direction locking for the control emitter junction.

EFFECT: increased operating frequency.

3 cl, 1 dwg

Description

The invention relates to the field of powerful semiconductor devices, specifically to silicon lockable thyristors, and can be used to create an element base of converter devices.

Semiconductor devices used as key elements of circuits of converting devices, in general, should have the following properties:

- block the specified (usually high) voltage in the forward and reverse directions with negligible leakage currents in the off state;

- pass large currents with minimal switching and static losses;

- switch (turn on and off) with the highest possible speeds.

At the present time, it is practically impossible to create a design that combines all of the above features simultaneously, however, there is a choice of certain relations between the listed parameters.

The semiconductor structures of silicon lockable thyristors are usually created by thermal diffusion of special impurities into its initial wafer of single-crystal silicon through its surface, creating p-type conductivity layers (introduction of boron and aluminum) and n-type conductivity (introduction of phosphorus). The boundary between these layers, called the pn- (or np-) junction, has a depth in the plate, measured from the surface through which the diffusion of the impurity was carried out.

Known lockable thyristor (ST) based on the silicon structure n ⁺ p'Nn'p ⁺ -type / A.Weber, N. Galster, E.Tsyplakov "A New Generation of Asymmetric and Reverse Conducting GTOs and their Snubber Diodes" PCIM97 Nurnberg, Power Conversion, June 1997 Proceedings /, containing an n ⁺ p'-control transition, where a thin buffer n'-layer with an increased concentration of dopant is introduced into the wide N-base from the side opposite to the narrow p'-base (10 ¹⁶ ÷ 10 ¹⁸ ) cm ^-3 . This layer limits the expansion of the space charge region (OOZ) of the collector p'N junction with an increase in the blocked voltage, which makes it possible to reduce the thickness of the N base to a value approximately equal to the OOZ width of the collector junction at the maximum voltage on the device and, accordingly, reduce the residual voltage in the on state .

In the unconnected state, the external voltage (minus at the n ⁺ emitter) in the power circuit is blocked by the reverse biased collector p'N junction. To turn on this device, a current pulse is passed in the control circuit in the conducting direction of the n ⁺ p'-junction. The electrons injected from the n ⁺ layer diffuse through the p′-layer to the space charge region (SCO) of the reverse biased p′N junction (collector), are emitted by the electric field into the quasineutral part of the N-layer, and the diffusion of the n'-layer to p ⁺ N-junction, lower its potential barrier and cause counter injection of holes from the p ⁺ -layer, thereby initiating the inclusion of the device. To turn off this device, a current pulse is passed through the control circuit in the direction shut off for the n ⁺ p'-junction (plus to the n ⁺ -layer). In this case, the injection of electrons from the n ⁺ layer stops, the electron – hole plasma is removed from the p′-layer and the collector part of the N layer, the p'N junction is displaced in the shut-off direction, and the device turns off.

In this device, switching losses are high, and the operating frequency is low, which is a drawback of such a structure.

Known lockable thyristor / Japan patent No. 6061477 /, taken as a prototype of the proposed technical solution, also containing silicon n ⁺ p'Nn'p ⁺ structure (in the prototype this is indicated as the structure of NpN ^- N ⁺ p-type). Each thyristor cell contains a control n ⁺ p'-emitter (Np) located in the p'-base layer (p), a collector p'N junction (pN ^- ) with a buffer n'-layer (N ⁺ ) in a wide N- base (N ^- ) from the side of the p ⁺ emitter (p). The edge contour is made in the form of a positive chamfer, which protects the structure from surface breakdown at high pulsed overvoltages. The lower p ⁺ emitter layer (p) is surrounded by an annular N-layer that shunts the emitter layer. Due to this, the surface leakage current of the collector p'N junction (pN ^- ) goes into the metal contact without leading to injection of holes from the emitter layer. This increases the operating voltage and operating temperature of the device. The structure is located on a metal temperature compensator.

The device works this way.

When the device is turned off, the external voltage (minus N-emitter) in the power circuit locks a reverse collector pN ^- junction. To enable the device in the control circuit, a current pulse is passed in the conducting direction for the Np junction. Electrons injected from the N layer diffuse through the p layer into the space charge region (SCO) of the reverse biased pN ^- junction (collector), are emitted by the electric field into the quasineutral part of the N ^- N ⁺ layer, and lower the potential barrier of the emitter pN ⁺ junction and cause counter injection of holes from the p-layer. These holes diffuse through the N ⁺ layer, then in the bipolar drift mode they pass through the quasineutral of the N layer and are ejected by the SCR field into the p base, causing counter injection of electrons from the N layer, etc. When the carrier loss due to recombination and escape through the potential barriers of the emitters becomes smaller than the carrier entry into the base layers due to injection, the structure goes into a stable conducting state. In this state, the base layers p and N ^are filled with a well-conducting electron-hole plasma, and a power current flows through the device.

To turn off the device, a current pulse is passed through the control circuit in the direction shut off for the Np junction (plus on the N layer). In this case, the injection of electrons from the N-layer is stopped, the electron-hole plasma is removed from the p-layer and the collector part of the N ^- layer, the pN ^- junction is displaced in the shutoff direction, and the current through the device decreases sharply. However, the electron-hole plasma remaining in the N ^- N ⁺ layer is a source of holes, and a slowly falling "tail" of the hole current flows through the device, which ceases after recombination of all excess electrons in the N ^- N ⁺ layer. The on-time is determined by the duration of electron diffusion through the p-base and the time of bipolar drift of the electron-hole plasma through the N ^- base, which in total is approximately (500 ÷ 700) nanoseconds, and the turn-off time is determined by the lifetime of excess carriers in N ^- - base and is (10 ÷ 15) microseconds, while for a considerable time the “tail” of the hole current flows with increasing voltage on the device. Because of this, switching losses in the device during shutdown are very large and therefore the maximum operating frequency does not exceed (5 ÷ 10) kHz.

The disadvantages of this structure are large switching losses, which means a low operating frequency, because in this device, the unit cells of the controlling Np emitter are located in the p-base layer, as a result of which the nature of the on and off processes leads to their long duration.

The group of inventions - a device and method of its operation, united by a single inventive concept, allows us to solve the problem of increasing the operating frequency of a lockable thyristor by reducing switching losses due to a reduction in its on and off time.

The problem is solved by a lockable thyristor containing at least one silicon chip, consisting of many p ⁺ n'Np'n ⁺ cells electrically connected in parallel, including a control emitter junction made in the form of a p ⁺ n'junction in a thin n'- a buffer layer introduced into a wide N base into which electron traps with a concentration of (5 · 10 ¹⁰ ÷ 5 · 10 ¹² ) cm ^{-3 are} introduced, the energy level of which is located in the middle of the silicon band gap, a narrow p'-base, collector p 'N-junction made by diffusion with a surface concentration of al luminium (10 ¹⁶ ÷ 10 ¹⁷ ) cm ^-3 and located at a depth of (50 ÷ 120) microns, and uncontrolled emitter n ⁺ p'-junction.

In a lockable thyristor, the edge contour can be made in the form of a positive chamfer.

The problem is also solved by the method of operation of a p ⁺ n'Np'n ⁺ -locked silicon thyristor, comprising turning on the device by passing an overvoltage pulse in the power circuit in the direction that is shut off for the collector p'N junction with a rise rate of at least 1.0 kV / ns and turning it off passing a current pulse through the control circuit in the direction shut off for the controlling emitter p ⁺ n'-junction.

The invention as a device provides a new nature of the processes of moving media in the proposed device when it is turned on and off, due to the new p ⁺ n'Np'n ⁺ structure with the location of the controlling emitter p ⁺ n'-junction in the n'-buffer layer, defined by and the location of the collector p'N junction and the presence of electron traps (atoms of deep impurities or defects capable of capturing an electron / Sah C.T., Noyce RN, Shockly W. Carrier Generation and Recombination in pn junction characteristics Proc. IRE, 45, p .1228 (1975) /) with a certain concentration and energy s, a N-layer, which can significantly reduce the switching losses and increase the operating frequency turn-off thyristor.

The boundary contour of the structure can be made in the form of a positive chamfer, which protects the structure from surface breakdown at high pulse overvoltages.

The invention as a method of operation of the proposed device, which comprises turning it on by transmitting an overvoltage pulse (i.e., a voltage exceeding the breakdown voltage of the collector junction, measured under conditions of a slow increase in voltage) in the direction that is shut off for the collector p'N junction, with slew rate of at least 1.0 kV / ns (10 ¹² V / s), enables the tunnel-thermal ionization deep electron traps and formation of shock-ionization front having a higher MSE motion velocity than the speed of motion of electrons in silicon, which leads to a significant reduction in the on time and, consequently, to a decrease in switching losses in the device, and when turned off, it is possible to output a control electron-hole plasma from an n'-layer introduced into N -layer, and then from the N-layer, which leads to a sharp (fast) turn-off of the current and also to a decrease in switching losses.

The minimum depth of the collector p'N junction from the surface of the silicon wafer through which Al diffusion (50 μm) and the maximum surface aluminum concentration (10 ¹⁷ cm ^-3 ), as shown by experiments, are determined by the maximum admissible impurity concentration gradient, higher where the launch of the shock-ionization front becomes impossible. The minimum allowable concentration of aluminum (10 ¹⁶ cm ^-3 ) is due to the fact that below this concentration the diffusion front has sharp bends, which leads to a decrease in the limit value of the blocked voltage due to sharp field distortion at the boundary inhomogeneities. The maximum depth of the p'N junction (120 μm) is limited by the acceptable duration of the diffusion process (no more than a day).

The energy level of the electron traps in the middle of the silicon band gap is due to the requirement to ensure a sufficiently high concentration of electrons trapped in the traps in the working temperature range of silicon devices (-40 ÷ + 70) ° С, which is necessary for a shock-ionization front that is uniform in area of excitation.

The range of permissible concentrations of deep electron traps was determined experimentally. At their concentration <5 · 10 ¹⁰ cm ^-3, instead of a uniformly ionized front over the area, a limited number of narrow streamer channels were excited, and the permissible amplitude of the switched current sharply decreased, and at a concentration> 5 · 10 ¹² cm ^-3 a usual avalanche breakdown occurred, and the speed inclusion sharply decreased.

With the proposed implementation of the collector p'N junction, to turn on the device it is necessary to apply a rapidly increasing pulse (speed of at least 1.0 kV / ns = 1 · 10 ¹² V / s) of overvoltage in the power circuit in the direction that is shut off for this junction. In this case, the field strength at the p'N junction significantly exceeds the critical field of avalanche breakdown under static conditions E _at ≈2 · 10 ⁵ B / cm after some time, but breakdown does not occur due to the absence of free fields in the strong field carriers that could produce ionization. When the field reaches a value of (4 ÷ 5) · 10 ⁵ V / cm, tunnel-thermal ionization of deep traps begins. The electrons released from them appear in a supercritical field and cause shock ionization of silicon, forming an electron-hole plasma with a high concentration. The field in the vicinity of the p'N junction decreases, but increases in the adjacent region of the N base, where tunnel-thermal ionization of the traps begins, etc. The shock-ionization front formed in this way moves from the p'N junction toward the n'-layer, the entire N base is filled with electron-hole plasma, and the device goes into a conducting state. The front velocity is determined mainly by the magnitude of the supercritical field and is usually 4–5 times higher than the maximum possible (saturated) electron velocity in silicon V _S ≈10 ⁷ cm / s. Therefore, the device turn-on time is tenths of a nanosecond, during this time the voltage on the device drops from (2 ÷ 3) kV to about 50 V, and the current rises to almost the nominal value, after which a further voltage drop is provided by an increase in the concentration of the electron-hole plasma in the base layers due to injection of electrons and holes by directly biased n ⁺ p'- and p ⁺ n'-emitters (the switching process continues by the usual thyristor mechanism). Since the main part of the process proceeds in fractions of a nanosecond, the switching losses in the device are several tens of times less than with the method of switching on analogs and prototypes (a typical way of turning on lockable thyristors), which ensures a decrease in switching losses and, as a result, an increase in the operating frequency of the thyristor.

To turn off the device, a current pulse is passed through the control circuit in the direction that is shut off for the control p ⁺ n'-junction, and in this device a minus is applied to the p ⁺ -layer. In this case, the injection of holes from the p ⁺ layer is interrupted, the electron-hole plasma is removed from the n'-layer, and then from the N-layer. The current through the n ⁺ p'-junction continues to flow until the entire electron-hole plasma is removed by the control current pulse, after which the p'N-collector junction goes into the locked state, and the device switches off abruptly with virtually no current tail . This process is fundamentally different from the process of turning off devices with a controlling emitter junction located in a thin p'-base in that the turn-off delay increases, but the duration of the current drop and the voltage increase on the device decreases, which leads to a sharp (tens of times) decrease in switching losses during shutdown (with lower voltage losses are less).

Thus, in a lockable silicon thyristor with the proposed design of the p ⁺ n'Np'n ⁺ structure, switching losses when switching on and off are reduced by tens of times, which allows to increase the operating frequency of powerful lockable thyristors up to the megahertz range.

The structure of the lockable thyristor is shown schematically in the drawing,

Where

1 - control p ⁺ emitter;

2 - buffer n'-layer;

3 - wide base N-layer;

4 - narrow base p'-layer;

5 - uncontrolled n ⁺ emitter;

6 - metal temperature compensator.

The device contains sequentially arranged partitioned p-type emitter layer 1, a buffer n-layer of n-type conductivity 2, a wide base N-layer of n-type conductivity 3, a narrow base p'-layer of p-type conductivity 4, a high-alloy emitter layer n-type conductivity 5 and metal temperature compensator 6.

The device operates as follows.

To start the device (in the power circuit AB), a rapidly increasing overvoltage pulse (speed of at least 1.0 kV / ns) is applied in the direction that is shut off for the collector p'N junction. The device goes into a conducting state, a power current flows through it with a small residual voltage. The device is turned off through the control circuit AC, in which a current pulse is passed in the direction that is shut off for the p ⁺ n'-junction (a minus is applied to the p ⁺ layer in the device). The device goes into off state, blocking the voltage of the power circuit.

Example 1

According to the invention (see drawing) was made silicon p ⁺ n'Np'n ⁺ -structure placed on the temperature compensator 6, with the following geometric and electrophysical parameters of the layers. The collector p'N junction was made by diffusion of aluminum with a surface concentration of N _A = 7 · 10 ¹⁶ cm ^-3 to a depth of 70 μm into the initial plate of n-type silicon with a specific resistance of ρ≥50 Ohm · cm and a thickness of 280 μm, buffer The n'-layer 2 was made by diffusion of phosphorus with a surface concentration of 1 × 10 ¹⁸ cm ^-3 to a depth of 10 μm, the p ⁺ and n ⁺ emitters 1 and 5 were made by diffusion to a depth of ~ 2 μm of boron and phosphorus with a surface concentration of ~ 10 ²⁰ cm ^-3 . The concentration of electron traps was N _l ~ 1 · 10 ¹² cm ^-3 . The blocked voltage was 1.9 kV, the residual voltage in the on state was ~ 1.3 V at a direct current density of 200 A / cm ² . The width of the unit cell of the control p ⁺ n'-emitter was ~ 10 μm. On the device with a diameter of the working part of the plate 0.7 cm placed 2 · 10 ⁴ cells. To start in the power circuit AB, an overvoltage pulse was applied, increasing at a speed of 1.2 kV / ns. In 2 ns, the voltage on the device increased to ~ 2.8 kV, and then within 0.15 ns it dropped to ~ 50 V, and then within 200 ns it decreased to 2 V at a current of 80 A. The device was turned off by passing through the control emitter p ⁺ n ' junction (in the AC circuit) of a current pulse with an amplitude of 5 A, a rise time of 20 ns, and a duration of 1 μs. In this case, the device shutdown delay was 100 ns, the fast decay portion was ~ 200 ns, and the tail of the current decay was ~ 300 ns. The maximum working frequency during forced air cooling was ~ 0.7 MHz, which is more than an order of magnitude higher than the working frequency of the prototype.

Example 2

A silicon p ⁺ n'Np'n ⁺ structure was fabricated, placed on a temperature compensator 6, with the following geometric and electrophysical parameters of the layers. The collector p'N junction was made by diffusion of aluminum with a surface concentration of N _A = 3 × 10 ¹⁶ cm ^-3 to a depth of 100 μm into the initial n-type silicon wafer with a resistivity of ρ≈100 Ω cm and a thickness of 350 μm, n the 'layer 2 was made by diffusion of phosphorus with a surface concentration of 7 · 10 ¹⁶ cm ^-3 to a depth of 18 μm, the p ⁺ and n ⁺ emitters 1 and 5 were made by diffusion of boron and phosphorus to a depth of 4 μm with a surface concentration of ~ 7 · 10 ¹⁹ cm ^-3 . The concentration of electron traps was N _L ~ 1 · 10 ¹¹ cm ^-3 . The blocked voltage was ~ 3.0 kV, the residual voltage in the on state ~ 1.5 V at a direct current density of 100 A / cm ² . The width of the unit cell of the p ⁺ n'-emitter was ~ 10 μm. On a device with a diameter of the working part of the plate 1.0 cm, 4 · 10 ⁴ cells were placed. A constant voltage of ~ 2 kV was applied to the device, and then an overvoltage pulse was applied, increasing at a speed of 1.2 kV / ns. Over 2.5 ns, the voltage on the device increased to 4.5 kV, then dropped to ~ 70 V within 0.25 ns, and then decreased to 2.5 V at a current of 100 A within 300 ns. The device was turned off by passing through a control emitter p ⁺ n'-junction a current pulse with an amplitude of 5 A, a rise time of 20 ns and a duration of 1 μs. The turn-off delay was 200 ns, the tail was ~ 500 ns. The limiting frequency under the same conditions as in example 1 was 350 kHz.

To verify the permissible ranges of changes in the structural parameters of the claimed device and the method of its operation, the following experiments were performed.

Fabricated and tested structures similar to those described in Example 1, with changes corresponding to the boundaries of the ranges of parameters and their foreign values.

Example 3

The surface concentration of aluminum varied in the following range: N _A = 5 · 10 ¹⁵ , 1 · 10 ¹⁶ , 1 · 10 ¹⁷ , 1 · 10 ¹⁸ cm ^-3 . At N _A = 5 · 10 ¹⁵ cm ^{-3, the} p'N junction had a sharply inhomogeneous front, a blocked voltage of 570 V (at the calculated value of 1.9 kV) and a large leakage current. Devices with N _A = 1 · 10 ¹⁶ and N _A = 1 · 10 ¹⁷ cm ^-3 had a lockable voltage corresponding to the rated voltage, and devices with N _A = 1 · 10 ¹⁸ cm ^-3 did not turn on at all. Thus, the working range is (10 ¹⁶ ≤N _A ≤10 ¹⁷ ) cm ^-3 .

Example 4

The concentration of N _L electron traps in the N layer was 2 · 10 ¹⁰ , 5 · 10 ¹⁰ , 5 · 10 ¹² and 8 · 10 ¹² cm ^-3 . At N _l = 5 · 10 ¹⁰ cm ^-3 and 5 · 10 ¹² cm ^-3, switching on when an overvoltage pulse was applied occurred in <1 ns; at N _L = 2 · 10 ¹⁰ cm ^{-3, the} device irreversibly broke through when turned on (probably due to the approximate nature of the inclusion), and at N _Л = 8 · 10 ¹² cm ^{-3, the} inclusion occurred at a voltage equal to the static voltage, and the switching time was ~ 0.7 microseconds. Thus, the working range of trap concentrations is (5 · 10 ¹⁰ ≤N _L ≤5 · 10 ¹² ) cm ^-3 .

Example 5

Structures similar to those described in Example 1, but with a p'N junction depth of 120, 50, 20 μm, were studied. At a depth of 120 μm and 50 μm, the instrument turned on normally for ~ 2 ns, and at a depth of 20 μm this time increased to ~ 1 μs, and the instruments failed after several starts. Since a depth of more than 120 μm is unacceptable from technological considerations (the diffusion process takes several days), the working range of the depth of the p'N junction lies in the range from 120 to 50 μm.

Example 6

On structures similar to those described in example 1, the inclusion was investigated at different rates of rise of voltage (du / dt). At du / dt = 1 kV / ns, the time of the fast switching-on section was 0.2 ns, at 2 kV / ns it was 0.1 ns (the resolution limit of the setup), at 0.7 kV / ns it was ~ 2 ns, and at 0.5 kV / ns it was 20 ns. Thus, for fast switching with low switching losses, it is necessary to have du / dt≥1 kV / ns.

Claims (3)

1. Lockable thyristor containing at least one silicon chip, consisting of many electrically connected in parallel p ⁺ n'Np'n ⁺ cells, including a control emitter junction, made in the form of a p ⁺ n'-junction in a thin n'-buffer a layer introduced into a wide N base into which electron traps with a concentration of 5 · 10 ¹⁰ to 5 · 10 ¹² cm ^{-3 are} introduced, the energy level of which is located in the middle of the silicon forbidden zone, a narrow p'-base, collector p'N transition made by diffusion with a surface concentration of aluminum from 10 ¹⁶ d about 10 ¹⁷ cm ^-3 and located at a depth of 50 to 120 microns, and uncontrolled emitter n ⁺ p'-junction. 2. Lockable thyristor according to claim 1, in which the edge contour is made in the form of a positive bevel. 3. The method of operation of a silicon p ⁺ n'Np'n ⁺ lockable thyristor, comprising turning on the device by passing an overvoltage pulse in the power circuit in the direction that is cut-off for the collector p'N junction with a slew rate of at least 1.0 kV / ns and turning it off passing a current pulse through the control circuit in the direction shut off for the controlling emitter p ⁺ n'-junction.