JP2019071503A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of reducing a leak current and suppressing oscillation at turn-off or recovery.SOLUTION: A semiconductor device comprises a first n-type buffer layer containing a proton which has a plurality of peak concentrations and in which an amount of injection becomes low as the depth from a rear surface of a semiconductor substrate becomes deeper, and a second n-type buffer layer containing phosphorus. A position of a peak concentration of the phosphorous is a position deeper than 1 μm and shallower than 6 μm from the rear surface of the semiconductor substrate. Three or more of peak concentrations of the proton exist at depths of 6 μm or higher and 30 μm or lower from the rear surface of the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device such as a diode or an insulated gate bipolar transistor (IGBT) and a method of manufacturing the same, and in particular, leakage current can be reduced, oscillation at turn-off or recovery can be suppressed, and easily in a general semiconductor factory. The present invention relates to a semiconductor device capable of forming an n-type buffer layer by proton injection and a method of manufacturing the same.

  From the viewpoint of energy saving, IGBTs and diodes are used in power modules and the like for performing variable speed control of a three-phase motor in the field of general-purpose inverters, AC servos, and the like. In order to reduce inverter loss, IGBTs and diodes are required to have devices with low switching loss and on-state voltage.

Most of the on-state voltage is the resistance of the thick n-type base layer required to hold the breakdown voltage, and to reduce the resistance, it is effective to make the wafer thinner. However, when the wafer is thinned, when a voltage is applied to the collector, the depletion layer reaches the back surface, causing a decrease in breakdown voltage and an increase in leakage current. Therefore, in general, a shallow n ⁺ -type buffer layer, which is denser than the substrate concentration, is formed on the rear surface of the substrate by an ion implantation machine.

However, with the technological innovation in IGBT manufacturing technology, the wafer thickness has been reduced to near the thickness that can ensure breakdown voltage, so in the shallow n ⁺ -type buffer layer, when IGBTs and diodes perform switching operation, power supply voltage + L * di When a surge voltage determined by / dt is applied between the collector and the emitter or between the cathode and the anode, and the depletion layer reaches the back side, carriers are depleted, and voltage and current oscillation occur. When oscillation occurs, radiation noise is generated, which adversely affects surrounding electronic devices.

On the other hand, by forming a deep n ⁺ -type buffer layer having a low concentration of about 30 μm on the back surface of the substrate, the depletion layer can be gently stopped even if a large voltage is applied to the collector or cathode at the time of switching. As a result, it is possible to prevent the depletion of carriers on the back side and to prevent a sharp rise in voltage by retaining the carrier.

FIG. 23 is a diagram showing a turn-off waveform of L load switching implemented by an IGBT with a withstand voltage of 1200 V in device simulation. As switching conditions, the depth of the n ⁺ -type buffer layer formed of phosphorus is 2 μm and 30 μm, Vce = 900 V, and Ic = 150 A. The waveform oscillates at a depth of 2 μm, but no oscillation occurs at 30 μm.

When a deep n ⁺ -type buffer layer of about 30 μm is formed by diffusion of phosphorus, it takes 24 hours or more at a general heat treatment temperature such as 1100 ° C., and mass productivity is low. Another method is to use an accelerator such as a cyclotron or a van degraph (see, for example, Patent Document 1). For example, when the silicon substrate is irradiated with protons at an acceleration voltage of 8 MeV, the range is about 480 μm and the half width is about 20 μm. In order to adjust the position of the range, irradiation energy can be decelerated to generate a broad proton peak near the surface of silicon by driving it through an absorber rather than directly into a silicon substrate. Thereafter, heat treatment is performed at 350 to 450 ° C. for 1 to 5 hours, whereby protons can be activated to form an n-type region. The rate of activation of protons is about 1% depending on the implantation conditions and heat treatment conditions.

JP, 2013-138172, A

The mechanism by which protons become donors is determined by the combined factor of the implanted hydrogen atoms, the crystal defects formed at the time of implantation, and the oxygen atoms remaining in the substrate, and the method of forming the silicon substrate, the solid solution The activation rate fluctuates depending on the oxygen concentration and proton injection conditions. When the concentration of the n ⁺ -type buffer layer formed by the proton injection fluctuates, the leak current, the variation of the on-state voltage increase, the deterioration of the short circuit resistance, etc. occur.

In addition, in order to manufacture a broad backside n ⁺ -type buffer layer with a depth of about 30 μm for IGBTs and diodes, it is necessary to inject protons by increasing the half width at a high acceleration voltage of about 8 MeV. On the other hand, conventionally, accelerators such as cyclotrons and van degraphs have been used. However, these accelerator bodies are radiation problems and need to be surrounded by a 1 to 4 m thick concrete shield and can not be easily used in a typical semiconductor factory.

  The present invention has been made to solve the above-mentioned problems, and its object is to reduce leakage current, to suppress oscillation at turn-off or at recovery time, and to facilitate proton injection even in a general semiconductor factory. A semiconductor device capable of forming an n-type buffer layer and a method of manufacturing the same.

  A semiconductor device according to the present invention is a semiconductor device provided with a semiconductor substrate, a p-type layer formed on the surface of the semiconductor substrate, and first and second n-type buffer layers formed on the back surface of the semiconductor substrate. The first n-type buffer layer is different in depth from the back surface of the semiconductor substrate, and includes protons having a plurality of peak concentrations with a lower dose as the depth from the back surface of the semiconductor substrate is deeper; The n-type buffer layer contains phosphorus, and the position of the peak concentration of phosphorus is a position deeper than 1 .mu.m and shallower than 6 .mu.m from the back surface of the semiconductor substrate, and plural peak concentrations of protons are 6 .mu.m or more and 30 .mu.m or less from the back surface of the semiconductor substrate. 3 or more at the depth of

  In the present invention, oscillation at the time of turn-off of the IGBT or at the time of recovery of the diode can be prevented by the first n-type buffer layer formed by proton implantation and having a low concentration and a deep diffusion depth. In addition, the depletion layer can be stopped by the high concentration second n-type buffer layer into which phosphorus is injected to prevent an increase in the leakage current. Further, the n-type buffer layer can be easily formed by proton injection even in a general semiconductor factory without using a cyclotron.

FIG. 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention. It is a figure which shows the back surface profile of the semiconductor device concerning Embodiment 1 of this invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor device according to Comparative Example 1; FIG. 7 is a view showing a back surface profile of the semiconductor device according to Comparative Example 1; FIG. 5 is a cross-sectional view showing a semiconductor device in accordance with a second embodiment of the present invention. It is a figure which shows the back surface profile of the semiconductor device concerning Embodiment 2 of this invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor device according to Comparative Example 2; FIG. 16 is a view showing a back surface profile of the semiconductor device according to Comparative Example 2; It is a figure which shows the turn-off waveform of L load switching implemented with IGBT with a withstand voltage of 1200V by device simulation.

  A semiconductor device according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to the drawings. The same or corresponding components may be assigned the same reference numerals and repetition of the description may be omitted.

Embodiment 1
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. This semiconductor device is an IGBT. A p-type base layer 2 is formed on the surface of an n-type silicon substrate 1. An n ⁺ -type emitter layer 3 and a p ⁺ -type contact layer 4 are formed on the p-type base layer 2. A trench gate 5 is formed in a trench penetrating the p-type base layer 2 and the n ⁺ -type emitter layer 3 via a gate insulating film. Interlayer insulating film 6 is formed on trench gate 5. Emitter electrode 7 is formed on the surface of n-type silicon substrate 1 and connected to p ⁺ -type contact layer 4.

First and second n ⁺ -type buffer layers 8 and 9 are formed on the back surface of the n-type silicon substrate 1. The first n ⁺ -type buffer layer 8 is formed by multiple injections of protons having different acceleration voltages. The second n ⁺ -type buffer layer 9 is formed by phosphorus implantation. A p-type collector layer 10 having a depth of about 1.0 μm is formed at a position shallower than the first and second n ⁺ -type buffer layers 8 and 9 from the back surface of the n-type silicon substrate 1. Collector electrode 11 is formed on the back surface of n-type silicon substrate 1 and connected to p-type collector layer 10.

FIG. 2 is a view showing a back surface profile of the semiconductor device according to the first embodiment of the present invention. The protons of the first n ⁺ -type buffer layer 8 have a plurality of peak concentrations different in depth from the back surface of the n-type silicon substrate 1. The position of the peak concentration of phosphorus in the second n ⁺ -type buffer layer 9 is shallower than the position of the peak concentration of protons in the first n ⁺ -type buffer layer 8 from the back surface of the n-type silicon substrate 1. The peak concentration of phosphorus is higher than the peak concentration of protons. At the position of the peak concentration of protons, the concentration of protons is higher than the concentration of phosphorus.

  3 to 10 are cross-sectional views showing steps of manufacturing the semiconductor device according to the first embodiment of the present invention. First, as shown in FIG. 3, the surface structure of the IGBT is formed by a normal surface process. At this time, the wafer thickness is about 700 μm, which is almost the same as the bare wafer.

  Next, as shown in FIG. 4, the back surface side of the n-type silicon substrate 1 is polished to a desired thickness by grinder or wet etching. Next, as shown in FIG. 5, protons are implanted into the back surface of the n-type silicon substrate 1 a plurality of times at different acceleration voltages of 500 keV or more and 1.5 MeV or less using a general ion implantation apparatus for semiconductor manufacture. The range of protons is 6 μm at 500 keV and about 30 μm at 1500 keV.

Next, as shown in FIG. 6, activation of protons is performed by furnace annealing at 350 ° C. to 450 ° C. to form the first n ⁺ -type buffer layer 8. Next, as shown in FIG. 7, phosphorous is implanted into the shallow region of the back surface of the n-type silicon substrate 1 at an acceleration voltage of 1 MeV or less. Next, as shown in FIG. 8, activation of phosphorus is performed by laser annealing to form a second n ⁺ -type buffer layer 9.

Next, as shown in FIG. 9, B is implanted into the back surface of the n-type silicon substrate 1. Next, as shown in FIG. 10, laser annealing is performed to form the p ⁺ -type contact layer 4. Thereafter, a collector electrode 11 of Al / Ti / Ni / Au or AlSi / Ti / Ni / Au is formed on the back surface of the n-type silicon substrate 1 by sputtering. Finally, heat treatment at about 350 ° C. is performed to reduce the contact resistance by making ohmic contact between the collector electrode 11 and the n-type silicon substrate 1. At this time, the heat treatment process can be reduced by one time by performing the heat treatment for activation of protons and performing the same process in the same process, so that the processing cost can be reduced.

Subsequently, the effect of the present embodiment will be described in comparison with a comparative example. FIG. 11 is a cross-sectional view showing a semiconductor device according to Comparative Example 1. As shown in FIG. FIG. 12 is a diagram showing the back surface profile of the semiconductor device according to Comparative Example 1. As shown in FIG. In Comparative Example 1, the n ⁺ -type buffer layer 12 is formed as deep as about 30 μm by proton injection using an accelerator such as a cyclotron or a Bandograph.

  When protons are injected at 1.5 MeV, the range is about 30 μm, and a deep buffer layer can be formed which can be expected to have an oscillation suppression effect. The acceleration voltage can be increased up to about 1.5 MeV even in a general ion implantation apparatus for semiconductor manufacturing. However, since the diffusion layer formed at a low acceleration voltage by the ion implantation apparatus for semiconductor manufacture has a small half width, it is difficult to form a broad diffusion layer as produced by cycloton.

Therefore, in the present embodiment, the first n ⁺ -type buffer having a relatively broad profile as shown in FIG. 2 is implemented by performing a plurality of proton injections at different acceleration voltages such as 500 keV, 1000 keV, and 1500 keV. Layer 8 can be formed.

However, if multiple implantations are performed, the larger number of crystal defects will occur as the surface is shallower from the back surface of the substrate. Since the activation of protons also depends on the amount of crystal defects, the concentration of the n-type layer may vary. Therefore, by forming a high concentration second n ⁺ -type buffer layer 9 formed by phosphorus implantation in the vicinity of the back surface, the depletion layer can be prevented from reaching the collector side when a voltage is applied, and the breakdown voltage decreases. An increase in leakage current can be suppressed.

In addition, phosphorus has a large atomic radius compared to protons, collisions of nuclei during injection may cause a large number of injection damage, and proton injection profiles may overlap proton injection profiles, which may affect proton donor formation. There is. Therefore, in the present embodiment, the position of the peak is set so that the concentration of the proton is higher than the concentration of phosphorus at the position of the peak concentration of the proton. Thereby, mutual interference can be prevented, and the first n ⁺ -type buffer layer 8 formed by proton activation can be made to have a desired concentration.

As described above, in the present embodiment, oscillation at turn-off of the IGBT can be prevented by the first n ⁺ -type buffer layer 8 formed by proton implantation and having a low concentration and a deep diffusion depth. In addition, the depletion layer can be stopped by the high concentration second n ⁺ -type buffer layer 9 into which phosphorus is injected to prevent an increase in the leak current.

Also, proton implantation is performed a plurality of times at different acceleration voltages using a general ion implantation apparatus for semiconductor manufacture to form the first n ⁺ -type buffer layer 8. Thereby, the first n ⁺ -type buffer layer 8 can be easily formed by proton injection even in a general semiconductor factory without using a cyclotron.

In addition, in a plurality of proton injections, it is preferable to lower the injection amount as the acceleration voltage becomes higher. This makes it possible to approximate the profile of the first n ⁺ -type buffer layer 8 formed by multiple proton injections to a Gaussian distribution.

  In addition, it is preferable that the injection amount of the profile with the highest acceleration voltage among the plurality of proton injections be the same as the injection amount of the profile with the second highest acceleration voltage. As a result, by forming a profile having a very gentle gradient, it is possible to gently stop the depletion layer spreading at the time of IGBT turn-off or at the time of recovery of the diode, and to prevent carriers from being swept rapidly and depleted. Can.

  In addition, the injection amount of phosphorus is lower than the injection amount of protons, activation of phosphorus is performed by laser annealing, and activation of protons is performed by furnace annealing at 350 ° C. to 450 ° C. By performing activation of phosphorus by laser annealing in this manner, the activation rate rises to about 70%. On the other hand, the activation rate of proton by furnace annealing is about 1%. Therefore, the peak concentration of phosphorus can be made sufficiently higher than the peak concentration of protons even if the injection amount of phosphorus is lower than the injection amount of protons. As a result, it is possible to carry out donorization of the proton injection region close to the phosphorus injection region while suppressing the influence of damage due to phosphorus injection.

Second Embodiment
FIG. 13 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present invention. This semiconductor device is a diode. A p-type anode layer 13 is formed on the surface of the n-type silicon substrate 1. An anode electrode 14 is formed on the surface of the n-type silicon substrate 1 and connected to the p-type anode layer 13. As in the first embodiment, the first and second n ⁺ -type buffer layers 8 and 9 are formed on the back surface of the n-type silicon substrate 1. A cathode electrode 15 is formed on the back surface of the n-type silicon substrate 1 and connected to the second n ⁺ -type buffer layer 9.

FIG. 14 is a diagram showing the back surface profile of the semiconductor device according to the second embodiment of the present invention. As in the first embodiment, the protons of the first n ⁺ -type buffer layer 8 have a plurality of peak concentrations different in depth from the back surface of the n-type silicon substrate 1. The position of the peak concentration of phosphorus in the second n ⁺ -type buffer layer 9 is shallower than the position of the peak concentration of protons in the first n ⁺ -type buffer layer 8 from the back surface of the n-type silicon substrate 1. The peak concentration of phosphorus is higher than the peak concentration of protons. At the position of the peak concentration of protons, the concentration of protons is higher than the concentration of phosphorus.

  15 to 20 are cross sectional views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 15, the surface structure of the diode is formed by a normal surface process. At this time, the wafer thickness is about 700 μm, which is almost the same as the bare wafer.

  Next, as shown in FIG. 16, the back surface side of the n-type silicon substrate 1 is polished to a desired thickness by grinder or wet etching. Next, as shown in FIG. 17, protons are implanted into the back surface of the n-type silicon substrate 1 a plurality of times at different acceleration voltages of 500 keV or more and 1.5 MeV or less using a general ion implantation apparatus for semiconductor manufacture. The range of protons is 6 μm at 500 keV and about 30 μm at 1500 keV.

Next, as shown in FIG. 18, activation of protons is performed by furnace annealing at 350 ° C. to 450 ° C. to form the first n ⁺ -type buffer layer 8. Next, as shown in FIG. 19, phosphorus is implanted into the shallow region of the back surface of the n-type silicon substrate 1 at an acceleration voltage of 1 MeV or less. Next, as shown in FIG. 20, activation of phosphorus is performed by laser annealing to form a second n ⁺ -type buffer layer 9.

  Thereafter, a cathode electrode 15 of Al / Ti / Ni / Au or AlSi / Ti / Ni / Au is formed on the back surface of the n-type silicon substrate 1 by sputtering. Finally, heat treatment at about 350 ° C. is performed to reduce the contact resistance by making ohmic contact between the cathode electrode 15 and the n-type silicon substrate 1. At this time, the heat treatment process can be reduced by one time by performing the heat treatment for activation of protons and performing the same process in the same process, so that the processing cost can be reduced.

Subsequently, the effect of the present embodiment will be described in comparison with a comparative example. FIG. 21 is a cross-sectional view showing a semiconductor device according to Comparative Example 2. As shown in FIG. FIG. 22 is a diagram showing the back surface profile of the semiconductor device according to Comparative Example 2. As shown in FIG. In Comparative Example 2, the n ⁺ -type buffer layer 12 is formed as deep as about 30 μm by proton injection using an accelerator such as a cyclotron or a van degraph.

On the other hand, in the present embodiment, as in the first embodiment, oscillation at the time of recovery of the diode is performed by the first n ⁺ -type buffer layer 8 formed by proton injection and having a deep diffusion depth. It can be prevented. In addition, the depletion layer can be stopped by the high concentration second n ⁺ -type buffer layer 9 into which phosphorus is injected to prevent an increase in the leak current. In addition, the first n ⁺ -type buffer layer 8 can be easily formed by proton injection even in a general semiconductor factory without using a cyclotron.

  The semiconductor substrate is not limited to one formed of silicon, and may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond. A power semiconductor element formed of such a wide band gap semiconductor can be miniaturized because of its high voltage resistance and allowable current density. By using this miniaturized device, it is possible to miniaturize a semiconductor module incorporating this device. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized, and the water cooling portion can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the semiconductor module can be highly efficient.

1 n-type silicon substrate (semiconductor substrate), 2 p-type base layer (p-type layer), 8 first n ⁺ -type buffer layer (first n-type buffer layer), 9 second n ⁺ -type buffer layer Second n-type buffer layer), 11 collector electrode (back surface electrode), 13 p-type anode layer (p-type layer), 15 cathode electrode (back surface electrode)

Claims (14)

A semiconductor substrate,
A p-type layer formed on the surface of the semiconductor substrate;
A semiconductor device comprising: first and second n-type buffer layers formed on the back surface of the semiconductor substrate;
The first n-type buffer layer has different depths from the back surface of the semiconductor substrate, and includes protons having a plurality of peak concentrations with a lower dose as the depth from the back surface of the semiconductor substrate is deeper,
The second n-type buffer layer contains phosphorus,
The position of the peak concentration of phosphorus is a position deeper than 1 μm and shallower than 6 μm from the back surface of the semiconductor substrate,
3. The semiconductor device according to claim 3, wherein the plurality of peak concentrations of the protons are present at a depth of 6 μm or more and 30 μm or less from the back surface of the semiconductor substrate. A semiconductor substrate,
A p-type layer formed on the surface of the semiconductor substrate;
A semiconductor device comprising: first and second n-type buffer layers formed on the back surface of the semiconductor substrate;
The first n-type buffer layer has different depths from the back surface of the semiconductor substrate, and includes protons having a plurality of peak concentrations with a lower dose as the depth from the back surface of the semiconductor substrate is deeper,
The second n-type buffer layer contains phosphorus,
The position of the peak concentration of phosphorus is a position deeper than 1 μm and shallower than 6 μm from the back surface of the semiconductor substrate,
The semiconductor device characterized in that the plurality of peak concentrations of the protons are located only at a depth of 6 μm or more and 30 μm or less from the back surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the peak concentration of the phosphorus is higher than the peak concentration of the protons, and the concentration of the protons is higher than the concentration of phosphorus at the peak concentration position of the protons.   The semiconductor device according to any one of claims 1 to 3, wherein an injection amount of the phosphorus is lower than an injection amount of the proton. Injecting protons from the back surface of the semiconductor substrate a plurality of times at different acceleration voltages;
Injecting phosphorus from the back side of the semiconductor substrate;
And activating the protons implanted into the semiconductor substrate after activating the phosphorus implanted into the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 5, wherein the phosphorus is activated by laser annealing, and the protons are activated by furnace annealing. Implanting boron from the back side of the semiconductor substrate;
7. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of activating the boron after activating the phosphorus and before activating the proton.   The method of manufacturing a semiconductor device according to any one of claims 5 to 7, wherein an injection amount of the phosphorus is lower than an injection amount of the proton.   The method of manufacturing a semiconductor device according to any one of claims 5 to 8, wherein in the step of injecting the proton a plurality of times, the amount of proton injection is reduced as the acceleration voltage becomes higher.   9. The method according to any one of claims 5 to 8, wherein in the step of injecting the proton a plurality of times, the injection amount of protons when the acceleration voltage is the highest is the same as the injection amount of protons next to the highest acceleration voltage. The manufacturing method of the semiconductor device as described in these.   The method for manufacturing a semiconductor device according to any one of claims 5 to 9, wherein an acceleration voltage of the proton injection is 500 keV or more and 1.5 MeV or less.   The method for manufacturing a semiconductor device according to any one of claims 5 to 10, wherein an acceleration voltage of the phosphorus injection is 1 MeV or less. The activation of the protons forms a first n-type buffer layer containing protons having a plurality of peak concentrations different in depth from the back surface of the semiconductor substrate,
The activation of the phosphorus forms a second n-type buffer layer containing phosphorus having a peak concentration at a position shallower from the back surface of the semiconductor substrate than the position of the peak concentration of the protons.
The peak concentration of the phosphorus is higher than the peak concentration of the protons,
The method of manufacturing a semiconductor device according to claim 5, wherein a concentration of the proton is higher than a concentration of the phosphorus at a position of the peak concentration of the proton.   13. The semiconductor device according to claim 12, wherein the plurality of peak concentrations of the protons contained in the first n-type buffer layer decrease as the distance from the back surface of the semiconductor substrate increases. Method.

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