RU2321167C2 - Method for compensating discontinuous jumps of supporting signal of phase-locked loop frequency control - Google Patents

Abstract

FIELD: radio engineering, possible use in systems for phase-locked loop frequency control.

SUBSTANCE: method for compensating discontinuous jumps of phase signal of phase-locked loop frequency control consists of two stages: measurement of the moment of phase jump and estimation of value of the jump. The moment of phase jump is determined by threshold comparison of current change (increment) of phase difference signal to corresponding (positive or negative) local average change (increment) of phase difference signal. Value of the jump is estimated by selection of one of two values equal to difference of increment of phase difference signal in the moment of leap detection and two possible local average increments of phase difference signal (positive one or negative one) at that moment. The value which is closest to the difference between local average (filtered) values of phase difference signal before and after the jump is considered correct.

EFFECT: compensation of phase jumps of difference signal.

3 cl, 6 dwg

Description

The invention relates to phase-locked loop systems (PLL), in particular, to methods for estimating the phase difference with an abrupt reference signal.

Currently, for example, the use of an E1 / T1 signal is common, which is characterized by phenomena such as bit alignment and pointer alignment, which compensates for phase jumps and allows you to control the frequency of the internal controlled oscillator even in the absence of other continuous reference signals.

An E1 / T1 signal is a European system signal transmitted at a speed of 2.048 Mbit / s, carrying 30 telephone channels in 32 time slots, including frame alignment and signal information (uneven quantization of analog voice signals is accepted), described in Stefano Bregni's book "Synchronization of Digital Telecommunications Networks ", Copyright 2002 John Wiley & Sons, Ltd. ISBNs: 0-471-61550-1 (Hardback); 0-470-84588-0 (Electronic) [1].

Phase (or frequency) frequency locking is widely used in telecommunications to synchronize a controlled oscillator, whose signal serves as the PLL output, with a reference oscillator. Typically, the PLL contains a device for determining the phase difference (phase / frequency discriminator, phase comparator, time error counter). The phase / frequency discriminator generates a control signal characterizing the phase difference of the signals of the reference oscillator and the controlled oscillator. In turn, the controlled generator generates a signal whose frequency is determined by the value of the control voltage. In order to ensure PLL noise immunity, a low-pass filter (LPF) or other smoothing device is used. In addition, if the frequency of the controlled generator spontaneously varies, for example, due to changes in ambient temperature or aging, an integrator is also used in the PLL. When using digital devices, a digital-to-analog converter is used in the PLL loop. Finally, if the nominal frequencies of the reference oscillator and the controlled oscillator are different, in particular, if the reference frequency is lower, a frequency divider is included in the PLL to ensure approximate equality of the compared signals (see Pervachev SV Radioautomatics: Textbook for universities. - M .: Radio and communications, 1982. - 296 p., Ill. [2]).

The above synchronization method assumes a continuous reference signal having long-term frequency stability better than a controlled oscillator. However, for remote terminals, such as base stations of cellular communication systems, repeaters, etc., it is not always possible to find a suitable source of a reference signal. This problem was resolved to some extent with the advent of global GPS / GLONASS satellite systems broadcasting a highly stable radio signal. However, the satellite signal is not received everywhere and requires the use of an additional receiver. An alternative reference signal can be a frame synchronization signal as part of the information transmitted over the E1 / T1 trunk wire lines. However, such communication lines are characterized by the presence of phase jitter and phase jumps of large magnitude. Therefore, for normal PLL operation in this case, it is necessary to compensate for phase jumps.

The compensation for phase jumps is described in US patent No. 4019143 [3], in which the clock output signal is synchronized in phase with the main clock generator. In case of malfunction of the main generator, the standby control circuit changes the phase of the clock output signal until it coincides with the phase of the signal of the standby clock generator. The disadvantage of this invention is the need for a second reference signal, in particular from a standby generator. In its absence, the PLL will not function.

US Pat. No. 6,784,706 [4] describes a method of bringing a PLL, which incorporates a phase discriminator, a controlled generator, and an integrator, into a capture state after exposure to a phase or frequency jump in the discriminator output signal. This method involves storing the integrator output signal before a phase or frequency jump occurs, determining the moment of this jump and then restoring the integrator output signal from memory immediately to the end field of the jump or after some time, which allows reducing PLL overshoot as a result. The disadvantage of this invention is that it is not able to compensate for the effect of phase jumps of long duration or other non-pulsed form, for example step. In this case, the integrator output value recovered from the memory after the end of the jump may not be adequate to the discriminator output signal, which will bring the PLL to the deregulated state.

Closest to the proposed solution in technical essence is the solution described in US patent No. 5426672 [5].

The method of compensating for jumps in the reference signal of the phase-locked loop, described in the prototype [5], is as follows:

- compare the phases of the reference information sequence and the generated sequence of clock pulses, receiving the original phase-difference signal,

- service information is extracted from the information sequence, based on which the moment and magnitude of the phase jump are determined, and a compensation signal is generated,

- the compensation signal is summed with the original phase-difference signal, forming the output phase-difference signal.

The compensation process in the prototype [5] occurs in the phase jump compensator located between the output of the phase discriminator and the input of a controlled generator. In the absence of a phase jump, the control signal does not change the phase jump compensator, therefore, the output signal of the phase discriminator also remains unchanged. When determining the jump based on the service information, a compensation compensation signal is supplied, which corrects the discriminator output signal. With a positive phase jump, the corresponding value is subtracted from the output signal of the phase discriminator, otherwise the corresponding value is added.

However, when service information is not available, the compensation of the jump becomes problematic and phase-locked loop due to these jumps stops working.

The problem that the invention solves: compensation of phase jumps of the reference signal in order to ensure normal operation of the phase locked loop.

To solve this problem, in the method of compensating for jumps in the reference signal of the phase-locked loop, which consists in comparing the phases of the reference and generated sequences of clock pulses, obtaining the initial phase-difference signal, the following operations are introduced according to the invention:

filter the initial phase-difference signal, remember the original and filtered phase-difference signal,

determine the increment of the current value of the phase difference signal compared to the previous value,

remember the increment of the current value of the phase difference signal,

separately filter the received positive and negative increments of the current value of the phase-difference signal,

remember filtered increments of the current value of the phase difference signal,

comparing the current positive or negative increment value of the phase difference signal with the corresponding filtered increment value of the phase difference signal,

register a phase jump if the current positive increment of the phase difference signal is higher than the positive filtered value of the phase difference signal by the value of the specified threshold or the current negative increment of the phase difference signal is lower than the negative filtered value of the phase difference signal by the value of the specified threshold,

if the current phase jump is recorded, the value of the previous phase jump is estimated using the stored value of the increment of the input phase difference signal at the time of the previous jump, its current filtered value, as well as the filtered positive and negative increments of the phase difference signal at the time of the previous jump,

summarize the value of the obtained jump estimate with previous estimates,

the output corrected value of the phase difference signal is obtained by subtracting the total value of the jump estimate from the stored filtered phase difference signal.

The jump value is estimated by choosing one of two values equal to the increment of the phase difference signal at the moment of determining the jump and two possible filtered increments of the phase difference signal (positive or negative) at this moment.

The choice is made in favor of that of two values equal to the increment of the phase-difference signal at the moment of determining the jump and two possible filtered increments of the phase-difference signal (positive or negative) at that moment which is closer in absolute value to the difference in the values of the filtered phase-difference signal before and after the phase jump.

A comparative analysis of the method and device for compensating the phase jumps of the reference signal in the phase locked loop with the prototype shows that the present invention is significantly different from the known solutions, as it allows the compensation of the phase jumps of the reference signal and the normal operation of digital phase locked loop.

A comparative analysis of the claimed solutions with other technical solutions in this technical field did not allow to identify the features claimed in the distinctive parts of the claims. Therefore, the claimed solutions meet the criteria of "novelty", "inventive step", "industrial applicability".

Graphic materials used in the application materials:

Figure 1 is a structural diagram of the implementation of phase-locked loop.

Figure 2 is a structural diagram of the implementation of the phase jump compensator.

Figure 3 is an example of a phase jump estimation block.

Figure 4 - the time dependence of the output signal and the frequency error from time to time.

Figure 5 - dependence of the measured time mismatch × 109 (line A) and the estimated time mismatch (line B) on time in seconds of the traditional PLL.

6 is a dependence of the measured time mismatch × 109 (line A) and the estimated time mismatch (line B) on time in seconds when using the inventive phase jump compensator.

The proposed method of compensating for phase jumps of the reference signal of the frequency control is as follows:

comparing the phases of the reference and generated sequences of clock pulses, receiving the initial phase-difference signal,

filter the initial phase-difference signal, remember the original and filtered phase-difference signal,

determine the increment of the current value of the phase difference signal compared to the previous value,

remember the increment of the current value of the phase difference signal,

separately filter the received positive and negative increments of the current value of the phase-difference signal,

remember filtered increments of the current value of the phase difference signal,

comparing the current positive or negative increment value of the phase difference signal with the corresponding filtered increment value of the phase difference signal,

register a phase jump if the current positive increment of the phase difference signal is higher than the positive filtered value of the phase difference signal by the value of the specified threshold or the current negative increment of the phase difference signal is lower than the negative filtered value of the phase difference signal by the value of the specified threshold,

if the current phase jump is recorded, the value of the previous phase jump is estimated using the stored value of the increment of the input phase difference signal at the time of the previous jump, its current filtered value, as well as the filtered positive and negative increments of the phase difference signal at the time of the previous jump,

summarize the value of the obtained jump estimate with previous estimates,

the output corrected value of the phase difference signal is obtained by subtracting the total value of the jump estimate from the stored filtered phase difference signal.

The jump value is estimated by choosing one of two values equal to the increment of the phase difference signal at the moment of determining the jump and two possible filtered increments of the phase difference signal (positive or negative) at this moment.

The choice is made in favor of that of two values equal to the increment of the phase-difference signal at the moment of determining the jump and two possible filtered increments of the phase-difference signal (positive or negative) at that moment which is closer in absolute value to the difference in the values of the filtered phase-difference signal before and after the phase jump.

A phase locked loop can be represented as shown in FIG. This device contains a serially connected reference generator 1, a phase discriminator 2, a phase jump compensator 3, a low-pass filter 4, an integrator 8, a digital-to-analog converter 7, a controlled generator 6, a divider 5, the output of which is connected to the second input of the phase discriminator 2.

The phase (or frequency) discriminator 2 is used to determine the phase difference, which generates control signals characterizing the phase difference of the signals of the reference generator 1 and the controlled generator 6. In turn, the controlled generator 6 generates a signal whose frequency is determined by the value of the control voltage. In order to ensure the PLL noise immunity, a low-pass filter 4 or other smoothing device is used. If the frequency of the controlled oscillator 6 spontaneously varies, for example, due to changes in ambient temperature or aging, then an integrator 8 is used to stabilize it. When using digital devices, a digital-analog converter 7 is used in the PLL loop. If the frequency of the reference signal is lower than the frequency of the controlled generator 6, the PLL introduce a frequency divider 5, which serves to ensure approximate equality of frequencies of the compared signals of the reference generator 1 and the controlled generator 6.

A necessary condition for obtaining the PLL / CHAP characteristics, as described above, is the presence of an appropriate reference signal, which must be stable for a long time. For independent telecommunications entities, such as a base station, base station controller, a suitable reference signal is the GPS receiver signal. However, such a signal is not always available due to violations of the GPS receiver, the lack of satellites in the line of sight, etc. As a result, a backup mode of operation is provided, which ensures synchronization with the network signal.

The compensator 3 jumps of the phase of the reference signal estimates the time instants and values of the jumps based on the analysis of the phase-difference signal and then compensates for the obtained value. The phase jumps occur, for example, when the reference signal consists of pulses of the beginning of the frame of the information flow E1 / T1, where the jumps are caused by the phenomena of pointer alignment and bit alignment. The result is a corrected phase difference signal without jumps, suitable for regulating the internal oscillator by means of a phase / frequency self-tuning algorithm (PLL / CHAP).

The inventive method consists of two stages: determining the moment of the phase jump and estimating the value of this jump.

The moment of the phase jump is determined by threshold comparison of the current change (increment) of the phase difference signal with the corresponding (positive or negative) local average change in the increment of the phase difference signal.

The jump value is estimated by choosing one of two values equal to the difference in the increment of the phase-difference signal at the moment of determining the jump and two possible local average increments of the phase-difference signal (positive or negative) at that moment. The closest value to the difference between the local average (filtered) values of the phase difference signal before and after the jump is considered to be true.

Figure 2 shows the structural diagram of the compensator 3 phase jumps according to the invention. The phase jump compensator 3 comprises a differentiator 9, a switch 10, a first comparator 11, a second comparator 12, a third comparator 15, a first low pass filter 13, a second low pass filter 14, a third low pass filter 16, and a phase jump estimator 17.

The input of the differentiator 9 is the input of the compensator 3 of the phase jump, as well as the input of the signal of the temporary error (BP). The input of the phase jump compensator 3 is also connected to the first input of the third low-pass filter 16. The output of the differentiator 9 is connected directly to the first input of the switch 10, to the second input of the switch 10 through the first comparator 11 and to the first input of the phase jump estimation unit 17. The first output of the switch 10 is connected to the first input of the second comparator 12 and the first input of the first low-pass filter 13. The second output of the switch 10 is connected to the first input of the third comparator 15 and the first input of the second low-pass filter 14. The second input of the phase jump estimation unit 17 is connected to the output of the third low-pass filter 16, which is the output of the filtered initial phase-difference signal. The first output of the phase jump estimator 17 is the output of a low-pass filter reset signal and is connected to the second inputs of the first 13, second 14, and third 16 low-pass filters. The output of the second low-pass filter 14 is the output of the negative filtered increments of the phase difference signal and is connected to the second input of the third comparator 15 and the third input of the phase jump estimation unit 17. The output of the first lowpass filter 13 is the output of the positive filtered increments of the phase difference signal and is connected to the second input of the second comparator 12 and the fourth input of the phase jump estimator 17. The fifth input of the phase jump estimation unit 17 is the input of the initial setup and is connected to the output of the second 12 and third 15 comparators. The second output of the phase jump estimation unit 17 is the output of the phase jump compensator 3, as well as the output of the output value of the phase difference signal.

In the phase discriminator 2, the phases of the reference and the generated sequence of clock pulses are compared, obtaining the initial phase-difference signal. This initial phase-difference signal is fed to the input of the third low-pass filter 16, where it is filtered, then it is fed to the first input of the phase jump estimation unit 17, where it is stored. In the differentiator 9, the increment of the phase difference signal is determined, which is then compared with the zero threshold of the first comparator 11 and stored in the phase jump estimation unit 17. Through the switch 10, the positive increments of the phase difference signal are fed to the first low-pass filter 13, where they are filtered, and then the positive filtered increments of the phase difference signal are fed to the fourth input of the phase jump estimator 17 for storage. Negative increments of the phase-difference signal through the switch 10 go to the second low-pass filter 14, where they are filtered, then they go to the third input of the block 17, in which the negative filtered increments of the phase-difference signal are also stored.

In the comparator 12, the positive values of the increment of the phase-difference signal from the output of the differentiator 9 are compared with the filtered increment of the phase-difference signal from the output of the first low-pass filter 13. If they are larger than the specified threshold, it is believed that a phase jump has occurred. In the comparator 15, the negative values of the increment of the phase-difference signal from the output of the differentiator 9 are compared with the negative filtered increment of the phase-difference signal from the output of the second low-pass filter 14. If they are less than the specified threshold, it is also believed that a phase jump has occurred. In the case of recording the current phase jump, the phase jump estimation block 17 estimates the previous jump using the output signals of the first 13, second 14, and third 16 low-pass filters and differentiator 9, which were stored at that time. In the phase jump estimation block 17, the estimate of the previous jump is summed with previously obtained estimates, the output value of the phase difference signal is obtained by subtracting the total value of the jump estimate from the stored filtered phase difference signal.

Figure 3 presents a variant of the structural diagram of the block 17 evaluation of the phase jump. This block works as follows. Each time a new phase jump is recorded, the phase jump value estimator estimates the previous jump using the increment of the phase difference signal at the time of the previously determined phase jump, which was stored in the memory unit 20, filtered positive and negative increments of the phase difference signal at the time of the previously determined phase jump, which were stored in the memory unit 18 and the memory unit 19, as well as the current filtered increment of the phase difference signal and the filter Rowan increment signal phase difference at the time of the phase jump, which was stored in the memory unit 21. The output values from the memory blocks 18 and 20 are subtracted from each other in the subtractor 22, and the output values from the outputs of the blocks 19 and 20 are subtracted from each other in the subtractor 23. The input and output values of the memory block 21 are subtracted from the subtractor 24. The result obtained from the output of the subtractor 24 is subtracted from the outputs of subtractor 22 and subtractor 23 in subtractor 25 and subtractor 26, respectively. Then their absolute values are compared in the comparator 27. If the output absolute value of the subtractor 25 is less, then the signal of the integrator 29 is changed to the value of the output signal of the subtractor 22 using the selector 28. Otherwise, the signal of the integrator 29 is changed to the value of the output of the subtractor 23. After updating the output the signal of the subtractor 30, the contents of the memory units 18, 19, 20, 21 are also updated.

Verification of the characteristics of the invention was carried out by simulation. As an example, a PLL was used, using the pulses of the beginning of the E1 / T1 signal frame following with a frequency of 8 kHz as a reference signal, as well as a time misalignment detector as a phase discriminator and a tunable 10 MHz crystal oscillator as a controlled oscillator. The aging of the quartz generator was 10 ^-10 / day, and the temperature deviation in the range of 0-70 ° C was ± 10 ^-10 . An abrupt reference signal similar to E1 / T1 was considered, including a phase jump of 2 μs every 60 seconds. It should be noted that traditional PLL / CAP algorithms without phase jump compensation do not work in these conditions. However, when using the claimed invention, the characteristics of the PLL / CHAP correspond to the graph below, figure 4. In Fig.5 PLL / CAP is not used. This graph shows the observed and estimated (after compensating for the jumps) temporary mismatch.

Figure 4 presents the dependence of the absolute temporal mismatch of the output signal in ns (line A) and the frequency error in Hz (line B) on time in seconds during the day. The accuracy of the temporal mismatch detector is ± 2.5 ns, and the standard deviation (RMS) of the temporary jitter of the front of the crystal oscillator is 1.5 ps.

5 and 6. PLL / CHAP is not used.

Figure 5 presents the dependence of the measured time mismatch × 109 (line A) and the estimated time mismatch (line B) on time in seconds of the traditional PLL. Figure 6 shows the dependence of the measured time mismatch × 109 (line A) and the estimated time mismatch (line B) on time in seconds when using the inventive phase jump compensator.

The simulation results show that the method of compensating for the phase jumps of the PLL reference signal proposed by the invention almost completely compensates for the phase jumps of the reference signal and allows the PLL to operate in normal mode.

Claims (3)

1. The method of compensating for jumps in the reference signal of the phase-locked loop, which consists in comparing the phases of the reference and generated sequences of clock pulses, obtaining the initial phase-difference signal, and the adjustment signal of the controlled generator is a corrected phase-difference signal, characterized in that the initial phase-difference signal is filtered, stored the initial and filtered phase difference signals determine the increment of the current value of the phase difference signal compared to the previous value, remember the increment of the current value of the phase-difference signal, separately filter the received positive and negative increments of the current value of the phase-difference signal, remember the filtered increments of the current value of the phase-difference signal, remember it at the time of the jump, compare the current positive or negative value of the increment of the phase-difference signal with the corresponding filtered increment of the phase-difference signal signal, register a phase jump if the current a positive increment of the phase difference signal above the positive filtered value of the phase difference signal by the value of the specified threshold or the current negative increment of the phase difference signal below the negative filtered value of the phase difference signal by the value of the specified threshold; if the current phase jump is recorded, the value of the previous phase jump is estimated using the stored increment value of the input phase difference signal at the time of the previous jump, its current filtered The values and the filtered positive and negative phase difference signal increments at the time of the previous jump summed value obtained by the evaluation of the jump to previous estimates obtained output value corrected phase difference signal by subtracting the total value of estimation of jumps from the stored filtered phase difference signal. 2. The method according to claim 1, characterized in that the jump value is estimated by selecting one of two values equal to the increment of the phase difference signal at the time of determining the jump and two possible filtered increments of the phase difference signal (positive or negative) at this moment. 3. The method according to claim 2, characterized in that the choice is made in favor of one of two values equal to the increment of the phase-difference signal at the time of determining the jump and two possible filtered increments of the phase-difference signal (positive or negative) at that moment, which is closer in absolute value to the difference in the values of the filtered phase difference signal before and after the phase jump.

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