RU2304840C1 - Method and device for high-reliability data transmission and reception in mobile communication system supporting burst data transfer - Google Patents

Abstract

FIELD: mobile communication systems for burst data transfer including transfer of control data for hybrid automatic retransmission request.

SUBSTANCE: absolute six-bit grant pointing to admissible maximal data transfer speed is generated for transmitting burst data of ascending communication line and sixteen-bit control of cyclic redundancy code referred to user equipment identifier is conducted by combining cyclic redundancy code control with user equipment identifier. Cyclic redundancy code referred to user equipment identifier and eight tail bits are added to six-bit absolute grant and summed-up bits are encoded at code speed of 1/3. Nineteen resultant encoded bits are coordinated with respect to speed in compliance with predetermined combination for coordinating speed of (1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75, 7780, 83, 8485, 87, 88, 90) and transferred to user equipment.

EFFECT: enhanced reliability of control information transfer.

16 cl, 5 dwg

Description

Description

FIELD OF THE INVENTION

The present invention generally relates to a mobile communication system supporting packet data transmission. In particular, the present invention relates to a method and apparatus for transmitting control information necessary for a hybrid automatic retransmission request (HARQ).

State of the art

Universal Mobile Communications System (UMTS), which is a 3rd generation mobile communications system using WCDMA based on the European Global System for Mobile Communications (GSM) and General Purpose Packet Radio Communication (GPRS) provides mobile subscribers or computer users with unified services for text transmission on a packet basis, digitized speech, as well as video and multimedia data at a speed equal to or higher than 2 Mbps depending on their location in the world.

In particular, the UMTS system uses a transport channel called an enhanced uplink dedicated channel (E-DCH or EUDCH) to further increase the efficiency of uplink packet transmission from user equipment (UE) to Node B (with the option of being replaced with a base station). To provide more stable high-speed data transmission on the E-DCH channel, adaptive modulation and coding (AMC), hybrid automatic retransmission request (HARQ), shortened transmission interval (TTI), and scheduling under the control of Node B were introduced.

AMC is a method for determining a modulation and coding scheme (MCS) adaptively corresponding to a channel state between a Node B and a UE. In accordance with existing modulation schemes and coding schemes, a plurality of MCS levels can be determined. Adaptive selection of the MCS level according to the state of the channel increases resource efficiency.

HARQ is a packet retransmission scheme for retransmission of a packet in order to correct errors in the originally transmitted packet. Shortened TTI is a way to reduce time delay due to retransmission, which improves system throughput by using a shorter TTI interval shorter than the shortest 10 ms TTI provided by 3GPP Re15. Currently, a value of 2 ms is considered as the length for such a shortened TTI.

Scheduling under the control of Node B is a scheme in which Node B determines whether to allow transmission on the E-DCH for a given UE, and if the transmission is enabled, at what permissible maximum speed can the data be transmitted, after which Node B transmits information to the UE about a certain data rate in the form of a “planning grant”, and the UE, based on the planning grant, determines the available data rate on the E-DCH.

Planning under the control of node B is carried out in such a way that the noise rise or excess thermal noise (RoT) measurements for node B do not exceed the reference RoT to increase the overall system efficiency by, for example, providing low data rates to remote UEs and high transmission rates data to nearby UEs. RoT represents the uplink radio resources used by the Node B, which are defined as

RoT = Io / No, (1)

where Io denotes the spectral power density over the total reception band, that is, the total value of the uplink signals received at node B, and No denotes the spectral power density of thermal noise for node B. Thus, the allowable maximum RoT represents the total radio resources of the uplink available to node B.

Total RoT is expressed as the sum of inter-cell interference, voice traffic, and E-DCH traffic. When scheduling under the control of Node B, simultaneous transmission of packets from multiple UEs with high data rates is prevented, as a result of which the total RoT is maintained equal to or lower than the reference RoT, which ensures reception efficiency.

Figure 1 presents a diagram illustrating a typical signal flow when transmitting and receiving data on the channel E-DCH. In the case shown in FIG. 1, the UE transmits uplink data on the E-DCH, and the Node B performs scheduling for this UE under the control of the Node B.

Referring to FIG. 1, where the Node B and the UE equipment install the E-DCH channel in step 102. Step 102 includes transmitting messages on dedicated transport channels. In step 104, the UE transmits the scheduling information to the node B. The scheduling information may include information about the state of the uplink channel, including the transmit power and power headroom of the UE, as well as the amount of buffered data to be transmitted to the node B. In step 106, the node B monitors scheduling information from a plurality of UEs for scheduling uplink data transmission for individual UEs. When node B decides to authorize uplink packet transmission from the UE, it transmits a scheduling grant, including assignment information, to the UE in step 108. The planning grant indicates an increase / retention / decrease of the allowable maximum data rate or the allowable maximum data rate and allowable transmission time parameters. In step 110, the UE determines the TF (transport format) of the E-DCH (E-TF) channel based on a scheduling grant. Then, in step 112, the UE transmits the E-TF information to the Node B, as well as the uplink packet data on the E-DCH in step 114. The Node B in step 116 determines whether there are errors in the E-TF and packet information uplink data. If there are errors in either the TF information or the uplink packet data, the Node B transmits a negative acknowledgment (NACK) signal to the UE via the acknowledgment / negative acknowledgment (ACK / NACK) channel, while in the absence of both in another error, the Node B transmits a confirmation signal (ACK) via ACK / NACK to the UE in step 118. In the latter case, the packet data transmission is completed, and the UE transmits new packet data on the E-DCH to the Node B. On the other hand, in the first case, the UE transmits the same packet data on the E-DCH to the Node B.

For effective scheduling under the above conditions, the Node B receives from the UE scheduling information about the buffer load and power status. Based on the scheduling information, the Node B distributes the low data rates to the remote UEs, the UEs with poor channel conditions and the UEs with data with a low service class, and distributes the high data rates to the nearby UEs, the UEs with good channel conditions, and the UEs with the data with high class service. In this context, there is a need to develop a method for transmitting and receiving a planning grant, which may be an absolute grant (AG) indicating the absolute value of the allowable maximum data rate for the UE, or a relative grant (RG) indicating the increase / retention / decrease of the previous allowable maximum transfer rate.

SUMMARY OF THE INVENTION

One aspect of the present invention is associated with at least the above problems and / or disadvantages and provides at least the advantages described below. Accordingly, one aspect of the present invention relates to the provision of a method and apparatus for improving the reliability of transmitting control information the size of a small block, such as an E-DCH scheduling grant.

The present invention also provides a method and apparatus for transmitting information with a higher reliability requirement, such as an absolute grant (AG) indicating an allowable maximum data rate for UE equipment.

The above exemplary objectives are achieved by providing a method and apparatus for transmitting control information the size of a small block with high reliability in a mobile communication system that supports the transmission of packet data uplink communication.

According to one aspect of an exemplary embodiment of the present invention, in a method for transmitting control information related to the transmission of uplink packet data in a mobile communication system, a 16-bit CRC associated with a UE-ID is created by combining a CRC created to detect errors in the control information, with a user equipment identifier (UE-ID), for identifying the UE for receiving control information. 90 coded bits are created by adding a CRC associated with the UE-ID and 8 tail bits to 6-bit control information and encoding the summed bits with a code rate of 1/3. A 60-bit rate-matched block is created by matching the encoded bits in accordance with a predetermined combination to match the rate representing the positions of the bits to be punctured among the encoded bits. The speed-matched block is transmitted to the UE equipment. The combination for speed matching is {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}.

According to another aspect of an exemplary embodiment of the present invention, in a control information transmission apparatus for transmitting uplink packet data in a mobile communication system, a CRC generator associated with a UE-ID creates a 16-bit CRC associated with a UE-ID by combining a CRC created to detect errors in the control information, with a UE-ID for identifying the UE for receiving control information. The channel encoder creates 90 encoded bits by adding a CRC associated with the UE-ID and 8 tail bits to the 6-bit control information and encoding the summed bits with a code rate of 1/3. The rate matching device creates a 60-bit rate-matched block by matching the encoded bit rate in accordance with a predetermined combination to match the rate representing the position of the bits to be punctured among the encoded bits. The physical channel mapper transmits a rate matched block to the UE. The combination for speed matching is {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}.

According to a further aspect of an exemplary embodiment of the present invention, in a method for receiving control information related to the transmission of uplink packet data in a mobile communication system, a 60-bit rate-matched block is extracted from a signal received from node B. 90 coded bits are generated by back-matching the speed of a speed-matched block in accordance with a predetermined combination to match a speed representing the positions of the bits to be punctured. 6-bit control information and a 16-bit CRC associated with the UE-ID are obtained by decoding the encoded bits at a code rate of 1/3. The control information is output by checking the CRC associated with the UE-ID. The combination for speed matching is {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}.

According to another aspect of an exemplary embodiment of the present invention, in a device for receiving control information related to the transmission of uplink packet data in a mobile communication system, the physical channel demapper extracts from the signal received from the node B a 60-bit speed-matched block. The rate matching device generates 90 coded bits by back-matching the speed-matched block in accordance with a predetermined combination for speed matching representing the positions of the bits to be punctured. The channel decoder creates 6-bit control information and a 16-bit CRC associated with the UE-ID by decoding the encoded bits at a code rate of 1/3. The CRC verification device outputs control information by checking the CRC associated with the UE-ID. The combination for speed matching is {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}.

Brief Description of the Drawings

The above and other exemplary objectives, features and advantages of the present invention will become more apparent from the following detailed description together with the accompanying drawings, in which:

Figure 1 is a diagram illustrating a stream of typical signals when transmitting and receiving data on the channel E-DCH;

Figa and 2B - convolutional encoder with a speed of 1/3 and a convolutional encoder with a speed of 1/2, respectively;

Figure 3 is a block diagram of a transmitter of node B according to a preferred embodiment of the present invention;

4 is a block diagram of a receiver of a UE according to a preferred embodiment of the present invention.

It should be clear that in all the drawings, the same reference position refers to the same elements, features and structures.

Detailed Description of Exemplary Embodiments

The issues discussed in the description, such as a detailed design and elements, are proposed in order to facilitate a comprehensive understanding of embodiments of the invention. Accordingly, it will be apparent to those skilled in the art that various changes and modifications of the embodiments described herein may be proposed within the scope and spirit of the invention. We also note that for clarity and brevity, a description of well-known functions and constructions is omitted here.

The following describes some exemplary embodiments of the present invention in the context of an E-DCH channel of a UMTS system. The physical channel, called the E-DCH Absolute Grant Channel (E-AGCH), transfers the AG grant from Node B to the UE. The grant AG is determined by the scheduler of the Node B in accordance with the scheduling information received from the UE and the uplink radio resources available to the Node B.

The AG grant may include an allowable maximum data rate indicating the maximum amount of uplink radio resources available to the UE, or an equivalent power offset for an allowable maximum data rate, an AG duration indicator indicating how long the AG remains valid, and a validity indicator AG for the process, indicating whether the AG is valid for one particular HARQ process or the entire HARQ process. The power offset is defined as the maximum power ratio of the Enhanced Dedicated Physical Data Channel (E-DPDCH) through which the E-DCH is displayed to the reference physical channel with controlled power — the dedicated physical control channel (DPCCH). Here we consider the allowable data transfer rate or power offset from 4 to 8 bits, the 1-bit AG duration indicator and the 1-bit AG validity indicator for the process. The E-AGCH also requires a UE-ID to identify the UE on the common channel and a cyclic redundancy check (CRC) code to detect errors in the AG. The UE-ID and CRC are each 16 bits and are bit-wise modulo 2. They are contained together with the AG in the control information delivered via the E-AGCH as a 16-bit CRC masked by the UE-ID.

Thus, the E-AGCH control information may be a total of 21 to 16 bits in length. This control information, in particular the grant AG, is intended for the efficient distribution of radio resources, and therefore high reliability is required for its transmission. Typically, in communication systems, channel coding is used to transmit / receive data with high reliability. Channel coding allows the receiver to correct transmission errors by entering redundant information into the transmitted data.

As a channel coding method for highly reliable transmission and reception on the E-AGCH channel, a convolutional code with a code restriction length of 9 and a code rate of 1/3 defined in 3GPP standards can be used. Control information from 21 to 26 bits in length, to be delivered via the E-AGCH, is attached to 8 tail bits, and then encoded to obtain from 87 to 102 encoded bits ((21 + 8) x3 = 87, (26 + 8) x3 = 102) by convolutional coding at a rate of 1/3.

FIG. 2A shows a convolutional encoder 200 with a code constraint length of 9 and a code rate of 1/3 defined in 3GPP standards.

2A, where a convolutional encoder 200 includes eight consecutive shift registers 202, 204, 206, 208, 210, 212, 214 and 216, as well as a plurality of adders 202b, 202c, 204a, 204c, 206a, 206b, 208b , 210a, 210c, 212a, 214a, 214b, 216a, 216b and 216c for receiving input information bits or output bits of the shift registers 202 to 216. The input information, including eight tail bits, sequentially passes through the shift registers 202 to 216 starting from the first bit, as a result of which coded bits are created in the order output0, output1, output2, output0, output1, output2, ...

The channel-encoded control information is delivered at 2-millisecond TTI intervals of the E-AGCH. If an expansion coefficient (SF) of 256 and quadrature phase shift keying (QPSK) are used for the E-AGCH, then only 60 bits can be transmitted in the 2-millisecond TTI interval. Thus, from the encoded control information of the E-AGCH channel, 27 (= 87-60) to 42 (= 102-60) bits are cracked. For gouging, you can use speed matching. The rate matching brings the number of channel encoded bits into correspondence with the number of bits transmitted over the physical channel by puncturing or repeating the bits at predetermined positions in the channel encoded bit stream of one block. In the general case, when matching the speed, the positions of the punctured or repeated bits are equidistant.

However, rate matching for small-volume control information, such as 20 bits delivered over the E-AGCH, makes it difficult to achieve the optimal frequency of occurrence of erroneous blocks (BLER). If such a block with a relatively small number of bits is convolutionally encoded and rate matched, then the beginning and end of this block is characterized by low error bit rates (BER), while in the middle part there is a high BER. Therefore, the BLER of the block increases, and the reliability of the E-AGCH channel decreases. The presence of at least one erroneous bit in one block leads to the appearance of BLER. If a particular part of one block has a low BER, but the rest has a high BER, this leads to a decrease in efficiency, and not to an increase in efficiency based on BLER.

Highly reliable (i.e., few errors) transmission and reception of E-AGCH control information is achieved by reducing BLER. In addition, standard rate matching results in large BER deviations at each bit position of the block.

In this context, it is assumed that exemplary embodiments of the present invention provide rate matching that minimizes BLER and allows transmission of control information the size of a small block. To this end, combinations for rate matching are proposed that minimize the change in BER at each bit position of one control information block and thereby reduce the BLER for the E-AGCH, which delivers small volume control information of the order of 20 bits after convolutional channel coding.

Combinations for rate matching, which can increase BLER efficiency for control information delivered over the E-AGCH, may be implemented in specific exemplary embodiments of the present invention. Exemplary options one through six relate to example combinations for rate matching and corresponding transmission and reception for a 7-bit grant AG, 8-bit AG, 9-bit AG, 10-bit AG, and 5-bit AG, respectively.

Example 1

As an example implementation of the present invention, a combination is proposed for rate matching for a 6-bit AG grant. The AG grant, for example, includes a 4-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or a 4-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 5-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 5-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of six bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 22-bit control information with a 6-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is a 90-bit encoded stream. 30 bits are punctured from the 90-bit channel encoded block for transmission in the 2-millisecond TTI interval of the E-AGCH channel, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. The following combinations for speed matching are available for use.

Combination for speed matching =

{1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75, 77, 80, 83 , 84, 85, 87, 88, 90},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 18, 24, 48, 51, 54, 57, 60, 63, 66, 75, 78, 80, 81, 83 , 84, 86, 87, 89, 90},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 18, 21, 24, 57, 60, 66, 69, 75, 78, 80, 81, 83, 84, 85 , 86, 87, 88, 89, 90},

{1, 2, 3, 5, 6, 7, 8, 12, 14, 15, 18, 23, 25, 48, 50, 52, 57, 59, 61, 71, 75, 77, 79, 80, 82 , 84, 86, 87, 88, 89},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 24, 42, 48, 54, 57, 60, 66, 75, 78, 80, 81, 83, 84, 85 , 86, 87, 88, 89, 90},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 18, 24, 48, 50, 52, 57, 59, 61, 66, 75, 78, 80, 81, 83 , 84, 86, 87, 89, 90},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 24, 42, 54, 57, 60, 66, 69, 75, 78, 80, 81, 83, 84, 85 , 86, 87, 88, 89, 90} or

{1, 2, 3, 5, 6, 7, 8, 10, 12, 14, 15, 18, 23, 25, 50, 52, 57, 59, 61, 71, 75, 77, 79, 80, 82 , 84, 86, 87, 88, 89}.

The elements of each of the combinations for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 90. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

FIG. 3 is a block diagram of a transmitter of a Node B for transmitting an E-AGCH according to an exemplary embodiment of the present invention.

Referring to FIG. 3, where, after entering a 6-bit grant AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG grant, a 16-bit CRC, generates a CRC associated with the UE-ID by performing the operation on module 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving the AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 22-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/3, adds eight tail bits to the 22-bit control information and convolutionally encodes the 30-bit information to obtain a 90-bit encoded block. The rate matching device 310 punctures a 90-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. When implemented in this example, the control information transmission controller 316 controls the code rate of the channel encoder 308 and selects a sequence for rate matching of the rate matching device 310. The control information transfer controller 316 stores at least one of the above combinations for rate matching and applies one of the combinations for rate matching for the rate matching device 310. The combination used for speed matching is set in advance between the transmitter and receiver. The control information transmission controller 316 may be included in a packet data reception controller (not shown) for controlling the reception of packet data on an E-DCH.

4 is a block diagram of a UE receiver for receiving an E-AGCH according to an exemplary embodiment of the present invention.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block by filling in zeros of the punctured bits in accordance with the speed matching used in the speed matching device 310 of node B If the E-AGCH uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and reverse rate matching unit 406 perform the same operation five times and combine the resulting coded subblocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 6-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC When implemented in this example, the control information reception controller 418 selects a combination for rate matching for the rate inverse matching device 406 and the code rate of the channel decoder 408. The control information reception controller 418 remembers at least one of the above combinations for rate matching and applies one of the combinations for rate matching for the reverse rate matching device 406. A controller information receiving controller 418 may be included in a packet data controller (not shown) for controlling packet data transmission on an E-DCH.

Example 2

As an example implementation of the present invention, a combination is proposed for rate matching for a 7-bit AG grant. The AG grant, for example, includes a 5-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or a 5-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 6-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 6-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of seven bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 23-bit control information with a 7-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is a 93-bit encoded stream. 33 bits are punctured from the 93-bit channel encoded block for transmission in the 2-millisecond TTI interval of the E-AGCH channel, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. The following combinations for speed matching are available for use.

Combination for speed matching =

{1, 2, 3, 4, 5, 7, 9, 11, 12, 13, 15, 17, 20, 23, 42, 45, 46, 50, 54, 70, 71, 74, 77, 80, 81 , 82, 83, 85, 86, 87, 80, 90, 91, 93},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 21, 24, 42, 47, 54, 56, 58, 66, 68, 78, 81, 83, 84 , 86, 87, 88, 89, 90, 91, 92, 93},

{1, 2, 3, 5, 6, 7, 8, 10, 12, 14, 15, 16, 21, 23, 42, 47, 49, 54, 56, 58, 66, 68, 73, 78, 80 , 82, 83, 85, 87, 89, 90, 91, 92},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 21, 23, 25, 42, 47, 54, 56, 58, 66, 68, 73, 78, 80 , 82, 83, 85, 87, 89, 90, 91, 92},

{1, 2, 3, 5, 6, 7, 8, 12, 14, 15, 16, 21, 23, 25, 42, 47, 49, 54, 56, 58, 66, 68, 75, 77, 79 , 82, 83, 85, 87, 89, 90, 91, 92},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 21, 24, 42, 48, 54, 57, 60, 66, 69, 78, 81, 83, 84 , 86, 87, 88, 89, 90, 91, 92, 93},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 16, 21, 23, 28, 42, 49, 54, 56, 58, 66, 68, 74, 78, 80 , 82, 83, 85, 87, 89, 90 91, 92},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 18, 21, 24, 27, 54, 57, 60, 66, 69, 78, 81, 83, 84 , 86, 87, 88, 89, 90, 91, 92, 93},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 21, 24, 42, 48, 54, 57, 60, 63, 66, 69, 78, 81, 83, 84 , 86, 87, 88, 89, 90, 91, 92, 93}, or

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 21, 24, 42, 48, 54, 57, 60, 63, 66, 69, 72, 75, 78, 81 , 83, 84, 86, 87, 89, 90, 92, 93}.

The elements of each of the combinations for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 93. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, a transmitter of a Node B for transmitting an E-AGCH according to a second exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 3, where, after entering the 7-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 23-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/3, adds eight tail bits to the 23-bit control information and convolutionally encodes the 31-bit information to obtain a 93-bit encoded block. The rate matching device 310 punctures a 93-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transfer controller 316 stores at least one of the above combinations for speed matching and applies one predetermined combination of combinations for speed matching for the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a second exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 7-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 3

As an example implementation of the present invention, a combination for rate matching for an 8-bit AG grant is provided. The AG grant, for example, includes a 6-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or a 6-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 7-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 7-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of eight bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 24-bit control information with an 8-bit AG coupled to a 16-bit CRC associated with the UE-ID and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is a 96-bit encoded stream. 36 bits are punctured from a 96-bit channel encoded block for transmission in the 2-millisecond TTI interval of the E-AGCH, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. The following combinations for speed matching are available for use.

Combination for speed matching =

{1, 3, 4, 6, 7, 8, 11, 13, 14, 20, 22, 23, 24, 25, 32, 36, 40, 44, 47, 50, 58, 64, 70, 73, 76 , 77, 79, 80, 83, 86, 88, 89, 92, 93, 94, 96},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 19, 24, 29, 35, 37, 45, 47, 50, 54, 58, 62, 68, 75, 82 , 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96},

{1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 21, 23, 25, 32, 41, 43, 48, 50, 52, 57, 59, 64, 69, 75, 77 , 79, 82, 83, 86, 87, 88, 90, 92, 93, 94, 95},

{1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 21, 23, 25, 30, 32, 41, 43, 48, 50, 52, 57, 59, 64, 69, 77 , 79, 82, 83, 86, 87, 88, 90, 92, 93, 94, 95},

{1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 21, 23, 25, 32, 48, 50, 52, 57, 59, 61, 66, 68, 70, 75, 77 , 79, 82, 83, 86, 87, 88, 90, 92, 93, 94, 95},

{1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 21, 23, 25, 30, 32, 34, 41, 43, 48, 50, 52, 57, 59, 64, 69 , 79, 82, 83, 86, 87, 88, 90, 92, 93, 94, 95},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 24, 27, 30, 33, 42, 45, 48, 51, 54, 57, 60, 66, 69, 81 , 84, 86, 87, 89, 90 91, 92, 93, 94, 95, 96},

{2, 3, 4, 5, 7, 9, 11, 13, 15, 21, 23, 25, 30, 32, 34, 39, 41, 43, 48, 50, 52, 57, 59, 64, 69 , 80, 82, 84, 86, 87, 88, 90, 92, 93, 94, 95},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 20, 21, 24, 27, 57, 60, 63, 66, 69, 72, 81 , 84, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 24, 26, 28, 33, 42, 44, 46, 51, 53, 55, 60, 66, 69, 81 , 84, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96}, or

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 24, 27, 30, 33, 42, 45, 48, 51, 54, 57, 60, 66, 81 , 84, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96}.

The elements of each of the combinations for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 96. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, a transmitter of a node B for transmitting an E-AGCH according to a third exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 3, where, after entering the 8-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving the AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 24-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/3, adds eight tail bits to the 24-bit control information and convolutionally encodes the 32-bit information to obtain a 96-bit encoded block. The rate matching device 310 punctures a 96-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314.

At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transfer controller 316 stores at least one of the above combinations for speed matching and applies one predetermined combination of combinations for speed matching for the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a third exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into an 8-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 4

As an example implementation of the present invention, a combination for rate matching for a 9-bit AG grant is provided. The AG grant, for example, includes a 7-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE equipment, or a 7-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes an 8-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes an 8-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of nine bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 25-bit control information with a 9-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is a 99-bit encoded stream. 39 bits are punctured from the 99-bit channel encoded block for transmission in the 2-millisecond TTI interval of the E-AGCH, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. The following combinations for speed matching are available for use.

Combination for speed matching =

{2, 3, 4, 5, 6, 9, 10, 12, 14, 17, 18, 21, 27, 32, 33, 36, 37, 41, 49, 51, 52, 55, 62, 71, 72 , 73, 78, 80, 85, 86, 88, 89, 91, 93, 94, 95, 96, 97, 98},

{2, 3, 4, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 30, 31, 35, 42, 44, 46, 51, 53, 55, 60, 62 , 64, 69, 71, 83, 85, 86, 89, 90, 91, 93, 95, 96, 97, 98},

{2, 3, 4, 5, 6, 7, 8, 12, 13, 15, 17, 19, 21, 24, 26, 31, 35, 42, 44, 46, 51, 53, 55, 60, 62 , 64, 69, 71, 82, 85, 86, 89, 90, 91, 93, 95, 96, 97, 98},

{1, 2, 3, 4, 6, 7, 8, 12, 13, 15, 17, 19, 21, 24, 26, 31, 35, 42, 44, 46, 51, 53, 55, 60, 62 , 64, 69, 71, 82, 85, 86, 89, 90, 91, 93, 95, 96, 97, 98},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 19, 21, 24, 42, 47, 54, 56, 58, 66, 68, 71 , 72, 73, 75, 84, 86, 87, 89, 90, 92, 93, 95, 96, 98, 99},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 20, 21, 24, 42, 48, 54, 57, 60, 66, 69, 71 , 72, 74, 75, 84, 86, 87, 89, 90, 92, 93, 95, 96, 98, 99},

{1, 2, 3, 5, 6, 7, 8, 12, 13, 15, 17, 18, 19, 21, 24, 26, 34, 42, 44, 46, 51, 53, 55, 60, 62 , 64, 69, 71, 83, 85, 86, 89, 90, 91, 93, 95, 96, 97, 98},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 18, 21, 24, 30, 33, 39, 42, 48, 54, 57, 60, 63, 66, 69 , 72, 75, 84, 87, 89, 90, 92, 93, 94, 95, 96, 97, 98, 99},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 21, 24, 27, 54, 57, 60, 63, 66, 69, 72, 75 , 78, 81, 84, 86, 87, 89, 90, 92, 93, 95, 96, 97, 98, 99}, or

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 20, 21, 24, 27, 30, 60, 66, 69, 72, 75, 78 , 80, 81, 83, 84, 86, 87, 89, 90, 92, 93, 95, 96, 98, 99}.

The elements of each of the combinations for speed matching represent the position of the bits to be punctured among the channel encoded bits # 1 through # 99. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a fourth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering the 9-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving the AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 25-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/3, adds eight tail bits to the 25-bit control information and convolutionally encodes the 33-bit information to obtain a 99-bit encoded block. The rate matching device 310 punctures a 99-bit encoded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314.

At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transfer controller 316 stores at least one of the above combinations for speed matching and applies one predetermined combination of combinations for speed matching for the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a fourth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 9-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 5

As an example implementation of the present invention, a combination for rate matching for a 10-bit AG grant is provided. The AG grant, for example, includes an 8-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or an 8-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 9-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 9-bit allowable maximum data rate or power offset and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of ten bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 26-bit control information with 10-bit AG coupled to the 16-bit CRC associated with the UE-ID and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is a 102-bit encoded stream. Of the 102-bit channel encoded block, 42 bits are punctured for transmission in the 2-millisecond TTI interval of the E-AGCH channel, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. The following combinations for speed matching are available for use.

Combination for speed matching =

{1, 2, 3, 4, 5, 6, 10, 13, 14, 16, 19, 26, 28, 30, 31, 36, 38, 39, 41, 42, 45, 50, 52, 57, 68 , 69, 71, 77, 79, 81, 82, 83, 85, 86, 88, 91, 95, 96, 97, 98, 100, 101},

{1, 3, 5, 6, 7, 9, 10, 12, 13, 15, 16, 17, 20, 21, 30, 32, 34, 42, 43, 44, 50, 52, 54, 55, 57 , 61, 75, 78, 79, 82, 84, 87, 88, 90, 92, 93, 94, 97, 98, 99, 101, 102},

{1, 2, 3, 5, 6, 7, 8, 12, 13, 15, 17, 18, 19, 21, 23, 25, 33, 35, 37, 42, 44, 52, 57, 59, 61 , 66, 68, 70, 75, 77, 84, 86, 88, 89, 92, 93, 94, 96, 98, 99, 100, 101},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 17, 18, 19, 21, 23, 25, 33, 36, 38, 40, 54, 56, 58, 63 , 65, 67, 72, 74, 76, 84, 86, 88, 89, 92, 93, 94, 96, 98, 99, 100, 101},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 20, 21, 24, 27, 36, 39, 42, 54, 57, 60, 63 , 66, 69, 72, 75, 78, 84, 87, 89, 90, 92, 93, 95, 96, 98, 99, 101, 102},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 19, 21, 23, 25, 36, 38, 40, 54, 56, 58, 63 , 65, 67, 72, 74, 76, 84, 87, 89, 90, 92, 93, 95, 96, 98, 99, 101, 102},

{1, 2, 3, 4, 5, 6, 7, 8, 12, 14, 15, 17, 18, 19, 21, 23, 25, 33, 36, 38, 40, 45, 47, 54, 56 , 58, 63, 65, 67, 72, 84, 86, 88, 89, 92, 93, 94, 96, 98, 99, 100, 101},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 18, 21, 24, 33, 36, 39, 42, 48, 54, 57, 60, 66, 69 , 72, 75, 78, 84, 87, 89, 90, 92, 93, 95, 96, 97, 98, 99, 100, 101, 102},

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 17, 18, 21, 24, 27, 36, 39, 42, 54, 57, 60, 66, 69 , 72, 75, 78, 84, 87, 89, 90, 92, 93, 95, 96, 97, 98, 99, 100, 101, 102}, or

{1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 15, 18, 21, 24, 33, 36, 39, 42, 48, 54, 57, 60, 66, 69 , 72, 75, 87, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102}.

The elements of each of the combinations for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 102. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a fourth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering a 10-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 25-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/3, adds eight tail bits to the 26-bit control information and convolutes the 34-bit information to obtain a 102-bit encoded block. The rate matching device 310 punctures a 102-bit encoded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314.

At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transfer controller 316 stores at least one of the above combinations for speed matching and applies one predetermined combination of combinations for speed matching for the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a fifth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 10-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 6

As an example implementation of the present invention, a combination is proposed for rate matching for a 5-bit AG grant. The AG grant, for example, includes a 4-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE equipment, or a 4-bit equivalent power offset for the allowable maximum data rate and a 1-bit AG duration indicator to indicate how long the AG is valid. Either the AG grant includes a 4-bit allowable maximum data rate or power offset, and a 1-bit AG duration indicator indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 21-bit control information with 5-bit AG coupled to the 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/3. As a result, a channel encoded block is created, which is an 87-bit encoded stream. 27 bits are punctured from the 87-bit channel coded block for transmission in the 2-millisecond TTI interval of the E-AGCH channel, for which the SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit speed-matched block. A speed matching pattern representing punctured bit positions is modeled so that the change in the BER frequency at each bit position of the speed-matched block is reduced, thereby improving the BLER response. When using 2-millisecond TTI intervals for the E-AGCH, the following combination is available for rate matching.

Combination for speed matching =

{1, 2, 3, 4, 6, 7, 10, 12, 14, 17, 19, 20, 21, 39, 45, 48, 59, 65, 67, 74, 75, 76, 80, 81, 83 , 85, 86, 87}

Combination elements for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 87. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a sixth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering a 5-bit grant, AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 21-bit control information. The channel encoder 308, which uses a convolutional code with a code restriction length of 9 and a code rate of 1/3, adds eight tail bits to the 21-bit control information and convolutionally encodes the 29-bit information to obtain an 87-bit encoded block.

The rate matching device 310 punctures an 87-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for speed matching and applies it to the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a sixth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 5-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

In the above first to sixth exemplary embodiments, a convolutional code with a code restriction length of 9 and a code rate of 1/3 defined in 3GPP standards is used as a channel coding method for an E-AGCH. Further, in exemplary seventh through eleventh embodiments of the present invention, rate matching is provided for the E-AGCH, where a convolutional code with a code restriction length of 9 and a code rate of 1/2 is used as the channel coding method for the E-AGCH.

The control information from 21 to 26 bits in length, to be delivered via the E-AGCH, is coupled with 8 tail bits, and then encoded to obtain from 58 to 68 coded bits ((21 + 8) × 2 = 58, (26 + 8) × 2 = 68) by convolutional coding at a rate of 1/3.

2B shows a convolutional encoder with a code restriction length of 9 and a code rate of 1/2, as defined in 3GPP standards.

2B, where the convolutional encoder 220 includes eight consecutive shift registers 222, 224, 226, 228, 230, 232, 234 and 236, as well as a plurality of adders 222b, 224a, 224b, 226a, 226b, 228a, 230b , 234b, 236a, and 236b for receiving input information bits or output bits of shift registers 222 to 236. Input information including eight tail bits, which are zeros, sequentially passes through shift registers 222 to 236, starting from the first bit, as a result, coded bits are created in the order output0, output1, output2, output0, output1, output2 ,. ..

The channel-encoded control information is delivered in a 2-millisecond TTI interval of the E-AGCH. If an expansion coefficient (SF) of 256 and QPSK modulation are used for the E-AGCH, a total of 60 bits can be transmitted in the 2-millisecond TTI interval. Thus, 2 bits are repeated (= 58-60), or up to 8 bits (= 68-60) are punctured from the encoded control information of the E-AGCH channel. It should be noted here that in the case of a 6-bit AG grant, control information including 6-bit AG, 16-bit CRC associated with the UE-ID, and 8 tail bits are convolutionally encoded with a code constraint length of 9 and a code rate 1/2 to get 60 channel coded bits. Since the number of transmitted bits in the 2-millisecond TTI interval is 60, in this case, rate matching is not required.

The following exemplary embodiments of the present invention are intended to provide rate matching combinations that minimize the BLER characteristic of control information delivered over the E-AGCH. Exemplary seventh through eleventh embodiments of the present invention provide combinations for rate matching and corresponding transmission and reception methods for a 5-bit AG grant, 7-bit AG grant, 8-bit AG grant, 9-bit AG grant, and 10-bit AG grant, respectively .

Example 7

As an example implementation of the present invention, a combination is proposed for rate matching for a 5-bit AG grant. The AG grant, for example, includes a 4-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE equipment, or a 4-bit equivalent power offset for the allowable maximum data rate and a 1-bit AG duration indicator to indicate how long the AG is valid. Either the AG grant includes a 4-bit allowable maximum data rate or power offset, and a 1-bit AG duration indicator indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 21-bit control information with a 5-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code restriction length of 9 and a code rate of 1/2. The result is a channel encoded block representing a 58-bit encoded stream. 2 bits from a 58-bit channel coded block are repeated to match the size of the channel coded block with a 2-millisecond TTI interval of the E-AGCH, for which an SF coefficient of 256 and QPSK modulation are used. Thus, a 60-bit speed-matched block is created. A speed matching pattern representing repetitive bit positions is modeled so that changes in the BER frequency at each bit position of the speed-matched block are reduced, which improves the BLER performance. The following combination is available for speed matching.

Combination for speed matching = {23, 57}.

Combination elements for rate matching represent the positions of the bits to be repeated among channel encoded bits # 1 through # 58. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a seventh exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering a 5-bit grant, AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 21-bit control information. The channel encoder 308, which uses a convolutional code with a code restriction length of 9 and a code rate of 1/2, adds eight tail bits to the 21-bit control information and convolutionally encodes the 29-bit information to obtain a 58-bit encoded block.

The rate matching device 310 punctures a 58-bit encoded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for rate matching and applies it to the rate matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a seventh exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The rate matching device 406 reconstructs (i.e., combining) the bits repeated by the rate matching device 310 for a speed-matched block in accordance with the speed matching combination used in the node speed matching device 310. If 10- is used in the E-AGCH 402 millisecond TTI interval with five repeating 2 millisecond TTI intervals, then the physical channel demapper 404 and the speed demapper 406 perform the same op radio five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 5-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 8

As an example implementation of the present invention, a combination is proposed for rate matching for a 7-bit AG grant. The AG grant, for example, includes a 5-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or a 5-bit equivalent power offset for the allowable maximum data rate and a 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 6-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 6-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of seven bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 23-bit control information with a 7-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/2. As a result, a channel encoded block is created, which is a 62-bit encoded stream. 2 bits from a 62-bit channel coded block are repeated to match the channel coded block size with a 2-millisecond TTI interval of the E-AGCH channel, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit rate matched block. A speed matching pattern representing repetitive bit positions is modeled so that changes in the BER frequency at each bit position of the speed-matched block are reduced, which improves the BLER performance. The following combination is available for speed matching.

Combination for speed matching = {2, 62}.

The rate matching elements of the combination represent the positions of the bits to be repeated among the channel encoded bits # 1 through # 62. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to an eighth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering the 7-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 23-bit control information. The channel encoder 308, which uses a convolutional code with a code restriction length of 9 and a code rate of 1/2, adds eight tail bits to the 23-bit control information and convolutionally encodes the 31-bit information to obtain a 62-bit encoded block.

The rate matching device 310 punctures a 62-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for speed matching and applies it to the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to an eighth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits repeated by the rate matching device 310 for a speed-matched block, in accordance with the rate matching combination used in the speed matching device 310 of the node B. If the channel E- AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the speed demapper 406 spans perform the same operation five times and combine the resulting coded sub-blocks into one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 7-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 9

As an example implementation of the present invention, a combination for rate matching for an 8-bit AG grant is provided. The AG grant, for example, includes a 5-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to UE equipment, or a 6-bit equivalent power offset for an allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 7-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 7-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of eight bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 24-bit control information with an 8-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code restriction length of 9 and a code rate of 1/2. As a result, a channel encoded block is created, which is a 64-bit encoded stream. 4 bits from a 64-bit channel encoded block are punctured to match the size of the channel encoded block with a 2-millisecond TTI interval of the E-AGCH channel, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit rate matched block. A speed matching pattern representing repetitive bit positions is modeled so that changes in the BER frequency at each bit position of the speed-matched block are reduced, which improves the BLER performance. The following combination is available for speed matching.

Combination for speed matching = {2, 10, 60, 63} or {2, 6, 60, 63}.

Combination elements for rate matching represent the positions of the bits to be repeated among the channel encoded bits # 1 through # 64. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a ninth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering the 8-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving the AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 24-bit control information. The channel encoder 308, which uses a convolutional code with a code constraint length of 9 and a code rate of 1/2, adds eight tail bits to the 24-bit control information and convolutionally encodes the 32-bit information to obtain a 64-bit encoded block. The rate matching device 310 punctures a 64-bit encoded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for speed matching and applies it to the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a ninth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into an 8-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 10

As an example implementation of the present invention, a combination for rate matching for a 9-bit AG grant is provided. The AG grant, for example, includes a 7-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE equipment, or a 7-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes an 8-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes an 8-bit allowable maximum data rate or power offset, and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of nine bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 25-bit control information with a 9-bit AG coupled to a 16-bit CRC associated with the UE-ID, and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/2. As a result, a channel encoded block is created, which is a 66-bit encoded stream. 6 bits from a 66-bit channel encoded block are repeated to match the channel encoded block size with a 2-millisecond TTI interval of the E-AGCH for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit rate matched block. A speed matching pattern representing repetitive bit positions is modeled so that changes in the BER frequency at each bit position of the speed-matched block are reduced, which improves the BLER performance. The following combination is available for speed matching.

Combination for speed matching = {1, 3, 7, 59, 63, 66} or {1, 4, 10, 59, 63, 66}.

The elements of each of the combinations for speed matching represent the position of the bits to be punctured among the channel encoded bits # 1 through # 66. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to a tenth exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering the 9-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving the AG grant, and then combines the CRC associated with the UE-ID with the AG grant, resulting in 25-bit control information.

The channel encoder 308, which uses a convolutional code with a code restriction length of 9 and a code rate of 1/2, adds eight tail bits to the 25-bit control information and convolutionally encodes the 33-bit information to obtain a 66-bit encoded block. The rate matching device 310 punctures a 66-bit encoded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314.

At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for speed matching and applies it to the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to a tenth exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) bits punctured by the rate matching device 310 for a speed-matched block in accordance with a speed matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 and perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 9-bit AG grant and a 16-bit CRC tied to a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

Example 11

As an example implementation of the present invention, a combination for rate matching for a 10-bit AG grant is provided. The AG grant, for example, includes an 8-bit allowable maximum data rate representing the maximum amount of uplink radio resources available to the UE, or an 8-bit equivalent power offset for the allowable maximum data rate, 1-bit AG duration indicator to indicate how long the AG is valid, and a 1-bit AG validity indicator for the process, indicating whether the AG is valid for one particular HARQ process or for the entire HARQ process. Either the AG grant includes a 9-bit allowable maximum data rate or power offset and a 1-bit AG duration indicator.

In a third example, an AG grant includes a 9-bit allowable maximum data rate or power offset and a 1-bit AG validity indicator for the process. Either the AG configuration includes the permissible maximum data rate or power offset, the AG duration indicator, the AG validity indicator for the process, and other E-AGCH control bits, a total of ten bits.

In addition to the AG grant, the E-AGCH carries the UE-ID for identifying the UE and CRC for error detection in the AG grant. The UE-ID and CRC are each 16 bits and are modulo 2 operations on a bit-by-bit basis. Thus, they are transmitted as a 16-bit CRC masked by a UE-ID. This 16-bit CRC is called a UE-ID CRC. The UE may determine whether the received AG grant is intended for a given UE using the CRC associated with the UE-ID.

Eight tail bits are added to the 26-bit control information with a 10-bit AG coupled to a 16-bit CRC associated with the UE-ID and are convolutionally encoded with a code constraint length of 9 and a code rate of 1/2. As a result, a channel encoded block is created, which is a 68-bit encoded stream. 8 bits from a 68-bit channel coded block are punctured to match the channel coded block size with a 2-millisecond TTI interval of the E-AGCH, for which an SF coefficient of 256 and QPSK modulation are used, resulting in a 60-bit rate-matched block. A speed matching pattern representing repetitive bit positions is modeled so that changes in the BER frequency at each bit position of the speed-matched block are reduced, which improves the BLER performance. The following combinations are available for speed matching.

Combination for speed matching = {1, 2, 3, 8, 49, 65, 67, 68} or {2, 5, 6, 10, 54, 59, 63, 68}.

Combination elements for rate matching represent the positions of the bits to be punctured among the channel encoded bits # 1 through # 68. If the 10-millisecond TTI interval of the E-AGCH is specified, the 2-millisecond TTI of the E-AGCH appears five times.

Next, with reference to FIG. 3, a transmitter of a Node B for transmitting an E-AGCH according to an eleventh exemplary embodiment of the present invention is described.

Referring to FIG. 3, where, after entering a 10-bit grant of AG 302, the CRC adder 304 associated with the UE-ID creates, based on the AG, a 16-bit CRC, generates a CRC associated with the UE-ID by performing a modulo operation 2 for a 16-bit CRC with a 16-bit UE-ID to identify the UE equipment for receiving an AG grant, and then combines the CRC associated with the UE-ID with an AG grant, resulting in 26-bit control information. The channel encoder 308, which uses a convolutional code with a code restriction length of 9 and a code rate of 1/2, adds eight tail bits to the 26-bit control information and convolutionally encodes the 34-bit information to obtain a 68-bit encoded block. The rate matching device 310 punctures a 68-bit coded block according to a predetermined combination for rate matching. The physical channel mapper 312 maps the speed-matched block to a physical channel frame configured to be suitable for 2-millisecond TTI intervals of the E-AGCH. Thus, control information is transmitted on the E-AGCH 314. At the same time, the control information transmission controller 316 controls the transmission of control information for the E-DCH through the CRC adder 304 associated with the UE-ID, the channel encoder 308, the rate matching device 310 and the physical channel display device 312. The control information transmission controller 316 stores the above combination for speed matching and applies it to the speed matching device 310.

Next, a receiver UE for receiving an E-AGCH according to an eleventh exemplary embodiment of the present invention is described with reference to FIG.

Referring to FIG. 4, where a UE receives a signal on an E-AGCH 402. A physical channel demapper 404 extracts a rate-matched block from a 2 millisecond TTI interval in a received signal. The reverse rate matching device 406 restores (i.e., performs the reverse puncturing operation) the bits repeated by the rate matching device 310 for the speed-matched block in accordance with the rate matching combination used in the rate matching device 310 of the node B. If on the E-AGCH 402 uses a 10-millisecond TTI interval with five repeating 2-millisecond TTI intervals, then the physical channel demapper 404 and the reverse rate matcher 406 STI perform the same operation five times and combine the resulting coded sub-blocks in one coded block.

Channel decoder 408 decodes the encoded block received from the reverse rate matching device 406. The coded block is divided into a 10-bit AG grant and a 16-bit CRC associated with a UE-ID. The UE-ID mapped CRC allocator 410 allocates a 16-bit CRC by performing a modulo 2 operation for a 16-bit UE-ID mapped CRC with a 16-bit UE-ID 412 of the UE and provides dedicated CRCs and AG to the CRC verification device 414. CRC verifier 414 checks the 16-bit CRC to detect errors in the AG grant. If the CRC check is successful, then the CRC checker 414 issues an error free grant AG 416. Grant AG 416 is used to determine the allowable maximum data rate for E-DCH data. If the CRC verification fails, then the AG grant is rejected.

Meanwhile, the control information reception controller 418 controls the reception of control information for the E-DCH through the physical channel demapper 404, the speed demapper 406, the channel decoder 408, the UE-ID associated CRC allocator 410, and the verifier 414 CRC

As described above, specific, exemplary embodiments of the present invention can improve the reliability of an AG transmission indicating the absolute value of the allowable maximum data rate for a UE by providing a combination for rate matching that reduces BER variation at each bit position in a block and, therefore, can improve the performance of BLER. In addition, with the same BLER characteristic value, power consumption may decrease, and as a result, uplink interference can be reduced.

Although the invention has been shown and described here with reference to specific examples of its implementation, it should be clear to those skilled in the art that various variations in form and detail can be made to these options without departing from the spirit and scope of the invention as defined by the appended claims inventions.

Claims (16)

1. A method of transmitting control information related to the transmission of packet data of the uplink communication system in a mobile communication system, the method comprising creating a 16-bit cyclic redundancy code (CRC) associated with a user equipment identifier (UE-ID) by combining a CRC created to detect errors in control information with a UE-ID for identifying user equipment (UE) for receiving control information; creating 90 coded bits by adding a CRC code associated with the UE-ID and 8 tail bits to 6-bit control information and encoding the summed bits with a code rate of 1/3; creating a 60-bit rate-matched block by matching 90 encoded bits in accordance with combinations for matching the rate representing the positions of the bits to be punctured among the 90 encoded bits; and transmitting a 60-bit speed-matched block to the UE, where the combination for speed matching contains {1, 2, 5, 6, 7, 11, 12, 14,15,17,23,24,31,37,44,47,61,63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}. 2. The method according to claim 1, in which the control information contains an indication of the allowable maximum data rate for transmitting packet data uplink from the UE. 3. The method of claim 2, wherein the control information comprises a 5-bit equivalent power offset for the allowable maximum data rate and a 1-bit validity indicator for the process indicating whether the control information is valid for the entire Hybrid Automatic Repeat Request (HARQ) process . 4. The method according to claim 1, in which the creation of a CRC code associated with a UE-ID, comprises creating a CRC code associated with a UE-ID, by performing a modulo operation 2 for a 16-bit CRC code with a 16-bit UE ID . 5. A device for transmitting control information related to the transmission of packet data uplink communication in a mobile communication system, the device comprising a 16-bit cyclic redundancy code (CRC) generator mapped to a user equipment identifier (UE-ID) to generate a 16-bit cyclic redundancy code (CRC) mapped to a user equipment identifier (UE-ID) by combining a CRC code, created to detect errors in the control information, with a UE-ID for identifying the UE for receiving control information; a channel encoder for generating 90 encoded bits by adding a CRC code associated with a UE-ID and 8 tail bits to 6-bit control information and encoding the added bits with a code rate of 1/3; a rate matching unit for creating a 60-bit rate-matched block by matching 90 encoded bits in accordance with a combination for rate matching representing the positions of the bits to be punctured among the 90 encoded bits; and a physical channel converter for transmitting a 60-bit speed-matched block to the UE, where the combination for matching the speed contains {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}. 6. The device according to claim 5, in which the control information contains an indication of the allowable maximum data rate for transmitting packet data uplink from the UE. 7. The device according to claim 6, in which the control information contains a 5-bit equivalent power offset for the permissible maximum data rate and a 1-bit validity indicator for the process, indicating whether the control information is valid for the entire process of the hybrid automatic repeat request (HARQ) . 8. The device according to claim 5, in which a CRC code associated with a UE-ID is created by performing a modulo 2 operation for a 16-bit CRC code with a 16-bit UE ID. 9. A method for receiving control information related to the transmission of packet data in a mobile communication system, the method comprising extracting a 60-bit speed-matched block from a signal received from network node B; creating 90 encoded bits by performing backward matching of the speed with a 60-bit rate-coordinated block in accordance with combinations for matching the speed representing the positions of the bits to be back-punctured; creating 6-bit control information and a 16-bit cyclic redundancy code (CRC) associated with the user equipment identifier (DE-ID) by decoding 90 encoded bits with a code rate of 1/3; and the output of control information by checking the CRC code associated with the UE-ID, where the combination for matching the speed contains {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}. 10. The method according to claim 9, in which the control information contains an indication of the allowable maximum data rate for transmitting packet data uplink. 11. The method of claim 10, wherein the control information comprises a 5-bit equivalent power offset for an allowable maximum data rate and a 1-bit validity indicator for a process indicating whether control information is valid for the entire Hybrid Automatic Repeat Request (HARQ) process . 12. The method according to claim 9, in which the CRC code associated with the UE-ID is created by performing the operation modulo 2 for a 16-bit CRC code with a 16-bit UE ID. 13. A device for receiving control information related to the transmission of packet data in a mobile communication system, the device comprising: a physical channel inverter for extracting a 60-bit speed-matched block from a signal received from network node B; a reverse rate matching unit for generating 90 coded bits by performing reverse rate matching with a 60-bit rate-matched block in accordance with a combination for rate matching representing the positions of the bits to be reverse punctured; a channel decoder for generating 6-bit control information and a 16-bit cyclic redundancy code (CRC) associated with a user equipment identifier (UE-ID) by decoding 90 encoded bits with a code rate of 1/3; and a CRC checker for outputting control information by checking a CRC code associated with the UE-ID, where the combination for matching the speed contains {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75 , 77, 80, 83, 84, 85, 87, 88, 90}. 14. The device according to item 13, in which the control information contains an indication of the permissible maximum data rate for transmitting packet data uplink. 15. The apparatus of claim 14, wherein the control information comprises a 5-bit equivalent power offset for an allowable maximum data rate and a 1-bit validity indicator for a process indicating whether control information is valid for the entire Hybrid Automatic Repeat Request (HARQ) process . 16. The device according to item 13, in which the CRC code associated with the UE-ID, is created by performing the operation modulo 2 for the 16-bit CRC code with 16-bit UE ID.

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