RU2304283C1 - Device for transforming value of force to voltage - Google Patents

Abstract

FIELD: measuring equipment engineering, possible use for designing various control systems, in particular, when designing automated measuring complex, used for determining physical and mechanical properties of materials by means of kinetic indenting method.

SUBSTANCE: device for transforming force to voltage contains an instrumental amplifier with first resistor connected to it, and also measuring bridge, consisting of second and third resistors, sensor and compensating element. Transformer also contains a power supply, impulse generator, first and second 4AND-NOT logical elements. Introduced to transformer are binary reverse counter, digital-analog converter, first and second support voltage supplies, logical elements 8AND-NOT and 8OR. Buffer generator, first and second operation amplifiers, first and second comparators, fourth and fifth resistors are added. Transformer additionally contains input bus, first and second output buses.

EFFECT: increased precision characteristics.

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Description

The present invention relates to measuring technique and can be used in the development of various kinds of automated control systems, in particular when designing an automated measuring complex used to determine the physicomechanical properties of materials by kinetic indentation.

Known invariant measuring bridge [1]. Also known is a converter of mechanical quantities into an electrical signal, which is the closest technical solution to the proposed invention [2].

The main disadvantage of this converter is the high measurement error of small signals. This disadvantage significantly reduces the accuracy of the converter.

The aim of the invention is to increase the accuracy characteristics in the entire range of measured values. This goal is achieved by the fact that in the transducer is the magnitude of the force of influence into voltage, then a transducer containing a tool amplifier 8 with a first resistor 6 connected to it, as well as a measuring bridge consisting of the second and third resistors 2 and 3, respectively, of the sensor 4 and compensating element 5, and the inputs of the second and third resistors 2 and 3, respectively, are interconnected and are the first power input of the measuring bridge, the output of the second resistor 2 is connected to the input of the sensor 4 and the first input instrumentation amplifier 8, the output of the third resistor 3 is connected to the input of the compensating element 5 and the second input of the instrumentation amplifier 8, outputs of the sensor 4 and the compensating element 5 are united with each other and constitute the second input of the power measuring bridge. The converter further comprises a power source 1, a pulse generator 7, the first and second logic elements 9 and 10, respectively, 4I-NOT. A binary reversible counter 11, a digital-to-analog converter 12, first and second sources 13 and 14, respectively, of a reference voltage, logic elements 15 and 17 of 8 AND-NOT and 8 OR, respectively, are also introduced into the converter. A buffer former 16, first and second operational amplifiers 18 and 23, respectively, a first comparator 19, as well as a second comparator 20, fourth and fifth resistors 21 and 22, respectively, are also added to the converter. The converter also further comprises an input bus 24, a first output bus 25 and a second output bus 26. The first output of the power supply 1 is connected to the first power input of the measuring bridge, and the second output is connected to the second power input of the measuring bridge and the common bus. The output of the instrument amplifier 8 is connected to the U _op - input of the digital-to-analog converter 12, the outputs of which are connected to the inputs of the first operational amplifier 18. The output of the first operational amplifier 18 is connected to the feedback input of the digital-to-analog converter 12 and through the fourth resistor 21 to the first input of the second operational amplifier 23 The first input of the second operational amplifier 23 is connected through the fifth resistor 22 with the interconnected output of the second operational amplifier 23, the first inputs of the first and second omparatorov 19 and 20, respectively, and a second output line 26. The second inputs of the first and second comparators 19 and 20, respectively, are connected to the outputs of the first and second sources 13 and 14, respectively, of the reference voltage. The outputs of the first and second comparators 19 and 20, respectively, are connected to the fourth inputs of the second and first logic elements 10 and 9, respectively, 4I-NOT, and the third inputs of these elements are connected to the outputs of the logic elements 17 and 15, respectively, 8OR and 8I- NOT. The output of the first logic element 9 4 AND is NOT connected to the + 1-input of the binary reverse counter 11, the -1-input of this counter is connected to the output of the second logic element 10 4I-NOT. The code output of the binary reversible counter 11 is connected to the inputs of a logical element 15 8I-NOT, a logical element 17 8OR, a buffer driver 16 and a digital-to-analog converter 12. The first inputs of the first and second logic elements 9 and 10, respectively, 4I-NOT connected to input bus 24, and the second with the output of the generator 7 pulses. The second input of the second operational amplifier 23 is connected to a common bus, and the code outputs of the buffer driver 16 are connected to the first output bus 25.

The converter operates as follows. If there is no force acting on the sensor 4 at the output of the measuring bridge and, accordingly, at the input of the instrumental amplifier 8, the differential voltage will be zero. This will lead to the formation of a zero level at the output of the instrumentation amplifier 8 and, accordingly, at the U _op - input of the digital-to-analog converter 12. The digital-to-analog converter 12, operational amplifiers 18 and 23, as well as resistors 21 and 22 with their interconnections shown in the drawing, form a controlled amplifier, the gain of which is determined by the value of the code received at the input of the digital-to-analog converter 12 from the code output of the binary reversible counter 11. The zero level with U _op is the input of the digital-to-analog pre the browser 12 will go to the first inputs of the first and second comparators 19 and 20, respectively. The output voltage of the second reference voltage source 14 is set below the maximum allowable voltage on the output bus 26, then a zero level at the first input of the second comparator 20 will generate an enable signal at the output of this comparator and, accordingly, at the fourth input of the first logic element 9 4I-NOT. If there is an enable signal on the input bus 24 and the output code is not equal to 11 ... 1, the binary reversible counter 11 pulses from the output of the generator 7 pulses through the first logic element 9 4I-NOT will be sent to the + 1-input binary counter counter 11, increasing its output code by “one” with each pulse. When the value of this code reaches 11 ... 1, the gain of the controlled amplifier will be maximum, and a signal will be generated at the output of the AND-NOT logic element 158, which will prevent the pulses from passing from the output of the 7-pulse generator through the first logic element 9 4I-NOT to + 1-input of the binary reversible counter 11. When a force is applied to the sensor 4, a differential voltage is generated at the output of the measuring bridge, which is amplified by an instrumental amplifier 8, the gain of which is determined by the value first resistor 6, and then amplified by a controlled amplifier with a set maximum gain (code 11 ... 1). The output voltage of the reference voltage source 13 is equal to the maximum allowable voltage on the second output bus 26 and when the amplified differential voltage from the output of the measuring bridge is reached equal to the output voltage of the first reference voltage source 13, a signal will be generated at the output of the first comparator 19, which, if any enable signal on the input bus 24, will ensure the passage of pulses from the output of the generator 7 pulses through the second logic element 10 4I-NOT on the -1-input reverse binary counter 11. With the next pulse, the output code of the binary reverse counter 11 will be reduced by “one”, which will lead to a decrease in the gain of the controlled amplifier and, accordingly, a decrease in voltage on the second output bus 26 and the first inputs of the first and second comparators 19 and 20, respectively , up to a value below the threshold of operation of these comparators. A further increase in the differential voltage from the output of the measuring bridge will again lead to a decrease in the output code of the binary reversible counter 11 and, accordingly, to a decrease in the gain of the controlled amplifier. Reducing the differential voltage from the output of the measuring bridge below the threshold of the second comparator 20 will lead to the formation of a signal at the output of this comparator that unlocks the first logical element 9 4I-NOT, as a result of which the output code of the binary reversible counter 11 will be increased by the next pulse from the output of the 7 pulse generator and, accordingly, the gain of the controlled amplifier is increased. Thus, in the entire range of differential voltages on the second output bus 26, the voltage that is extremely close to the maximum will be automatically maintained, and on the output bus 25, the binary code of the gain of the controlled amplifier, into which it is necessary to divide the voltage on the second output bus 26 for getting its actual value. Logic element 17 8 OR is necessary to prohibit further subtraction by the binary reverse counter 11 after the formation of the code 00 ... 0 at its output. To obtain a unique code on the first output bus 25, a logical "0" is set on the input bus 24, which blocks the first and second logic elements 9 and 10, respectively, 4I-NOT, excluding transients of the binary reverse counter 11 for the duration of this logical "0 "

Information sources

1. RF patent No. 2117304 from 09/27/93.

2. RF patent No. 2071065 from 04/13/93.

Claims (1)

The converter of the magnitude of the force of influence into voltage, containing an instrument amplifier with a first resistor connected to it, as well as a measuring bridge, consisting of a second and third resistors, a sensor and a compensating element, the inputs of the second and third resistors being combined and are the first power input of the measuring bridge , the output of the second resistor is connected to the input of the sensor and the first input of the instrument amplifier, the output of the third resistor is connected to the input of the compensating element and the second input the house of the instrumental amplifier, the outputs of the sensor and the compensating element are combined and are the second power input of the measuring bridge, characterized in that it additionally contains a power source, a pulse generator, the first and second logical elements 4I-NOT, a binary reversible counter, logical elements 8I-NOT and 8 OR, the first and second sources of reference voltage, the first and second comparators, a digital-to-analog converter, the first and second operational amplifiers, the fourth and fifth resistors, a buffer form spruce, input bus, and first and second output buses, said first power supply output is connected to the first input power of the measuring bridge, the second output - to a second input power measuring bridge and the common bus, the instrumentation amplifier output is connected to the U _op - input of a digital to analog a converter, the first output of which is connected to the first input of the first operational amplifier, the second output - to the second input of the first operational amplifier, the output connected to the feedback input of the digital-to-analog converter, and through the fourth resistor - with the first input of the second operational amplifier, the first input of the second operational amplifier is also connected through the fifth resistor to the combined output of the second operational amplifier, the first inputs of the first and second comparators and the second output bus, the second inputs of the first and second comparators are connected to the outputs the first and second sources of reference voltage, respectively, the outputs of the first and second comparators are connected to the fourth inputs of the second and first logic elements 4I-N respectively, the third inputs of the first and second logical elements, respectively, are 4I-NOT connected to the outputs of the logical elements 8I-NOT and 8OR, respectively, the output of the first logical element 4I-NOT is connected to the + 1-input of the binary reversible counter, and the output of the second logical element is 4I -NOT - with-1-input of a binary reversible counter, code output connected to interconnected inputs of logical elements 8I-NOT and 8IL, as well as a buffer driver and digital-to-analog converter, the first inputs of the first and second logs 4I-NOT elements are connected to the input bus, and the second to the output of the pulse generator, the code outputs of the buffer driver are connected to the first output bus.