RU2291479C2 - Commutation device containing temporary intervals bus and several buffers - Google Patents

Abstract

FIELD: data nodes in networks, independent consequent data streams transfer through synchronous multiplexing commutator with time division.

SUBSTANCE: there is one data buffer on commutator receiving side for each bus with time division multiplexing (TDM) for data buffering before transfer through bus. Connection table, related to each buffer, contains buffer byte addressing elements. Address order defines the order of byte transfer through bus. Besides, there is one buffer for each bus on the transmitting side, but only one common connection table. Connection table is divided into memory areas - one for every input line and defines data bytes order, in which bytes appear on the corresponding output lines.

EFFECT: increased data throughput.

8 cl, 6 dwg

Description

The scope of the invention

The invention relates to data nodes in communication networks, in particular to the transmission of independent streams of serial data through synchronous time division multiplexing switches (MVR).

BACKGROUND OF THE INVENTION

The lower level of communication networks, for example, the level of connectivity in the core network of a cellular communication environment, can be considered as a level of distributed resources for managing data flows. Switches and multiplexers are part of the core components that serve this purpose. In complex communication networks that manage data of various formats and variable data rates, it is very important that the design of the components be flexible, but not too complex.

Traditionally, switches contain a number of serial inputs and outputs. The data stream at one input may be entirely directed to a specific output line, or may consist of a mixture of time-division multiplexed data frames to be distributed across multiple outputs. Different lines can use different interfaces, for example, E1, E2, E3 and STM-1 (figure 1). Additionally, the data rate of each input line can vary over a wide range. The movement of data frames in the switches is often done through the bus time intervals (MBR) located on the connecting panel of the switches. The MBR bus has a total throughput of usually about 1 Gbit / s, with 64 kbit of data per time slot.

A traditional MBP bus application consists of a data bus (usually 8-bit), a data clock, and a frame sync signal. The time resource is divided into frames, with each frame having a fixed duration (usually 125 μs). The frame synchronization signal (CS) indicates the beginning of each frame and has a period equal to the duration of the frame. The frame synchronization signal and the data clock signal come from the main synchronization source and form the main timing signals for all transmitters and receivers communicating via the MBP bus. Frames are divided into a fixed number (n) of time intervals (VI) identified by local channel interval counters. Local time interval counters are reset to zero by the signal of the COP. In each VI, data can be transmitted from the transmitter to the receiver using time division multiplexing (TDM). Serial data coming from data lines are parallelized (8 bits), which allows you to display data in time intervals.

In implementations of the above-described components of the prior art, there are limitations in the flexibility of synchronous digital switches with respect to minimum delay and configuration flexibility when combined with the concept of no blocking, multi-channel switching, high bandwidth and high reliability.

International patent application WO 99/59276 describes a synchronous digital switch, improved over commercially available components, using matrix circuits with a centralized architecture.

The addressing method set forth in WO 99/59276 is described superficially. The use of only 2-bit RAM for each time interval limits the possibility of connecting (switching) time intervals between two line cards. For example, it is not described how to change the order of time intervals.

SUMMARY OF THE INVENTION

The present invention is to provide a device that eliminates the above disadvantages. The features defined in the attached claims characterize this method.

Brief Description of the Drawings

In order to provide a deeper understanding of the invention, in the following discussion we will rely on the accompanying drawings.

Figure 1 is a block diagram illustrating an example of serial I / O lines with various interfaces connected to the MBP bus, for example, in a switch.

Figure 2 shows how pointers allocate memory space for the MBP buffer according to the present invention.

Figure 3 shows three different blocks of MBP buffers with corresponding connection tables on the receiving side of the three MBR buses.

4 is an example of a connection table element on the receiving side of MBP buses according to the present invention.

5 shows three different blocks of MBP buffers and one shared connection table on the transmitting side of three MBR buses.

6 is an example of a connection table element on the transmitting side of MBP buses according to the present invention.

Description of Preferred Embodiments

A preferred embodiment of the present invention will be described below. This is only one of numerous embodiments and variations within the scope of the invention defined by the attached independent claims, and should not be considered as a limitation.

A preferred embodiment is implemented in a switch with input / output lines for various interfaces shown in FIG. 1. There are three buses on the connection panel, and incoming data must be distributed between them. On each bus (66 MHz) there are 8192 time slots per frame, which provides a total of 24576 time slots.

Incoming data is buffered in one set of memory blocks for each bus. The physical size of the memory blocks is set to 2048 bytes, i.e. the system can manipulate a maximum of 2048 different bytes (channel slots) per frame. The memory is configured in advance using a pointer value for each active line, as shown in FIG.

The value of the pointer contains the address at which the first byte in the frame is supposed to be stored. This address is loaded into the local pointer at the beginning of a new frame, and the pointer increments after writing data to this address. The memory can be shared by 32 different lines, but can also be occupied only by one.

According to figure 3, in addition to the memory blocks, each of them is associated with one table of connections containing 8192 elements. Each element has one address field and one control field. The address field indicates a memory location where you can find the data to be read from the memory, and the control field contains information, for example, whether the current time interval is allowed, whether it is a time interval with a minimum delay, etc.

When reading data from memory, a time slot counter is used to index connection tables. The counter is synchronized with the data clock signal and increments together with time intervals on the connection panel. The backplane bus can carry three different bytes at the same time (one byte per bus), so that the current element of the connection table is simultaneously associated with time intervals x, x + 1 and x + 2.

The byte order in which they arrive on the bus matches the order of their corresponding addresses in the connection table. Thus, the sequence of bytes of MBP buses, and therefore the switching of data from input lines to output lines, depends on where the addresses are stored in the connection table. This is predefined by the software in accordance with the switching requirements.

An element of the connection table of the receiving side is shown in Fig.4. The element consists of the following fields:

ADDRESS - byte addressing in the memory block.

EN - resolution of the time interval. It is set to 1 if the time interval is allowed, and the corresponding data must be placed on the connection panel bus.

MIN - indicates whether the time interval is the minimum delay.

CPU - indicates whether to retrieve data from the CPU register.

The term “minimum delay” expresses a switching mode in which fast data transfer is given high priority. In normal delay mode, data is stored in one frame and placed on the bus in the next frame. In other words, two memories are required, each of which contains 2048 bytes. However, in the minimum delay mode, only one memory is required, since the data should be placed on the bus as quickly as possible. The software developer must be sure that in the same frame the data location is not read before writing. The minimum delay should be adjusted at the line level, and not at the level of time intervals.

So far, we have described only the receiving side of the MBR tires. According to the present invention, a similar architecture exists in the transmitting side shown in FIG. The modules are responsible for storing data coming from the backplane bus and transferring them to the output lines.

As already indicated, the connection panel has three buses, and each of them can have 8192 time intervals (66 MHz). This adds up to 24,576 time slots. The data coming from the connection panel must go to one memory block on the bus, and then the connection table addresses these memories. Unlike the receiving side, there is only one connection table, and not one for each bus. However, the transmit side connection table also contains addresses and control bits. Addresses are used to indicate cells in memory blocks, and control bits can be used to set the minimum delay.

The size of the connection table is set to 2048 bytes, i.e. the system can manipulate a maximum of 2048 different bytes per frame. The connection table is preconfigured using the size parameter and pointer value for each active output line. The pointer value contains the address where you can find the first memory address.

This pointer value is loaded into the local pointer at the beginning of a new frame, and the pointer increments after retrieving data from the cell addressed by the pointer. A connection table can be shared by 32 different lines, but can also be occupied by one. The size parameter controls the selection of the connection table.

A time slot counter is used to index large memory while retrieving data from the backplane bus. Since there are three buses, you need to retrieve three bytes of data in parallel. The order of the output of the corresponding bytes in the corresponding output lines depends on the order of the addresses in each part of the connection table.

In addition, on the transmitting side, the minimum delay means that only one memory block is used per MBR bus, since data should be placed on the bus as quickly as possible. The software developer must be sure that the data location is not read before writing in the same frame.

There are 32 dedicated CPU registers for storing idle data. These combinations can be transmitted on serial lines.

An element of the connection table of the transmitting side is shown in Fig.6. The element contains the following fields:

ADDRESS - RAM addressing.

MIN - indicates whether the time interval is the minimum delay.

BUS - "00" - retrieves data from bus 1.

"01" - retrieves data from bus 2.

"10" - retrieves data from bus 3.

"11" - extracts data from the CPU register.

The present invention provides complete flexibility in switching time intervals, and any combination of time intervals can be transferred between lines (changing the order and number of time intervals) depending on how the tables are configured for writing to and reading from the MBP bus.

In addition, the delay on the node can be very small when the minimum delay is used. In fact, it may be less than 40 μs for a 2 Mbps connection. In minimum delay mode, the system is not non-blocking.

The present invention allows to increase the speed of the connecting panel and to realize high throughput at relatively low cost.

In addition, the excess MBR bus, multicast and broadcast (one transmitter and several receivers) are acceptable.

Abbreviations

E1 is a data transfer method with a speed of 2 Mbps.

LINE - serial data lines (buses), i.e. E1, STM-1, etc.

BP - power supply.

STM-1 - synchronous transmission mode.

MVR - time division multiplexing.

Claims (8)

A switching device applicable to a node in a communication network, wherein the node contains one or more buses of time intervals transferring frames from a series of serial input lines located on the receiving side of the node to a series of serial output lines located on the transmitting side of the node, characterized in that contains one or two data buffers for each bus time slots on the receiving side for buffering frames from the input lines before transmission, a connection table for each bus time slots on the receiving side, and each element of the connection table contains at least a data address indicating a byte in the corresponding data buffer, and the elements are organized in the order in which the corresponding bytes should be transmitted on the data bus, and a counter synchronized with the clock used by the time slot bus to transmit time slots, indicating which byte in the corresponding data buffer is currently being read from the data bus buffer in the time interval of the corresponding data bus by indexing the elements of the connection table. 2. The device according to claim 1, characterized in that the data buffers are shared by all input lines by means of corresponding pointers allocating one memory area in the data buffer for each input line. 3. The device according to claim 1 or 2, characterized in that each element of the connection table contains, in addition to the data address, a control field. 4. The device according to claim 1 or 2, characterized in that for each bus time slots there is only one data buffer and in the same frame, while the data cell in the buffer is not read before writing. 5. A switching device applicable to a node in a communication network, wherein the node contains one or more buses of time intervals transferring frames from a series of serial input lines located on the receiving side of the node to a series of serial output lines located on the transmitting side of the node, characterized in that contains one or two data buffers for each bus time slots on the transmitting side to buffer frames from the bus time slots before feeding them to the output line, a connection table, each element of the connection table containing at least a data address indicating a byte in one of the data buffers, the elements being organized in the order in which the corresponding bytes should be transmitted to the output line. 6. The device according to claim 5, characterized in that it contains one initial pointer to the output line for allocating one memory area in the connection table for each of the output lines and for indicating the first element in each memory area, one indexing pointer to the output line to indicate a connection table element containing the address of the byte currently being extracted from one of the buffers in the corresponding output line. 7. The device according to claim 5 or 6, characterized in that each element of the connection table contains, in addition to the data address, a control field. 8. The device according to claim 5 or 6, characterized in that there is only one data buffer for each bus time intervals and in the same frame, the data cell in the buffer is not read before writing.

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