RU2273948C2 - Method for amplifying digital signals and digital amplifier - Google Patents

Abstract

FIELD: amplification equipment engineering, mainly meant for use in digital sound-reproducing lines, functioning with digital signals sources, and allows amplification of signals received directly from digital carrier without their preliminary transformation to analog form.

SUBSTANCE: method includes: multi-digit digital code, appropriate for count of analog signal, is split onto several portions, therefore forming partial digital signals of decreased digit capacity, then amplified and transformed after amplification to analog form, with following joining.

EFFECT: decreased distortions of output signal due to preservation of required resolution capability, determined by digit capacity of source digital code.

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Description

The invention relates to amplification technology and is mainly intended for use in digital sound reproducing paths that operate with digital signal sources, for example, Audio-CD, DVD-Audio, and other players. The invention allows amplification of signals received directly from a digital medium without first converting them to analog form.

The amplification of the signals, presented in the form of a pulse sequence modulated according to one of the time parameters, makes it possible to use directly to increase the amplitude and power of the signals cascades operating in a class D mode, characterized in that the transistors are either in a saturation state or a cutoff state. The above provides a sufficiently high efficiency of amplifiers, unattainable for Class B circuits. The most common type of modulation in Class D amplifiers is pulse width modulation (PWM), and there are also pulse frequency modulation amplifiers, less often with a combination of several types of modulation. PWM sequence demodulation is carried out quite simply by low-pass filters (low-pass filters), often the role of which is played by frequency-selective loading.

The classical method of amplifying signals by converting them to a pulse sequence is that the amplified analog signal is converted into a PWM sequence using it as a modulating one, then the pulses of the PWM sequence are amplified, after which the PWM sequence is demodulated, thereby isolating the amplified analog signal [Shkritek P. Reference manual for sound circuitry. M .: Mir, 1991, pp. 226-227; Controller class-D audio amplifier TDA 8929T. Philips Semiconductors, 2001].

The method is used to amplify signals received from analog sources. At the same time, a significant part of modern storage media contains information presented in digital form. In these cases, it is advisable to apply a digital code to the amplifier input as a primary signal, without converting it into an analog form. This method is also known, differs little from the first and is as follows.

The method (prototype) of amplification of signals presented in digital form is that an N-bit digital code is converted into a sequence of pulse-width modulated pulses that amplify, and after amplification, the PWM sequence is demodulated, thereby converting the original digital signal into an analog [ TAS 5001 digital audio PWM processor. Texas Instruments, 2001].

A digital amplifier that implements the prototype method comprises a digital code converter (pulse-code modulated (PCM) signal) into a PWM sequence, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to the output of the converter, the input of which serves as the input of a digital amplifier, the output of which is the output of the filter [TAS 5001 digital audio PWM processor. Texas Instruments, 2001; TAS 5100A PWM power output stage. Texas Instruments, 2002].

The disadvantage of both the prototype method and the devices that implement it is the low accuracy of the transmission of the waveform. Distortions in the output signal arise due to the complexity of converting a multi-bit digital code into pulses of the corresponding width (duration), i.e. Cannot convert the digital code into a PWM sequence with the required resolution. If the input N-bit code provides a potential resolution of (2 ^N -1) ^-1 , then the PCM-PWM converter should have at least the same resolution. For small N (up to about 10) it is still possible to obtain the required resolution of the converter, but for large N it is extremely difficult to do. The currently widely used 16-bit / 44.1 kHz audio recording standard (not to mention the 24-bit / 96 kHz standard included in the law) requires the generation of pulses from the PCM-PWM converter output, the width of which should take one of 65535 values at a repetition rate 300-500 (kHz). Information on such a resolution was not found in the above bibliographic sources. It is easy to calculate that if in the classical case, in the absence of an input signal, a meander is present at the output of the PCM-PWM converter, then at a frequency of 400 kHz, the pulse width can vary as much as possible from 1.25 μs to 2.5 μs. Therefore, in the range of 1.25 μs, it is necessary to place 65535 values, for which it will be necessary to form pulses whose durations differ by only 19 ps. To create such a digital converter on the existing element base is difficult even for laboratory research.

The technical result achieved using the present invention is to reduce the distortion of the output signal by maintaining the required resolution, determined by the resolution of the source digital code.

The technical result is achieved by the fact that in the method of amplifying the signals represented in digital form, according to the invention, the N-bit digital code corresponding to the count of the analog signal is divided into K groups of bits, thereby forming K partial digital signals of reduced capacity, each of the received K digital signals are amplified and converted after amplification into analog form, after which K analog signals are combined into a single output signal, taking into account the weights of the bits of the original N-bit code.

Partial digital signals can be amplified by converting into a sequence of pulse-width modulated pulses and amplifying directly received pulses.

The technical result according to the first embodiment is achieved by the fact that in a digital amplifier including a channel containing a digital code converter into a sequence of pulses modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to according to the invention, (K-1) channels and an analog K-input adder, the output of which is the output of a digital amplifier, the N-bit input of the digital amplifier (N> K) is the set of inputs of all K channels, the amplification factors of the pulse amplifiers in which are selected from the set {2 ⁰ , 2 ¹ , 2 ² , ..., 2 ^N-1 }.

The technical result according to the second embodiment is achieved by the fact that in a digital amplifier including a channel containing a digital code converter into a sequence of pulses modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to according to the invention, (K-1) channels and an analog K-input weighting adder are additionally introduced, the input weights of which are selected according to the invention m 2 from the set ^{0, 2 ^1, 2 ^2, ..., 2 ^N-1}, and the adder output is the output of the digital amplifier, N-bit input which (N> K) is the set of all K input channels.

-разрядного входа первого канала и

-разрядного входа второго канала, отношение коэффициентов усиления усилителей импульсов второго и первого каналов составляет

, при этом группа

разрядов, относящихся ко входу первого канала, является группой младших разрядов N-разрядного входа цифрового усилителя, а группа

разрядов, относящихся ко входу второго канала, является группой старших разрядов входа цифрового усилителя.The technical result according to the third embodiment is achieved by the fact that in a digital amplifier including a channel containing a digital code converter into a sequence of pulses modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to according to the invention, a second channel is additionally introduced, the voltage at the output of which has a polarity opposite to polarity These are the voltages at the output of the first channel, the outputs of the digital amplifier are the outputs of the channels, the voltage between the outputs of which serves to supply a digital amplifier to the load, the input of which is an N-bit input, which is a combination of

-digit input of the first channel and

-digit input of the second channel, the ratio of the amplification factors of the amplifiers of the pulses of the second and first channels is

, while the group

bits related to the input of the first channel is the group of the least significant bits of the N-bit input of a digital amplifier, and the group

bits related to the input of the second channel, is a group of high-order bits of the input of a digital amplifier.

At the same time, the digital code converter into the pulse train, which is part of each channel, can be made in the form of a device that converts the input digital signal into a sequence of pulse-width modulated pulses.

The invention is illustrated graphic material. Figure 1 shows a timing diagram illustrating a method of amplifying digital signals, figure 2 is a functional diagram (example implementation) of a digital amplifier according to claim 3, figure 3 is a functional diagram (example implementation) of a digital amplifier according to claim 7 of the claims, FIG. 4 is a functional diagram of one of the options for constructing a converter of a digital code into a pulse sequence.

The timing diagram (figure 1) contains:

- signal u ₁ (t), which is the result of demodulation of the PWM sequence (conversion to analog form) of the group of lower digits;

- the signal u ₂ (t), which is the result of demodulation of the PWM sequence of the group of senior bits;

- the resulting signal u _S (t), which is the sum of the voltages u ₁ (t) and u ₂ (t).

The functional diagram of the digital amplifier of figure 2 contains two 4-bit PCM-PWM converters 1, 2, two amplifiers 3, 4 pulses, two low-pass filters 5, 6 and the adder 7. The output of the adder 7 is the output of a digital amplifier, the 8-bit input of which serve the inputs of the converters 1 and 2, the outputs of which are connected to the inputs of the amplifiers 3 and 4 pulses, respectively, the outputs of which are in turn connected to the inputs of the low-pass filter 5 and 6, respectively, the outputs of which are connected to the inputs of the adder 7.

The functional diagram of the digital amplifier of FIG. 3 contains two 4-bit PCM-PWM converters 8, 9, two pulse amplifiers 10, 11 with bi-polar outputs, two low-pass filters 12, 13 and an amplifier load with resistance R _L. The load of the digital amplifier is connected between the inputs of the low-pass filter 12 and 13, the 8-bit input of the digital amplifier is the inputs of the converters 8 and 9, the outputs of which are connected to the inputs of the amplifiers 10 and 11 pulses, respectively, the outputs of which are in turn connected to the inputs of the low-pass filter 12 and 13, respectively.

Functional diagram (figure 4) of the PCM-PWM converter contains an AND 14 element, a counter 15, a digital comparator 16, a trigger 17, a leading edge discriminator 18, and an OR element 19. The PCM information input is the first multi-bit input of the comparator 16, the second multi-bit input of which connected to the output of the counter 15, the summing input of which is connected to the output of the element And 14, the first input of which serves as the first clock input CLK1 of the Converter, the second clock input CLK2 of which are the combined resetting input of the counter 15 and the input of the discriminator 18, the output of which is connected to the installation input of the trigger 17, the resetting input of which is connected to the output of the comparator 16, the second input of the AND element 14 and the first input of the OR element 19, the output of which is the output of the PWM converter, the second input of the OR element is connected to the output of the trigger 17 19 is connected to input CLK2 of the converter.

The idea underlying the invention is as follows.

It is known that the number U - the countdown of the analog signal - in positional notation with base 2 is expressed as a series

U = a _N-1 2 ^N-1 + a _N-2 2 ^N-2 + ... + a ₂ 2 ² + a ₁ 2 ¹ + a ₀ 2 ⁰ ,

where N is the number of bits (positions) of the selected number system, in this case it is equal to the number of bits of the binary code U (n) = (a _N-1 , a _N-2 , ..., a ₁ , a ₀ );

a _n is the value of the n-th digit (n = 0, 1, 2, ... N-1);

2 ⁿ is the weight of the n-th digit.

The presented expression of any capacity (if N is a finite number) can be transformed using the distributive property and obtain a weighted sum of several groups as a result. As an illustration, we give the count U, described by an eight-bit binary code.

U = 2 ⁴ (a ₇ 2 ³ + a ₆ 2 ² + a ₅ 2 ¹ + a ₄ 2 ⁰ ) + a ₃ 2 ³ + a ₂ 2 ² + a ₁ 2 ¹ + a ₀ 2 ⁰

In this example, we have two four-bit groups: the first is enclosed in brackets and is a group of high-order bits with a total weight factor of 2 ⁴ , and the second group is a group of low-order bits, represented by the first four members on the right. It can be seen from the above record that the group of digits, indicated by brackets, has the same bit weights as the group of the lower four digits. Therefore, we can assume that the eight-digit binary number u _S (n) = (a ₇ , a ₆ , ..., a ₁ , a ₀ ) is presented in the form of the sum of two four-digit numbers u ₁ (n) = (a ₃ , a ₂ , a ₁ , a ₀ ) and u ₂ (n) = (a ₇ , a ₆ , a ₅ , a ₄ ), the last of which is involved in addition with a weight coefficient. For clarity, figure 1 shows two analog signals u ₁ (t) and u ₂ (t), each value of which was obtained by converting from four-digit binary codes u ₁ (n) and u ₂ (n), respectively. The reduced bit codes u ₁ (n) and u ₂ (n) were obtained in the above way from the eight-bit code u _S (n) describing the sinusoidal signal u _S (t). The weighted sum of the two analog signals u ₁ (t) and u ₂ (t) gives the original signal u _S (t) (of course, with sampling and quantization errors)

u _S (t) = 2 ⁴ u ₂ (t) + u ₁ (t).

Thus, to amplify the signal represented in the eight-bit binary code u _S (n), it should be divided into two low-resolution signals and amplify each of them. For digital amplification of the obtained partial signals, one can use the well-known technique: converting signals from the PCM to the PWM sequence, amplifying the pulses of the PWM sequence directly, and demodulating. Obtained after demodulation, the analog signals u ₁ (t) and u ₂ (t) are added taking into account the weight coefficients.

An eight-bit digital amplifier with conversion to a PWM sequence is shown in FIG. The amplifier is a two-channel, because The original eight-bit code is divided into two four-bit groups (K = 2). The four-digit input of converter 1 serves to receive the low-order group code, and a similar input of converter 2 serves to receive the high-order group code. Partial PWM sequences are amplified in amplifiers operating in class D. The weighting summation is carried out by choosing the amplification factors K _U1 and K _{U2 of} amplifiers 3 and 4, respectively, so that the condition (K _U2 / K _U1 ) = 2 ^{4 is} fulfilled.

In the two-channel amplification scheme, you can do without the adder 7 as a separate functional unit. Such a solution is shown in FIG. The difference from the previous circuit consists mainly in the fact that the amplifiers 10 and 11 emit pulses of opposite polarity with respect to each other. Therefore, when connecting the load R _L between the outputs of the amplifiers (through filters 12, 13), the potential difference determined by the sum of the modules u ₁ (t) and u ₂ (t) will be applied to the load.

, представляя исходный отсчет U в виде:In the general case, when dividing an N-bit binary code into two equal groups, a group of higher digits is assigned a common weight coefficient equal to

presenting the original reference U in the form:

-разрядных кодаand form for further transformations and amplification two

-bit code

and

The number K of discharge groups, as well as their bit depth, can be arbitrary. Only the inequality K <N must be satisfied and the sum of all digits in the groups should be equal to N. At K = N, we can talk about bitwise processing. As for the weighting coefficients assigned to specific groups of discharges, they are in all cases included in the set {2 ⁰ , 2 ¹ , 2 ² , ..., 2 ^N-1 } and are selected so that the sum of the series is equal to U.

One of the options for the converter PCM-PWM may be the circuit shown in figure 4. The converter operates in synchronous mode, characterized by the fact that the positive edges of the pulses of the PWM sequence appear at strictly fixed times and, in the absence of an input modulating signal, an unmodulated pulse sequence is present at the PWM output with the minimum pulse duration specified by the clock parameters at the input of CLK2. The repetition period of the CLK2 clock pulses is equal to the repetition period of the pulse-width modulated pulses at the output of the PWM converter. The pulse sequence supplied to the input CLK1 is countable and serves to count the time interval that determines the desired change in the width of the modulated pulses. The operating principle of the converter is based on comparing the PCM input modulating code with the code generated in the converter itself and determining the moment of their equality. The time affected by the counter 15 to achieve their equality, and is equal to the increment of the width (duration) of the modulated pulses. The conversion process begins with the arrival of CLK2 clock pulses. On the positive edge of the clock CLK2, the trigger 17 switches to a high logic level, allowing the passage of counting pulses CLK1 through the element And 14 to the counting input of the counter 15, however, the counter 15 starts counting only after the end of the clock CLK2, since during this time the reset input R of the counter there is an active level. Thus, the current code sent to the comparator 16 for comparison with the PCM information code begins to be formed only after the PWM converter e formed part of the information pulse, equal to its minimum duration. At the moment of equality of the compared codes, the logical “1” from the output of the comparator 16 resets the trigger 17, a negative edge of the output pulse PWM is formed, and the device goes into standby mode for the next clock pulse. We also add that the output modulated signal can also be taken directly from the output of the trigger 17, while in the absence of an input signal at the output of the converter, the initial pulse sequence will not, which is characteristic of asynchronous converters.

-разрядные группы. Каждый из преобразователей в этом случае имеет разрешение

, в то время как выходной аналоговый сигнал усилителя строится из 2^N-1 значений. Следовательно, усилитель в целом имеет разрешение (2^N-1)^-1. Из чего видно, что усилитель обладает разрешающей способностью, лучшей каждого из преобразователя ИКМ-ШИМ примерно в

раз.In the engineering implementation of the proposed technical solutions, their main advantage will be expressed in the reduction of the required range of pulse widths of the PWM sequence while maintaining the same dynamic range of the output (input) signals. This will allow amplifying multi-bit digital signals with a resolution exceeding the resolution of the PCM-PWM converters used. (The resolution of the PCM-PWM converters means the smallest value of the quantization step or the smallest increment of the output analog quantity after demodulation, but without amplification. The resolution of a digital amplifier should be considered the minimum possible increment of the output analog signal.) The resolution of the digital amplifier described in the present work, it turns out to be better than the resolution of PCM-PWM converters, it is easy to see if we take for example the simplest case of two-channel amplification N-bit code divided into two

-digit groups. Each of the converters in this case has permission

, while the analog output of the amplifier is built from 2 ^N -1 values. Therefore, the amplifier as a whole has a resolution of (2 ^N -1) ^-1 . From which it can be seen that the amplifier has a resolution better than each of the PCM-PWM converters, approximately

time.

Decreasing the resolution requirements for PCM-PWM converters simplifies their design, reduces the clock frequencies at which the serial logic of the converters operates, and in some cases eliminates ultra-fast element base and improves the reliability of converters. In addition, reducing the dynamic range of pulse widths (widths) of PWM sequences allows one to increase the minimum pulse width, reduce the effective spectrum width of the PWM sequence, and thereby reduce the required upper cutoff frequency of the amplification paths.

Claims (8)

1. The method of amplification of signals presented in digital form, characterized in that the N-bit digital code corresponding to the count of the analog signal is divided into K groups of bits, thereby forming K partial digital signals of reduced capacity, each of the received K digital signals is amplified and after amplification, they are converted into analog form, after which K analog signals are combined into a single output signal, taking into account the weights of the bits of the original N-bit code. 2. The method according to claim 1, characterized in that the partial digital signals are amplified by converting into a sequence of pulse-width modulated pulses and amplifying the directly received pulses. 3. A digital amplifier including a channel containing a digital code converter into a pulse train modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to the output of the converter, the input of which serves as the channel input the output of which is the output of a low-pass filter, characterized in that (K-1) channels and an analog K-input adder are additionally introduced into it, the output of which is the digital output preamplifier, N-bit input of the digital amplifier (N> K) is the set of all K input channels, the gain factors of amplifiers in which pulses are selected from the set {2 ^0, 2 ^1, 2 ^2, ..., 2 ^N-1}, the adder serves to add the output signals of K channels. 4. The digital amplifier according to claim 3, characterized in that the digital code to pulse train included in each channel is made in the form of a device that converts the input digital signal into a sequence of pulse-width modulated pulses. 5. A digital amplifier including a channel containing a digital code converter into a sequence of pulses modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to the output of the converter, the input of which serves as the channel input the output of which is the output of a low-pass filter, characterized in that (K-1) channels and an analog K-input weighing adder are additionally introduced into it, the weights of the inputs of which are selected from the set {2 ⁰ , 2 ¹ , 2 ² , ... 2 ^N-1 }, the output of the adder is the output of a digital amplifier, the N-bit input of which (N> K) is the set of inputs of all K channels, the adder serves to add the output K channel signals. 6. The digital amplifier according to claim 5, characterized in that the digital code to pulse train included in each channel is made in the form of a device that converts the input digital signal into a sequence of pulse-width modulated pulses. 7. A digital amplifier including a channel containing a digital code converter into a sequence of pulses modulated by a time parameter, a pulse amplifier and a low-pass filter, the input of which is connected to the output of the pulse amplifier, the input of which is connected to the output of the converter, the input of which serves as the channel input the output of which is the low-pass filter output, characterized in that a second channel is additionally introduced into it, the output voltage of which has a polarity opposite to that of the voltage at the output of the first channel, the output of the digital amplifier are the outputs of the channels, the voltage between the outputs of which serves to supply a digital amplifier to the load, the input of which is an N-bit input, which is a combination

-digit input of the first channel and

-digit input of the second channel, the ratio of the amplification factors of the amplifiers of the pulses of the second and first channels is

, while the group

-digits related to the input of the first channel is the group of the least significant bits of the N-bit input of a digital amplifier, and the group

-digits related to the input of the second channel is a group of high-order bits of the input of a digital amplifier. 8. The digital amplifier according to claim 7, characterized in that the digital code to pulse train included in each channel is made in the form of a device that converts the input digital signal into a sequence of pulse-width modulated pulses.

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