RU2257678C2 - Module scaled commutator and method for distribution of frames in fast ethernet network - Google Patents

Abstract

FIELD: data transfer networks, in particular Ethernet-based.

SUBSTANCE: device is made in form of multiple individually programmed single-port communication modules for access to common distributor bus 10, while each single-port communication module has: programmed micro-controller 1, made as access control block for transmitting environment Ethernet (MAC), containing processor with short command list (RISC CPU), and logic device 5 for distribution of data frames, including processing in real time scale and transmission to addresses frame destination ports of Ethernet data, received on said one-port communication module, transfer process is serial and is performed in save-and-send mode.

EFFECT: higher data distribution flexibility control.

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Description

The invention relates to a modular, scalable structure for building switches of fast Ethernet networks accessing a common data distribution bus, and to a method of distributing frames on an Ethernet network in a store-and-forward mode.

Currently, Ethernet switches, especially those that comply with the IEEE 802.1D standard, are based on two different approaches to the implementation of filtering and transmission of Ethernet network frames, namely:

a) based on store-and-forward mode

b) based on the cut-through-forwarding mode.

Save-and-forward switches, as defined by the IEEE 802.3 standard (1998 edition), store incoming data frames completely before sending them again. The filtering functions are performed while the data frames are received and / or contained in the buffer. Such filtering functions include, for example,

- Address discovery and determination of the receiving port (always);

- filtering frames containing errors by checking CRC (Cycling Redundancy Check, control using cyclic redundancy code) (always);

- detection of defective frame structures (always), addresses, frame data fields, frame transmission frequencies (partially or never).

The data flow in the switches operating in the save-and-forward mode (a) is shown schematically in FIG. 4.

An input buffer 40 is always required in this switch structure. Such data buffering seriously affects the operation of the corresponding switch and can lead to a blocking state. Short-term congestion arising from the corresponding congestion of the receiving port can be balanced by such an intermediate buffer. The implementation of receive port allocation depends on the architecture concerned. One of the possibilities is to provide additional buffering of data frames associated with the receiving or transmitting port, as shown in the form of an additional (optional) output buffer 41. The disadvantage of this strategy is that, due to the intermediate buffer, additional latency should be taken into account for the entire system .

Save-and-forward switches are typically processor based systems. A processor or hard logic filters data from multiple ports that are processed sequentially. Typically, processing is performed by copying a data frame into the shared memory of the switch, which the receive port processor also has access to.

According to the clipping-for-forwarding strategy (b), data frames are sent immediately after analysis of the recipient address, that is, without intermediate buffering. Compared to the aforementioned strategy (a), the latency is minimal, however, no complex filtering functions can be applied, since data frames are transmitted in real time for distribution. Erroneous or distorted data frames are also transmitted, and therefore occupy expensive network bandwidth.

5 and 6 depict two architectures operating according to the principle of shared memory, in which all ports have access to a common memory field.

According to the block structure of FIG. 5, the central component 50 is responsible for processing and sending all incoming data frames. If the number of ports and / or the rate of data exchange increases, the central component 50 may become the bottleneck of the entire architecture. In addition, the common data bus 51 is usually heavily loaded, since all data transfers go through the mentioned bus. First, incoming frames are transmitted via a shared data bus 51 to shared memory 52, and then filtered and transmitted by the central processor in the centralized component 50. Then, data frames are distributed from shared memory 52 via data bus 51 to output ports 53. Accordingly, each data frame is transmitted bus 51 twice. This explains the fact that the factor “2” should be used in the following equation to estimate the required bandwidth:

Bandwidth = number of ports · frequency of the input stream · 2 = 3.2 Gbit / s (for the case of 16 ports of 100 Mbit / s).

This equation is valid only if one frame should be sent to one output port (unicast). For broadcast transmission (multicast, one frame to multiple outputs), the required bandwidth increases accordingly. A typical example of a prototype Ethernet switching structure according to the save-and-forward method for 16 full duplex, fast Ethernet channels was created by LEVEL ONE, which uses a central network processor such as 1XP1200.

6 shows another example for the aforementioned principle of shared memory having a distributed architecture. All submodules 60 operate independently of each other when data frames should only be sent within the corresponding node. The connection of many elements of the block is provided through a common data bus 61. Such a distributed architecture is easier to scale, because the increase in the number of ports 62 can be implemented by adding the appropriate submodules.

A typical prototype of this type of architecture is the GALNETII family of GALILEO TECHNOLOGIES, LTD. Port preprocessing and port-by-port-based filtering is provided by tough logic. This, however, is limited to only a few functions that cannot be changed or expanded or programmed by the user. In particular, the limiting factor of this type of architecture is the bandwidth of the high-speed connection (backplane). In addition, due to the limited bandwidth of the backplane, a significant reduction in the distribution rate of broadcast frames should be considered if more ports are to be served.

Forwarding clipping strategy was further developed in the so-called channel cell switches. Input data frames are divided into data blocks (cells of equal size), thereby providing a fixed transmission time within the distribution node of the switch. This makes it possible to ensure bandwidth independence on the size of the data frame, the amount of transmitted data and the number of ports. Cells are defragmented and reorganized at the destination port in order to restore the original data frame, usually done by copying the data frames to the output buffer. However, it should be noted that cell-based data distribution is not acceptable for safety critical applications, such as on-board electronics.

Finally, with regard to prototypes, a completely different method for distributing data frames is implemented in switches built on the basis of custom LSIs, as shown in Fig. 7. After analyzing the destination address or the destination address, a point-to-point connection is established through the switching matrix. Compared to the bus concept briefly described above, the switching matrix concept has the advantage that it allows multiple connections to exist simultaneously, that is, the bandwidth is increased upon request. However, this advantage can only be realized when there is no need to transmit frames to several ports at the same time (broadcasting). In this case, the full distribution of the data is blocked until each of the receiving ports is freed to receive the corresponding data frame.

A typical example of this type of architecture is the l-Cube LS100 / LS101 family. Ltd.

The technology of the switching matrix has the following advantages:

- High data performance, as many connections can exist simultaneously;

- Small delays;

- Serial switching is allowed;

- Simplicity of hardware implementation, that is, high reliability.

The disadvantages of this technology, on the other hand, are:

- A large number of pins is required (number of ports * 2 * bus width of the port interface), which means that scalability is limited;

- There is no concentration of bandwidth if frames should be sent to multiple ports to recipients;

- Failure of the switching matrix element entails a complete failure of the switch;

- There is no programmable port-based frame processing capability.

The aim of the invention is to improve fast Ethernet switches, as well as well-known methods for distributing Ethernet data frames, so that greater flexibility in managing data distribution with minimal delay can be achieved based on the concept of “save-and-forward”.

In accordance with the invention, a modular scalable structure for developing fast Ethernet switches is achieved by the use of high flexibility of individual transmission or broadcasting with a minimum number of packets, preferably in one packet, that is, in one transmission cycle, performing, in accordance with paragraph 1 of the claims, each Ethernet switch as an individually programmable module with one communication port.

Advantageous design options, modifications and improvements are the subject of the dependent claims and are explained by the necessary references to the figures in the description.

The method of allocating Ethernet data frames organized in a save-and-forward mode is characterized, in accordance with paragraph 8 of the claims, by the construction of a modular scalable structure consisting of individually programmable single-port communication modules that are organized for internal transmission of data frames in this way that each port, after receiving, saving and checking the integrity of the data frame, competes for access to the high-speed data exchange bus, for which the arbitration scheme based on but EPA and the port identifier. Then, the corresponding data frame is transmitted to one or more receiving (output) ports, preferably during one cycle of the data frame. The output ports independently decide, according to the status of the associated output buffer, the corresponding transmitted data frame should be received or discarded.

It is desirable that the data frames received by one communication module be filtered in real time, at least by bandwidth, frame size and field address fields, in particular, a control processor with a reduced instruction set (RISC). This is advantageous if the specified control process, in accordance with the invention, can be promptly changed in relation to the amount of filtering using resettable configuration parameters.

A particularly advantageous feature of the invention is that at least one of these single-port communication modules can be specially assigned, according to special configuration tables, either before, or during operation, to monitor the flow of information in order to filter and Capturing some data frames to analyze information flow without the cost of additional bandwidth on the backplane.

Another advantage of the invention is that any required maximum switch delay having a value less than a predetermined one is determined only by the size of the output queue of the single-port communication module. A certain advantage can be achieved by using the present invention if all or at least one of these single-port communication modules is configured to perform one or more administrative and / or control functions, for example, by executing a simple network management protocol (SNMP), a management database (MIB), in particular for organizing the Ethernet switch structure, providing the necessary network addresses and / or sequences of the application level, that is, available for the network level I am through any single-port communication module.

A particular advantage of the invention is that the data structures received from a particular single-port communication module are real-time filtered, at least with respect to bandwidth, frame size and frame addresses, by processing on a reduced set of instructions operating at the network layer two , that is, at the media access control (MAC) level.

In the future, in order to avoid redundant explanations for the knowledgeable reader, abbreviations will be used, which, however, are explained in the text.

The invention, advantageous details and design options will be described below with reference to the accompanying figures, in which:

Figure 1 shows a functional diagram of a single-port communication module according to the invention;

Figure 2 shows the blocks of interaction of functional elements of the software, as an example for typical single-port communication modules according to the invention;

Figure 3 shows a block diagram of a save-and-forward distribution;

Figure 4 shows the principle of the strategy “save-and-forward" according to the invention (already explained);

Figure 5 shows a centralized architecture for processing and sending incoming data frames using shared memory according to the prototype (already explained);

Figure 6 shows the distributed architecture for building Ethernet switches according to the prototype, including independent subnodes (already explained);

Figure 7 shows the construction of an Ethernet switch based on a custom LSI for point-to-point connections with a switching matrix according to the prototype (already explained).

The equipment structure of a typical embodiment in accordance with the invention and its interaction with typical software elements are described below with reference to Figs. 1, 2 and 3.

In the functional diagram of the unit of FIG. 1, Ethernet signals are fed, for example, through a shielded twisted pair cable to each direction with galvanic isolation by magnetic isolation in the transformer 12. Next, as a physical device, transceiver 13, that is, an Ethernet transmitter / receiver, responsible, among among other things, for converting serial code to parallel and vice versa, and for channel coding control. The transceiver 13 is connected to the Ethernet by the medium access control (MAC) unit 1, which contains a central processor element with a reduced instruction set (RISC CPU). In this block MAC + RISC CPU 1, which is responsible for structuring and processing incoming Ethernet frames, the central processing unit CPU performs step-by-step execution in each cycle of the instruction from the reduced set. Block 14 is a serial interface according to the RS-232 protocol, with asynchronous start and stop bits and parity corresponding to the COM interface of a personal computer with a maximum speed of 115 kbps. MAC + RISC CPU 1 is connected via a system bus consisting of, for example, 32 bits, on the one hand, with dual-port random access memory (DPRAM) 4, and on the other hand, with dynamic random access memory (DRAM) 3, which interacts with functional module of direct memory access (DMA) 2, which transfers memory - memory independently of CPU 1. The erasable software read-only memory (EPROM) 6 is connected via the system bus to CPU 1, DRAM 3 and DPRAM 4. DPRAM 4 and the subsequent allocation logic 5 frames, including speed yuschy arbiter 9, service-port communication modules forming the Ethernet switch according to the invention in Figure 3, connected on the one hand, with the high speed data bus 10, and on the other hand, via the high speed arbiter 9 - with the bus arbitration and control 11.

Typical software functional elements of single-port communication modules according to the invention are shown in FIG. 2. These functional elements of the software include:

- configuration tables 20 contained in an erasable read-only memory (EPROM) defining the functions of the modules;

- real-time operating system 21;

- loader 22 for loading configuration and tasks, checking them and communicating with the service / user unit;

- control function and application blocks 23, which are the module (modules) of the software for management, registration, etc. operational parameters;

- Simple Network Management Protocol (SNMP) in block 25, that is, a protocol for transmitting / exchanging operational parameters;

- Management Database (MIB) 24, including a system for classifying and coding operational parameters;

- a protocol stack unit 26, necessary for establishing a connection and exchanging data, including transmission control protocol (TCP), user data protocol (UDP) and Internet protocol (IP);

- many software modules 27 for monitoring and testing the network, as well as data traffic;

- hardware-software module 28 for switching and monitoring the port, i.e. for switching Ethernet frames and for displaying data exchange on a port / channel.

In this context, filtering information flow means filtering data according to certain criteria, for example, frame size, addresses, etc. Policing services relate to the management / monitoring of data flow in relation to a specific data rate and bandwidth.

The principle of operation is described below.

When using the programmable single-port communication modules according to the invention for fast Ethernet switches, the transmission process is strictly sequential in nature, corresponds to the work-conserving service disciplines and is organized in the “save-and-forward” mode mentioned above. Monitoring the integrity of the frame before the start of the transmission process involves a save-and-forward mechanism. To ensure maximum certainty, as required, for example, in on-board equipment, this project according to the invention involves the implementation of a strictly defined scheme.

The mechanism works in such a way that the port after receiving and processing the correct and full frame, i.e. after filtering the data stream, working out the strategy, it updates the (internal) header of this frame together with the corresponding sending information (CAM vector) in the frame buffer, that is, in DPRAM 4, so that this structure is marked for sending. This is accomplished by the high-speed frame allocation logic of switch 5, which, as shown in FIG. 1, also has access to DPRAM 4.

Upon completion of the contest for access to the high-speed internal data distribution bus of switch 10, the data / frame 5 distribution logic now transmits a complete frame to one (unicast) or several (multicast) output destination ports in one packet in accordance with a given CAM vector. Any output port independently decides, in accordance with the status of its output buffer, which is again the port associated with DPRAM 4, to accept or discard the sending frame in accordance with the internal delay requirements, explained in detail below.

As an example for a switch with 16 ports, the wire speed determines the internal frame transmission time of approximately 420 nsec per frame (i.e. 16 · 148800 frames of minimum size per second = 2.4 million frames per second).

The data transfer speed on the data distribution bus 10 is high enough to serve all ports ("for example, up to 16 ports), constantly transmitting 64-byte frames with wire speed. Due to the structure of a single-port module, port data stream filtering services can be easily implemented in real time, in a frame-by-frame mode, which assumes that the required transfer speed of the switch depends only on the transfer rate on bus 10 (connection panel).

The transmission process through the frame allocation logic 5 works as follows:

The internal data distribution mechanism works so that the port, having received and verified the full frame stored in DPRAM 4, competes for access to the high-speed data distribution bus 10 of the module. Decentralized high-speed arbiters 9 installed in the frame allocation logic node 5 of each port of the communication module, according to the fair arbitration scheme, provide access to bus 10 in accordance with the port number or its identifier. The port then sends the frame to one (unicast) or to multiple (multicast) output ports in one packet. Each output port, in accordance with the status of its buffer, independently decides whether to accept or discard the transmitted frame.

In accordance with the invention, the maximum latency can be configured, as explained below:

Latency is defined as the difference between the arrival time of the first bit of a frame and the departure time of the first bit of the last instance of the same frame from the switch, where the term “last instance” refers to broadcast, when the copied frames can leave the switch at different points in time.

As described below, any additional delay due to internal processing of the switch data and sending functions is zero, and any required maximum latency is less than tbd <so in the original - approx. > milliseconds is determined by the size of the output queue of the switch located only in DPRAM 4.

Example:

The required maximum latency should be 1 ms. For frames with 64 byte MAC data sizes, the size of the output queues should be calculated so that they can contain 149 frames, in strict accordance with the transmission speed in the environment of 100 Mbit / s with an inter-frame interval of 96 bits. For frames having a length greater than 64 bytes, the number of frames stored in the output queues correspondingly decreases. This is due to the fact that the number of frames that can be transmitted at a set speed in the medium of 100 Mbit / s, within the interval T _R = 1 ms decreases with increasing frame length.

As a result, DPRAM 4 output queues have a capacity

149 * (message block internal size for 64 byte frames) [bytes].

Depending on the status / level of the output queue (output queues), any port independently decides whether to accept or refuse a frame sent by the internal data distribution logic. The size of the output queue of a single-port communication module is configured by software or by loading configuration parameters during operation.

The following describes the programmable functions:

Ability to monitor data flow: assuming that the number of single-port modules is n, one or more of them can perform this task. The main purpose of such a control port is to filter and capture some frames for flow analysis.

The control port has a special configuration table that allows you to choose which destination MAC address among the group of input ports, except for the control port itself, should be copied to the control port output. Configuration table 20 allows you to select one or more MAC addresses that reach the switch and send them through the control port.

All ports that are not assigned to monitor data flow constantly send a copy of each received valid frame to the control port, without occupying the additional bandwidth of the high-speed data bus 10. This is due to the built-in broadcast properties of the data bus described above. The monitoring port configuration table determines which of these frames should be selected for transmission, for example, at the destination MAC address. All other frames are ignored. Therefore, changes to the monitoring configuration do not affect the transmission tables associated with all other ports.

Filtering abilities / flow strategies: Each received frame can be evaluated with respect to certain application parameters recorded in the configuration table in the EPROM 6 drive. Since the filtering / strategy functions are implemented programmatically due to the availability of one MAC + RISC CPU 1 per port, any algorithm can be applied depending on specific application requirements. In airborne equipment, important filtering services extend to (but are not limited to):

- bandwidth and jitter control;

- control the frame length;

- control of the frame address;

- control of frame data, and others.

For example, bandwidth control and jitter control can be performed by introducing the budget amount associated with the frame, which is based on the following parameters:

- bandwidth interval (expressed in seconds) associated with a specific MAC address,

- the maximum value of the budget according to the jitter value, expressed in seconds, associated with a specific MAC address.

The main concept and purpose of the described architecture of the switch according to the invention is to provide optimal bandwidth and data processing performance for all functional blocks between any pair of input and output ports, so that a sustained wire speed can be achieved. This includes the performance of the filter function / port data flow strategy, mainly achieved (as an example) by the 32-bit MAC + RISC CPU 1 allocated to each port.

You can give an example to evaluate the work:

The maximum load on the input port of the switch is formed when receiving frames of the minimum size, for example, 64 bytes of the MAC data field corresponding to 18 bytes of user data using the UDP / IP protocol, with a minimum inter-frame gap of 12 bytes. At a speed of information transfer in the medium, for example, 100 Mbit / s, this gives 149 frames / ms. According to the MAC frame structure of the IEEE 802.3 standard and without the 802.1 p / 1Q header attribute of 4 bytes, the total MAC frame size is 84 bytes.

Ethernet MAC devices installed in each port of the switch are capable of storing not only the MAC protocol data unit, but also the so-called internal message block, which also includes a CRC field, source and destination MAC addresses, type / length field, as well as other special information, such as time stamps, status, pointers, the CAM vector, etc., used to control the switches. In the worst case, the minimum size of the internal message block consists of 128 bytes (= 32 · 4 bytes, that is 32 bit word <so in the original, approx. Transl.>), The processing power of the RISC processor needed to control the bandwidth, that is, the strategy the budget calculation, as well as for updating the message block, will reach the following instructions per second (IPS) value:

The remaining typical stream filtering function, that is, frame filtering by destination MAC address, can be estimated at an additional ~ 2.25 MIPS, so the total processor load reaches ~ 10 MIPS for a port operating at full wired speed and a minimum frame size. When using one MAC + RISC processor 1 per port at 10 MIPS, real-time frame filtering in frame-by-frame mode can be provided even at full wire speed.

The time required to filter the data stream of one frame will be

10 MIPS / 149 · 10 ³ frames ≈67 IPS / frame, which gives 1.34 μs with a processor cycle time of 20 nsec, that is, for a 50 MHz RISC processor 1; at 33 megahertz, the calculation time reaches 67 · 33 nsec = 2.2 μsec.

The received frames are transmitted to DRAM 3 by the direct memory access controller, which is part of MAC + RISC CPU 1. At full wire speed, frames with 64 bytes of MAC data have a frame transmission duration of ~ 5.76 μs, followed by an interval of 0.96 ms for 12 octets of the frame interval . This gives a total minimum transmission time of 6.72 μs per frame.

Thus, only 1.34 / 6.72 = 20% (for 2.2 / 6.72 = 33%, respectively) of the minimum frame transmission time is used, which actually means that any additional delay due to the internal processing of the switch data and the sending function is zero, and the required the maximum latency of less than 1 ms is determined only by the length of the output queue of the switch.

This statement is valid only at time t ₀ = 0 for a frame that is completely transmitted and stored in DPRAM 4. Then, the filtering process immediately starts and is performed in parallel with the process of obtaining the next frame in MAC + RISC CPU 1 (pipeline action).

The following are the features of the network management function:

The modular architecture of the switch according to the invention allows access to internal public information through a simple network management protocol (SNMP), to a management information database (MIB) by, for example, using a user data / Internet protocol (UDP / IP) and a simple network management protocol on MAC + RISC CPU 1 of any port, which is indicated by reference 8 in FIG. 2. The interface is organized so that the SNMP protocol is used to obtain this information.

To ensure that the internal SNMP traffic does not occupy too much of the bandwidth of the switch connecting board, which can reduce the speed, i.e. increase the waiting time, instead, the shared memory bus of the direct memory interface (DMI) 2 can be used. The DMI 2 block provides separation of, for example, the 16-bit bus and allows the exchange of data stored in the local memory of each processor, that is, DRAM 3, EPROM 6 and DPRAM 4.

Further, in the event of a port failure as part of its switching services, this approach still allows you to control the MAC + RISC CPU 1, receiving status / error information on the corresponding defective port, which will not provide, for example, a mixed data stream with status information on the connection board.

Claims (14)

1. The modular scalable architecture of the fast Ethernet switch, characterized in that the Ethernet switch is made in the form of many individually programmable single-port communication modules for access to a common distribution bus (10), while each single-port communication module contains a programmable microcontroller (1), made as a unit Ethernet media access control (MAC), containing a processor with a reduced set of instructions (RISC CPU), and a logical device (5) for the distribution of data frames, providing for real-time processing nom time and transfer to the addressed destination ports of Ethernet data frames arriving on said single-port communication module. 2. The architecture of the fast Ethernet switch according to claim 1, characterized in that each individually programmable single-port communication module contains a dual-port frame buffer (4), made in such a way as to interact, on the one hand, with this programmable microcontroller (1) and, with on the other hand, with the indicated logical device (5) for distributing the data in such a way that the received correct data frame is updated, at least in terms of transmission information (CAM vector) in the specified frame buffer (4), in order to be suitable for transferring cottages through said data distribution bus (10). 3. The architecture of the fast Ethernet switch according to claim 2, characterized in that it contains an arbitration logic device (9) arranged in such a way that it is decentralized and contained in each of these individually programmable single-port communication modules, while this device is interconnected with the corresponding one from logical devices (5) for distributing data frames to provide access to valid data frames to said data distribution bus (10) according to a fair distribution of access rights and scheme ignalov control based on port numbering or identification. 4. The architecture of the fast Ethernet switch according to claim 1, characterized in that the said programmable microcontroller is configured to access for individual programming through the interface unit. 5. The architecture of the fast Ethernet switch according to claim 4, characterized in that said interface unit is an RS-232 interface. 6. The architecture of the fast Ethernet switch according to claim 1, characterized in that it further comprises a direct memory interface (DMI 2) associated with DRAM (dynamic random access memory) (3) for direct memory-memory operations and / or control data exchange and / or status information in the event of a failure in the logical device (5) of the distribution of data frames or data bus (10). 7. A method for distributing Ethernet data frames in a “store-and-send” mode using a modular scalable architecture of individually programmable single-port communication modules, including the following operations: providing the specified modular scalable architecture of individually programmable single-port communication modules organized for internal distribution of data frames in this way that each port after receiving, saving and checking the integrity of the data frame competes for access to the high-speed bus data distribution according to a fair arbitration scheme based on the numbering or identification of ports, transmitting the corresponding data frame to at least one output port for a certain number of cycles of the data frame, and performing a decision operation in such a way that each output port is independently the friend decides in accordance with the status of its output buffers to accept or reject the corresponding transmitted data frame. 8. The method according to claim 7, characterized in that the said number of cycles of the data frame is one and only one, regardless of the number of output ports simultaneously serviced by the said individually programmable single-port communication module. 9. The method according to claim 7, in which the data frames received by said individually programmable single-port communication module are processed in real time by filtering at least according to the bandwidth, frame size and frame addresses by means of a control process, at the network layer 2 ( network access level - MAC) using a reduced set of commands. 10. The method according to claim 9, characterized in that the said control process is variable in terms of the amount of filtering using resettable configuration parameters. 11. The method according to claim 7, characterized in that at least one of the aforementioned individually programmable single-port communication modules can be assigned by special configuration tables before and / or during the operating time to monitor the data flow in order to provide filtering and capture of some frames data to analyze data flow. 12. The method according to any one of the preceding paragraphs, characterized in that any desired switching delay value that is less than a predetermined time is determined only by the length of the output queue of an individually programmable single-port communication module. 13. The method according to p. 12, characterized in that at least one individually programmable single-port communication module is configured to perform at least one administration / management function. 14. The method according to item 13, wherein said at least one administration / management function is carried out by a simple network management protocol (SNMP) and / or management database (MIB) to represent access to information about the architecture of the Ethernet switch, providing the appropriate network addresses and application level (sequentially for network level 7), accessible through any individually programmable single-port communication module.

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