RU2253891C2 - System for actualization of databases for information-marketing centers of electronic trade - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: system has block for receiving actualization files, first and second devices for selecting supporting database record address, device for selecting address of user workplace block for selecting addresses of database record, data dispensing block, reverse counter, first and second codes comparison blocks, two registers, AND elements, OR elements and delay elements.

EFFECT: higher speed of operation.

8 dwg

Description

The invention relates to computing, in particular to a system for updating databases of information and marketing centers of electronic commerce.

Known systems that could be used to solve the problem (1, 2).

The first of the known systems contains data reception and storage units connected to control and data processing units, search and selection units connected to data storage and display units, the synchronizing inputs of which are connected to the outputs of the control unit (1).

A significant drawback of this system is the impossibility of solving the problem of updating data stored in memory in the form of relevant documents at the same time as solving the problem of delivering the contents of these documents to users in real time.

Another system is known, comprising data receiving units whose outputs are connected to a memory unit and to a data processing unit, a time interval selection unit whose outputs are connected to a data receiving unit, to a user request receiving unit and to a memory unit, and to a data processing unit the outputs of which are connected to one of the inputs of the switching unit of the data output channels, the other inputs of which are connected to the selection of time intervals, and the outputs are the outputs of the system (2).

The last of the above technical solutions is closest to the described.

Its disadvantage is the low speed of the system, due to the fact that the search for data to be updated is carried out throughout the database, which leads to unreasonable loss of time and the inability to implement the electronic commerce mode in real time.

The purpose of the invention is to improve system performance by eliminating the search for data addresses to be updated, and implementing direct addressing of changes to data records in the databases of information and marketing centers.

This goal is achieved by the fact that in the known system containing the block for receiving update files, the information input of which is the first information input of the system, the first and second synchronizing inputs of the block are the first and second synchronizing inputs of the system, and the first information output of the block is the information output of the system, the first a device for selecting a reference address of a database record, the information input of which is connected to the second information output of the update file receiving unit, sync the synchronizing input is connected to the synchronizing output of the update files receiving unit, the information output of the device is connected to one of the inputs of the OR elements of the group, and the synchronizing output of the selection device of the reference address of the database record is connected to one input of the first OR, the output of which is connected to the input of the first delay element, the output which is the first synchronizing output of the device, the first register, the information input of which is the second information input of the system, the synchronizing input connected to the output of the And element, one input of which is the third synchronizing input of the system, and the other is connected to the control output of the update files receiving unit, the second OR element, the output of which is connected to the input of the second delay element, the output of which is the second synchronizing output of the system, the second register, the information input of which is the third information input of the system, the synchronizing input is the fourth synchronizing input of the system, and the output is connected to one information input of the unit and the issuance of data, the information outputs of which are the information outputs of the system group, the third OR element, one input of which is connected to the synchronizing output of the first selection device of the reference address of the database record, the device for selecting the address of the user's workstation, the information input of which is connected to one output of the first register, the synchronizing input is connected to the fourth synchronizing input of the system, and the information and synchronizing outputs of the device for selecting the address of the workplace The fourth and fifth elements are connected to other information and synchronization inputs of the data output unit, respectively, the first code comparison unit is introduced, the information input of which is connected to the third information output of the update file receiving unit, the synchronization input is connected to the output of the first delay element, the first output of the first the code comparison unit is connected to the third synchronizing input of the update files receiving unit, to another input of the first OR element, and to one input of the fourth e OR, the second output of the first code comparison unit is connected to one input of the fifth OR element, and the third output of the block is the third synchronizing output of the system, the second code comparison unit, the information input of which is connected to the fourth information output of the update file receiving unit, the synchronization input is connected to the second the output of the first code comparison unit, the first output of the second code comparison unit is connected to the fourth synchronizing input of the update file reception unit, and the second output of the unit is connected connected to another input of the fifth OR element, the output of which is connected to the first installation input of the update file reception unit, and to the second installation input of the update file reception unit, a reversible counter, the information input of which is connected to the output of the OR elements of the group, the synchronizing input is connected to the output of the third element OR, the summing input is connected to the output of the fourth OR element, the installation input is connected to the output of the fifth OR element, and the input of the reverse counter is the address output of the system, the second a triple of selection of the database record address, the information input of which is connected to another output of the first register, the synchronizing input is connected to the output of the AND element, the first information output of the device is connected to other inputs of the OR elements of the group, and the synchronizing output of the device is connected to other inputs of the second and third elements of OR , and a database address selection block, the information input of which is connected to another output of the second selection device of the reference address of the database record, synchronizing the input to connected to the synchronizing output of the second selection device for the reference address of the database record, the first and second control inputs of the block are the first and second control inputs of the system, and the third control input of the block is connected to the control output of the block for receiving update files, while the first output of the block is connected to other inputs the second and fourth OR elements, and the second output of the block is connected to the subtracting input of the reverse counter and another input of the second OR element.

The invention is illustrated by drawings, where Fig. 1 shows a structural diagram of a system, Fig. 2 shows an example of a specific structural embodiment of a block for receiving update files, Fig. 3 is an example of a specific structural embodiment of a first selection device of a reference address of a database record and an address selection device the user's workplace, figure 4 is an example of a specific structural embodiment of the second device for selecting the reference address of the database record, figure 5 is an example of a specific structural Fig. 6 is an example of a specific structural embodiment of a second code comparison block; Fig. 7 is an example of a specific structural embodiment of a database address selection block; Fig. 8 is an example of a specific structural embodiment of a data output block.

The system (Fig. 1) contains a block 1 for receiving update files for databases of information and marketing centers (IMC), the first 2 and second 3 devices for selecting the reference address of the database record, device 4 for selecting the address of the user's workstation, the first 5 and second 6 registers, the first 7 and second 8 code comparison blocks, a reverse counter 9, a database address selection block 10, a data output block 11, a first 12, a second 13, a third 14, a fourth 15 and a fifth 16 OR elements, an AND element 17, a group of 18 OR elements The first 19 and second 20 delay elements.

1 also shows the first 21, second 22 and third 23 information inputs of the system, the first 24, second 25, third 26, fourth 27 synchronizing inputs of the system, the first 28 and second 29 control inputs of the system, as well as the information output 30 of the system, address 31 system outputs, the first 32, second 33 and third 34 synchronizing outputs of the system, and information outputs 35-37 of the system group.

Block 1 (figure 2) contains registers 40-43, trigger 44, elements 45-47 OR.

The drawing also shows the first 21 information input of the block, which is the first information input of the system, the first 24 and second 25 clock inputs of the block, which are the first and second clock inputs of the system, the third 50 and fourth 51 clock inputs of the block, the first 52 and second 53 installation inputs of the block as well as synchronizing 54, control 55, and first 56, second 57, third 58 and fourth 59 information outputs of the block.

Devices 2, 3, 4 are identical (FIGS. 3 and 4) and comprise a memory unit 71 made in the form of read-only memory, a decoder 72, AND elements 73-75, OR element 76, and delay elements 77-78. The difference between the device 3 is only in that the outputs of the memory block are conditionally divided into two outputs 81 and 83.

The drawing also shows information 79 and synchronizing 80 inputs of the block, as well as information 81, 83 and synchronizing 82 outputs of the block.

Block 7 (figure 5) contains a counter 90, a comparator 91, and delay elements 92, 93, and 94.

The drawing also shows the information 95 and synchronizing 96 inputs of the block, the first 98 and second 99, and the third 100 synchronizing outputs.

Block 8 (Fig.6) contains a comparator 101, a counter 102, elements 103, 104 delay.

The drawing also shows information 105 and synchronizing 106 inputs of the block, the first 107 and second 108 synchronizing outputs.

Block 10 (Fig. 7) contains a register 110, a counter 111, comparators 113, 114, first 115 and second 116 AND elements, first 117, second 118 and third 119 OR elements, first 120, second 121 and third 122 delay elements. The drawing also shows the information 125 and synchronizing 126 inputs of the block, the first 28, second 29 and third 127 control inputs of the block, as well as control 128 and 129 outputs of the block.

Block 11 (Fig. 8) contains a register 140, a decoder 141, a first 142, a second 143, and a third 144 of a group of AND elements, a delay element 145. The drawing also shows the first 146 and second 147 information and synchronizing 148 inputs of the block, as well as information 35-37 outputs of the group of outputs of the block and system.

All nodes and elements of the system are made on standard potential-impulse elements. To simplify the drawing, the chain of installation of nodes and blocks in the initial state is not shown in the drawing.

The core of the e-commerce system is a network of information and marketing centers, which provides communication:

- at the level of external interaction with the Government of the Russian Federation, ministries and departments, governments of republics, regions, constituent entities of the Federation and the federal center of electronic commerce;

- at the level of internal interaction within the zone serviced by the IMC with entrepreneurs and associations engaged in the supply of products and services.

At the same time, in the process of creating the IMC, their role is to make the transition from conventional (paper) methods for registering trade operations to electronic document management. Electronic document management changes the dynamics of trade operations and helps to increase the efficiency of the economy.

Information and marketing support of the market of goods and services on a national scale in Russia is focused on creating conditions conducive to achieving the following goals:

- reducing the number of intermediaries, accelerating the promotion of products and services in the markets, and as a result, increasing the efficiency of the use of working capital, reducing costs and increasing the profits of producers;

- increased competition among manufacturers, ensuring an increase in the quality of goods and services, lowering their cost and selling prices, increasing sales, increasing demand for electronic trading methods and integrated enterprise management information systems;

- reduction of time spent on searching and obtaining the necessary legal and market information, information and marketing services, as well as on the design of production, technical and trade documentation, including obtaining various permits, licenses, certificates, etc .;

- protection of national producers from the expansion of imported products in virtual electronic markets, overcoming the technological dependence of domestic enterprises in the field of IT-technologies;

- comprehensive development and support of the national industry of IT-technologies;

- a significant (up to 40-50%) increase in regular users of information telecommunication networks from among medium and small enterprises;

- the formation of a single, accessible and secure information space of data on supply and demand for the entire spectrum of goods, products, works and services;

- the use of objective market information to implement effective economic levers of government in executive bodies of all levels, to improve the quality of current and future planning, to introduce methods for forecasting and modeling the results of decisions;

- ensuring the widespread adoption of e-commerce methods, including e-commerce for government needs.

Today, the prerequisites necessary for rethinking the methodology and ways of organizing information and marketing support for market entities have already developed. The formation and distribution of data sets with primary information about producers and consumers is no longer a priority. It is necessary to develop and implement effective methods, tools and systems for organizing constant information flows of exchange of market data and electronic documents between subjects of market relations, ensuring the joint formation and use of accessible data arrays in a single electronic information and communication space.

Information and marketing centers are the basis for creating organizational, structural and technological conditions for direct interaction between manufacturers and consumers on the current telecommunication and technical base, with the lowest possible cost for telecommunication services.

Their functioning provides the possibility of direct, reliable and affordable exchange of data on supply and demand between producers and consumers with various capabilities and degrees of informatization, and also allows the formation of a unified system of marketing services, which is a centralized, geographically distributed, nationwide information and marketing structure .

The All-Russian system of IMC is designed to carry out systematic information and marketing activities throughout the country in order to ensure free and priority promotion of products and services of national manufacturers both within the country and abroad, including for public procurement at the federal and regional levels.

The system operates as follows.

During the work of geographically distributed information and marketing centers, each of them concludes contracts between bidders for the purchase (sale) of certain consignments of goods put up for sale in all information and marketing centers (IMC). As a result of these procedures, information on the quantity of goods put up for sale by the relevant seller at all other IMCs should be adjusted by amending the relevant database records of all information and marketing centers.

For this purpose, in the information and marketing center, where an agreement has been concluded for the sale (purchase) of consignments of relevant goods, according to the results of each transaction, an update file for the databases of all other IMCs is formed, having the following structure:

The generated database update file from the output of the information and marketing center, which initiated the database update process in all other IMCs, is transferred and written to the buffer memory (not shown) of each IMC, from where it arrives at the information input of 21 systems. The buffer memory is made in the form of a stack, which ensures the presentation of the next record on its output after reading the previous one.

From the input 21 of the system, the update file is sent to the information input of block 1, from where it is fed to the corresponding information inputs of registers 40-43. At the same time, with the clock pulse from input 24 passing through the corresponding elements 45-47 OR, the first three sections of the file structure are recorded in the corresponding registers 40-42, and the clock section from the input 25, the fourth section of the file structure is written in register 43.

At the same time, the same synchronizing pulse from the output of the OR element 45, firstly, is supplied to the single input of the trigger 44, setting it to a single state, in which a low blocking potential will be issued to the output 61 of the block 1, preventing users from accessing the database server during its update.

Secondly, the synchronizing pulse from the output of the OR element 45 passes to the output 54 of the block and then goes to the synchronizing input 80 of the block 2, the information input 79 of which from the output 56 of the register 40 receives the seller identifier code.

The decoder 72 decodes the code of the identifier of the seller, giving out one of its outputs high potential. For definiteness, we assume that a high potential is received at one input of element 75 I.

In parallel with this, the synchronizing pulse from the input 80 of block 2 is delayed by the element 77 for the time the code is entered into the register 40 and the decoder 72 is activated, and then it polls the states of elements 73-75 I.

Given the fact that only one element And will be open at one input, then passing through this element And, the clock pulse arrives, firstly, at the read input of a fixed memory cell of read-only memory 71, where the reference address code of the first memory cell of this seller is stored in the server’s database, and reads its contents through the output 81 of the block 2 elements 16 OR groups to the information input of the reverse counter 9.

Secondly, the read impulse, having passed the OR element 76, is delayed by the delay element 78 for the time of reading the contents of the fixed ROM cell, and then from the output 82 of the block 2, passing the 14 OR element, it goes to the synchronizing input of the reverse counter 9, fixing the reference address code in it the first memory location of this seller in the server database.

Thirdly, the same impulse, having passed the OR element 12, is delayed by the delay element 19 for the time the reference address code is entered into the reverse counter 9 and then goes through the system output 32 to the input of the first server interrupt channel. By this signal, the server goes to the polling routine of register 42 of block 1 to record its contents in the server database at the address generated at the output 31 of the reverse counter 9.

At the same time, the pulse from the output of the delay element 19 goes to the input 96 of block 7, where it is delayed by the element 92 during the polling and recording by the server of the contents of the register 42 into the database and goes to the counting input of the counter 90, fixing the unit in the counter as the fact of updating the first record in the server database.

In addition, the same pulse is delayed by the delay element 93 for the response time of the counter 90 and is supplied to the synchronizing input of the comparator 91, comparing the number of records of this seller in the register 41 with the readings of the counter 90 entries.

If the number of entries in the counter 90 is less than the number of entries in the register 41, then an impulse appears at the output 98 of the comparator 91, which, firstly, passes through the 15 element OR to the summing input of the reverse counter 9, thereby forming the next write address in the server database and, secondly, it is fed to the input 50 of block 1 and then through the element 47 OR it goes to the synchronizing input of the register 42, entering into it the next record of the update file from the buffer memory.

The same impulse through the OR element 12 is again delayed by the delay element 19 for the time the new content of the record was entered into the register 42 and again fed through the system output 32 to the input of the first server interrupt channel. By this signal, the server again switches to the polling routine of register 42 of block 1 and writing its contents to the server database at the address generated at the output 31 of the reverse counter 9.

At the same time, the pulse from the output of the delay element 19 again goes to block 7, where it is delayed by the element 92 during the polling and writing by the server of the contents of the register 42 to the database and arrives at the counter input of the counter 90, fixing the next unit in the counter as the fact of updating the next record in the server database.

In addition, the same pulse is delayed by the delay element 93 for the response time of the counter 90 and is again fed to the synchronizing input of the comparator 91, comparing the number of records of this seller in the register 41 with the readings of the counter 90 entries.

The described process of recording the content of entries in the update file in the server database continues until the number of entries in the register 41 of block 1 is equal to the number of records recorded by the counter 90 of block 7. The specified time will be fixed by issuing a pulse at the output 99 of comparator 91.

This pulse, firstly, through the OR element 16 is supplied to the installation inputs of the reverse counter 9 and block 1 (via input 52) and sets the reverse counter 9 and registers 40-42 of block 1 to its initial state.

Secondly, this pulse is delayed by the delay element 94 during the installation of registers 40-42 of block 1 and counter 9 in the initial state and is output to the system output 34, from where it arrives at the control input of the buffer memory (not shown in the drawing). By this signal, the first content record of the next seller, which is part of the update file, will be presented at the output of the buffer memory.

Thirdly, the same pulse goes to input 106 of block 8, from where it goes to the counting input of counter 102, fixing the unit in the counter as a fact of updating all the records of the first seller in the server database.

In addition, the same pulse is delayed by the delay element 103 for the response time of the counter 102 and is supplied to the synchronizing input of the comparator 101, which compares the code of the number of sellers in register 43 coming from the input 105 of block 8 with the readings of the counter 102 of sellers.

If the readings of counter 102 are less than the code of the number of sellers presented in register 43, then an output appears on the output of the comparator 107, which through the input 51 of block 1 and the elements 45-47 OR is fed to the synchronizing inputs of the registers 40-42, recording the update file in them the next seller from the buffer memory, and the process of updating the records of the next seller in the server database will continue as described until all the records of all sellers from the update file are updated.

The end of the database updating process will be fixed at the moment of the appearance of a pulse at the output 108 of the comparator 101 of block 8, which will reflect the fact that the code of the counter 102 is equal to the code of the number of sellers in the register 43 of block 1.

This pulse, firstly, through the OR element 16, is supplied to the installation inputs of the reverse counter 9 and block 1 and sets the reverse counter 9 and registers 40-42 of block 1 to its initial state.

Secondly, the same pulse from the output 108 through the input 53 of block 1 is supplied to the installation input of the register 43 and the installation input of the trigger 44, returning them to their original state, in which the trigger 44 removes the inhibitory potential from the input of the element 17 AND, indicating that that the process of updating the database of this information and marketing center is completed, and system users can now get all the information they are interested in from the server database.

The structure of the codogram formed at workstations has the following form.

To obtain relevant information from the IMC database, each user on his AWP selects a seller offering the product of interest to him, and presses the “View” key. In this case, the seller’s identifier codes and the user's workstation identifier through the input 22 go to register 5, where they are entered by the synchronizing pulse from input 26. From the first output of the register 5, the seller’s identifier code goes through the input 79 of block 3 to the input of the decoder 72.

Decoder 72 decrypts the seller’s code, giving out one of its outputs high potential. For definiteness, we assume that a high potential is received at one input of element 75 I.

In parallel with this, the synchronizing pulse from the output of element 17 AND through the input 80 of block 3 is delayed by element 77 for the time the code is entered in register 5 and the decoder 72 is activated, and then it polls the states of elements 73-75 I.

Given the fact that only one element And will be open at one input, then after passing through this element And, the clock pulse arrives, firstly, at the read input of a fixed memory cell of read-only memory 71.

In a fixed memory cell, the code of the reference address of the first memory cell of a given seller is stored in the server database and the code of the number of entries in the server database related to the trading offers of this seller.

The structure of the codogram is as follows.

The code of the reference address of the first memory cell and the code of the number of records of this seller are read from a fixed memory cell and fed to different outputs of the device 3.

The code of the reference address of the first memory cell from the output 81 of the device 3 through the elements 18 OR groups is fed to the information input of the reverse counter 9.

In parallel with this, the read pulse of the fixed memory cell, having passed the OR element 76, is delayed by the delay element 78 for the time of reading the contents of the fixed ROM cell. Further, from the output 82 of the device 3, this pulse enters through the element 14 OR to the synchronizing input of the reverse counter 9, fixing in the counter the code of the reference address of the first memory cell of this seller in the server database.

In addition, the same pulse from the output 82 of the device 3 passes through the OR element 13 and is delayed by the delay element 20 while the reference address code is entered into the counter 9 and from the system output 33 it is supplied to the second server interrupt input. According to this signal, the server goes to the subprogram for interrogating the contents of the memory cell at the address generated on the address output of the system 31 and issuing the read data through the system input 23 to the information input of the register 6, where they are entered by the server synchronizing pulse received at the system input 27.

The code of the number of records of the selected seller from the output 83 of the device 3 is supplied through the input 125 of the block 10 to the information input of the register 110, which is also recorded by the pulse from the output 82 of the device 3.

In parallel with this, the user workstation identifier code from the second output of the register 5 enters through the input 79 of the device 4 to the input of the decoder 72.

The decoder 72 decrypts the ID code of the user's workstation, giving out one of its outputs high potential. For definiteness, we assume that a high potential is received at one input of element 75 I.

In parallel with this, the synchronizing pulse from input 27 through input 80 of block 4 is delayed by element 77 for the duration of the operation of decoder 72 and then polls the states of elements 73-75 I.

Given the fact that only one element And will be open at one input, then passing through this element And, the clock pulse arrives, firstly, at the read input of a fixed memory cell of read-only memory 71, where the address code of the user's workstation is stored, and reads it through the output 81 of the device 4 to the information input 146 of the block 11.

Secondly, the same read pulse, having passed the OR element 76, is delayed by the delay element 78 for the time of reading the contents of a fixed ROM cell. Further, from the output 82 of the device 4, this pulse enters through the input 148 of block 11 to the synchronizing input of the register 140, fixing the address code of the user workstation in the register.

The decoder 141 decrypts the address code of the user's workstation and with high potential at one of its outputs opens the And elements of one of the groups 142-144. Simultaneously with this pulse from the input 148 of block 11, delayed by the delay element 145 for the duration of the decoder 141 operation, the code of the first read write from the output of register 6, passing through the input 147 of block 11 and the corresponding group of elements And 132-134, through the corresponding output 35-37 issued to the user's workstation.

The user is given the opportunity to view all the records of the selected seller in the server database and draw the appropriate conclusions on his trading offers.

To do this, the user uses the “Forward” and “Back” keys, the signals from which are fed to the control inputs 28, 29 of the system, respectively.

Given that the user can view the records of the selected seller only after the update mode of the server database is completed, the high potential of the trigger 44 of block 1 coming from the output of 55 block 1 to the input of 127 block 10 elements 115, 116 And will be opened.

When you press the “Forward” key, the pulse from the input 28 of the system passes through the element 115 AND to the counting input of the counter 111, fixing the number of views of records. This number of record views is compared by the comparator 113 with the number of records of the seller recorded in the register 110, according to the signal from the output of the delay element 120, which delays the pulse from the output of the element 115 AND at the time of operation of the counter 111.

If the number of views is less than the specified number of entries in the register 110, then a pulse is generated at the output 130 of the comparator 113, which passes through the element 118 OR to the output 128 of the block 10 and then through the element 15 OR to the summing input of the reverse counter 9, which forms the next read address at output 31 .

In addition, the same pulse, passing through the OR element 13 and the delay element 20, delaying this pulse for the duration of the operation of the reverse counter, passes to the output 33 and then again goes to the input of the second channel of the server interrupt.

By this signal, the server again switches to the subprogram for interrogating the contents of the memory cell at the address generated at the address output of the system 31 and issuing the read data through the input 23 of the system to the information input of the register 6, where they are entered by the synchronizing pulse of the server arriving at the input 27 of the system.

The described process of reading records from the server database and issuing them to the user's workstation continues until the number of records in register 110 of block 10 is equal to the number of records read from the database recorded by counter 111. The indicated moment will be recorded by issuing an impulse to the output 131 of the comparator 113.

The pulse from the output 131 of the comparator 113, firstly, through the element 119 OR enters the output 129 of the block 10 and then to the subtracting input of the reversing counter 9, reducing its readings by one. In addition, the same pulse, passing through the OR element 13 and the delay element 20, delaying this pulse for the duration of the operation of the reverse counter, passes to the output 33 and then again goes to the input of the second channel of the server interrupt.

By this signal, the server again switches to the subprogram for interrogating the contents of the memory cell at the address generated at the address output of the system 31 and issuing the read data through the input 23 of the system to the information input of the register 6, where they are entered by the synchronizing pulse of the server arriving at the input 27 of the system.

Secondly, the same pulse from the output 131 of the comparator 113 is delayed by the delay element 122 for the duration of the pulse and through the element 117 OR enters the subtractive input of the counter 111, reducing its readings.

After that, the user proceeds to the reverse view of seller’s records by pressing the “Back” key. The pulse from the input 29 through the element 116 OR, firstly, enters the subtracting input of the counter 111, and, secondly, after a delay by the element 121 for the duration of the operation of the counter 111 is fed to the synchronizing input of the comparator 114. By this signal, the comparator 114 compares the readings of the counter 111 with a “zero”. If the readings of the counter 111 are greater than zero, then a signal is generated at the output 132 of the comparator 114, which, through the OR element 119, is output to the output 129 of the block 10 and then to the subtracting input of the reverse counter 9.

If the readings of the counter 111 are equal to zero, then a pulse is generated at the output 133 of the comparator 114, which passes through the 118 element OR to the output 128 of the block 10 and then goes to the summing input of the reverse counter 9, putting the user in direct viewing of seller records in the database server.

Thus, the introduction of new nodes and blocks made it possible to significantly increase the system performance by eliminating the search for data addresses to be updated, and by directly addressing the implementation of data record changes in the databases of information and marketing centers.

Sources of information

1. Japanese Patent No. 4-38021. from 06/23/92.

2. US Patent No. 5136708. M.cl. G 06 F 15/16 from 08/04/92.

Claims (1)

The database update system of information and marketing centers of electronic commerce, containing a block for receiving update files, the information input of which is the first information input of the system, the first and second synchronization inputs of this block are the first and second synchronizing inputs of the system, and the first information output is the information output of the system, the first device for selecting the reference address of the database record, the information input of which is connected to the second information output of the unit As for receiving update files, the synchronizing input is connected to the synchronizing output of the updating file receiving unit, the information output of the specified device is connected to one of the inputs of the OR elements of the group, and the synchronizing output is connected to one input of the first OR, the output of which is connected to the input of the first delay element, the output of which is the first synchronizing output of the system, the first register, the information input of which is the second information input of the system, the synchronizing input is connected to the output of the And element, one input of which is the third synchronizing input of the system, and the other is connected to the control output of the update files receiving unit, the second OR element, the output of which is connected to the input of the second delay element, the output of which is the second synchronizing output of the system, the second register, information whose input is the third information input of the system, the synchronizing input is the fourth synchronizing input of the system, and the output is connected to one information input of the issuing unit for data, the information outputs of which are the information outputs of the system group, the third OR element, one input of which is connected to the synchronizing output of the first device for selecting the reference address of the database record, the device for selecting the address of the user's workstation, the information input of which is connected to one output of the first register, the synchronizing input connected to the fourth synchronizing input of the system, and the information and synchronizing outputs of the device for selecting the address of the user's workplace with the fourth and fifth OR elements, unified with other information and synchronization inputs of the data output unit, respectively, characterized in that it contains a first code comparison unit, the information input of which is connected to the third information output of the update file reception unit, the synchronization input is connected to the output of the first delay element , the first output of the first code comparison unit is connected to the third synchronizing input of the update files receiving unit, to another input of the first OR element, and to one input one of the fourth OR element, the second output of the first code comparison unit is connected to one input of the fifth OR element, and the third output of the block is the third synchronizing output of the system, the second code comparison unit, the information input of which is connected to the fourth information output of the update file receiving unit, the synchronization input is connected to the second output of the first code comparison unit, the first output of the second code comparison unit is connected to the fourth synchronizing input of the update file reception unit, and the second you the course of the second code comparison unit is connected to another input of the fifth OR element, the output of which is connected to the first installation input of the update file reception unit, and to the second installation input of the update file reception unit, a reverse counter, the information input of which is connected to the output of the elements OR groups, the synchronizing input connected to the output of the third OR element, the summing input is connected to the output of the fourth OR element, the installation input is connected to the output of the fifth OR element, and the input of the reverse counter is is the address output of the system, the second device for selecting the address of the database record, the information input of which is connected to another output of the first register, the synchronizing input is connected to the output of the AND element, the first information output is connected to other inputs of the elements of the OR group, and the synchronizing output is connected to other inputs of the second and the third OR element, and a database address selection unit, the information input of which is connected to another output of the second device for selecting the reference address of the database record, synchronization the main input is connected to the synchronizing output of the second selection device for the reference address of the database record, the first and second control inputs of the database address selection block are the first and second control inputs of the system, and the third control input is connected to the control output of the update file receiving unit, while the first output the database address selection block is connected to other inputs of the second and fourth elements OR, and the second output is connected to the subtracting input of the reverse counter and another input of the second element NTA OR.

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