RU2237972C2 - Frequency synthesizer - Google Patents

Abstract

FIELD: radio communications technology.

SUBSTANCE: device has clock pulse generator, low frequency filter n triggers rows, N table modulo multipliers, N controlled phase changers, harmonic signal generator, phase detector and device for extraction and storage.

EFFECT: higher speed of receiving separate counts of formed harmonic oscillations, due to which maximum value of synthesized frequency is increased.

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Description

The invention relates to techniques for radio communications and can be used to generate the local oscillator frequency in radio receivers.

A device [1] is known, which contains four code generators, a multiplexer, a digital-to-analog converter (DAC), and a low-pass filter (LPF). The disadvantage of this device is the low value of the maximum frequency of the generated oscillations.

Also known is a device [2] containing an input data and control register, a phase accumulator, a phase control register, an adder, read-only memory, and a DAC. The disadvantage of this device is the low value of the maximum frequency of the generated oscillations.

The closest in technical essence to the proposed invention is a device [3] containing a clock generator, accumulating an adder, read-only memory, DAC and low-pass filter.

The disadvantage of the prototype is the low value of the maximum frequency of the generated vibrations due to the limited speed of the functional elements included in its composition.

The goal, the solution of which the claimed device is directed, is to increase the frequency range of the generated harmonic oscillations.

The technical result is expressed in increasing the speed of obtaining discrete readings of generated harmonic oscillations, thereby increasing the maximum value of the synthesized frequency.

содержит m_i триггеров

m₁, m₂,... , m_N - взаимно простые целые положительные числа), в которой выход j-го триггера

соединен со входом (j+1)-го триггера, а выход m_i-го триггера - со входом первого (j=1) триггера, при этом тактовые входы всех триггеров подключены к выходу тактового генератора, выход k-го триггера

i-й

линейки триггеров соединен с (k-1)-м разрядом унитарного кода первого операнда i-го

табличного умножителя по модулю, к соответствующим разрядам второго операнда которого подключен унитарный код остатка по модулю m_i значения частоты синтезатора, выход i-го табличного умножителя по модулю соединен с первым входом i-го управляемого фазовращателя, причем второй вход первого (i=1) управляемого фазовращателя подключен к выходу генератора гармонического сигнала, выход l-го

управляемого фазовращателя соединен со вторым входом (l+1)-го управляемого фазовращателя, а выход N-го управляемого фазовращателя подключен к первому входу фазового детектора, второй вход которого соединен с выходом генератора гармонического сигнала, а выход фазового детектора - с первым входом устройства выборки и хранения, второй вход которого соединен с выходом тактового генератора, а выход устройства выборки и хранения подключен ко входу ФНЧ.The technical result is achieved by the fact that in the known device containing a clock generator and a low-pass filter (LPF), the output of which is the output of the device, according to the invention, N trigger lines, N modular table multipliers, N controlled phase shifters, harmonic signal generator, phase detector are introduced and a sampling and storage device, the i-th line of triggers

contains m _i triggers

m ₁ , m ₂ , ..., m _N are mutually prime positive integers), in which the output of the jth trigger

connected to the input of the (j + 1) th trigger, and the output of the m _i th trigger - to the input of the first (j = 1) trigger, while the clock inputs of all the triggers are connected to the output of the clock generator, the output of the k-th trigger

i-th

the trigger line is connected to the (k-1) -th bit of the unitary code of the first operand of the i-th

modulo table multiplier, to the corresponding bits of the second operand of which is connected a unitary code remainder modulo m _{i of} the synthesizer frequency value, the output of the i-th table multiplier is modulo connected to the first input of the i-th controlled phase shifter, and the second input of the first (i = 1) controlled phase shifter is connected to the output of the harmonic signal generator, the output of the l-th

the controlled phase shifter is connected to the second input of the (l + 1) -th controlled phase shifter, and the output of the Nth controlled phase shifter is connected to the first input of the phase detector, the second input of which is connected to the output of the harmonic signal generator, and the output of the phase detector is connected to the first input of the sampling device and storage, the second input of which is connected to the output of the clock generator, and the output of the sampling and storage device is connected to the input of the low-pass filter.

The device differs from the prototype in new elements: a line of triggers, tabular computers, controlled by phase shifters, a harmonic signal generator, and a sampling and storage device with corresponding connections.

Thus, the invention meets the criterion of "novelty."

The invention consists in converting a digital code of the number A into an analog harmonic signal with a frequency

where F _T is the frequency of the clock; M is a fixed positive integer based on the application of the periodicity property of a harmonic function, similar to the property of arithmetic operations modulo in an integer ring.

In the claimed device, the formation of harmonic oscillations X (t) = Ucos (2π f _out t) is carried out by obtaining its samples at time instants t = Δ t · k, which are multiples of the clock frequency F _T = 1 / Δ t, and extracting the first one using the low-pass filter harmonic sequence of these samples.

In view of (1), discrete samples of harmonic oscillations with amplitude U are described by the expression:

Where

Since cosine is a periodic function, then

Therefore, k can be formed within a period

однозначно кодируется своими остатками а_i по основаниям m_i:An arbitrary non-negative integer A can be represented in the code of the system of residual classes [4]. The system of residual classes (RNS) refers to the number of non-positional number systems in which the integer A in the range

uniquely encoded by its residues a _i on the grounds m _i :

[· ] - целая часть числа; m₁, m₂,... , m_N - совокупность взаимно простых целых положительных чисел, называемых основаниями СОК; N - число оснований.Where

[· ] - the integer part of number; m ₁ , m ₂ , ..., m _N - a set of mutually prime positive integers called the bases of RNS; N is the number of bases.

Let in expressions (1) and (2)

The code of the number (3) from JUICE can be converted into a positional number system based on the Chinese remainder theorem [4]:

where μ _i is a constant determined from the comparison solution: (M _i · μ _i ) modm _i ≡ 1; M _i = M / m _i .

The code in the RNS of the result of the product C of numbers A and k is determined by calculating the individual products of the residues for each base [4]:

Представим (2) в видеwhere c _i [k] = (α _i χ _i ) modm _i ; χ _i = (k) modm _i ;

We represent (2) in the form

может быть сформирован в когерентном модулярном сумматоре [5], включающем в свой состав генератор гармонического сигнала (ГТС), N последовательно соединенных управляемых фазовращателей (УФ₁-УФ_N), фазовый детектор (ФД), при этом вход первого управляемого фазовращателя (УФ₁) подключен к выходу ГГС, а выход последнего (УФ_N) - к первому входу ФД, ко второму входу которого подключен выход ГГС.Discrete reading, directly proportional to the value

can be formed in a coherent modular adder [5], which includes a harmonic signal generator (GTS), N series-connected controlled phase shifters (UV _1- UV _N ), a phase detector (PD), while the input of the first controlled phase shifter (UV ₁ ) is connected to the GHS output, and the output of the latter (UV _N ) is connected to the first input of the PD, to the second input of which the GHS output is connected.

равные

то суммарный набег фаз на выходе УФ_N в соответствии с (4) будет равенIf in controlled UV phase shifters _i set phase shifts

equal

then the total phase incursion at the output of UV _N in accordance with (4) will be equal to

and the voltage at the output of the PD will be directly proportional

будет определяться частотой ГГС. При использовании ГГС миллиметрового диапазона длин волн с периодом частоты T≈ 10^-11С, указанное время будет равно сумме времени задержки в N управляемых фазовращателях (≈ N· T=N· 10^-11C) и длительности переходного процесса в ФД(≈ (5-10)T=(5-10)10^-11C), то есть менее 1 нс.The time of voltage formation, directly proportional

will be determined by the frequency of the GHS. When using a millimeter-wave GHS with a frequency period T≈ 10 ⁻¹¹ C, the indicated time will be equal to the sum of the delay time in N controlled phase shifters (≈ N · T = N · 10 ⁻¹¹ C) and the duration of the transition process in the PD (≈ ( 5-10) T = (5-10) 10 ^-11 C), i.e. less than 1 ns.

и получить из гармонического колебания с выхода ГГС напряжение в ФД, прямо пропорциональное

Thus, for the formation of the kth discrete sample of harmonic oscillation with the frequency f _o (1) according to formula (2), it is necessary, in accordance with the current value of the code, of the number k in the RNS (k = (χ ₁ , ..., χ _N ) ) calculate the residuals c _i [k] = (α _i χ _i ) modm _{i of the} product of the frequency code A and the reference number k, set the phase shifts in UV _i (i = 1, N) equal to

and get from the harmonic oscillations from the output of the GHS the voltage in the PD, directly proportional

The total execution time of these procedures will be equal to:

where t _k is the time of formation in the _RNS code of the current value of the reference number k, t _smart. - time of multiplication of two numbers in RNS; T is the period of the GHS frequency.

числа k по основанию

представлен унитарным кодом. В данном коде применяются m_i, шин данных, причем, если χ _i=0, то на шине нулевого разряда будет логическая “1”, а на остальных “0”, если χ _i=1, на шине первого разряда - “1”, а на остальных - “0” и т.д.Let the remainder

base k

represented by unitary code. In this code, m _i , data buses are used, moreover, if χ _i = 0, then on the zero-bit bus there will be a logical “1”, and on the remaining “0”, if χ _i = 1, on the bus of the first bit - “1” , and on the rest - “0”, etc.

When forming harmonic oscillations in the inventive device, discrete samples X (Δ t · k) (2) are successively obtained for k = 0, 1, 2, 3, ..., M-1. The sequence of numbers k in the SOK code will be cyclically repeated for each base m _i .

For example, for m ₁ = 2 and m ₂ = 3 (M = m ₁ m ₂ = 6) we obtain the RNS codes:

k = 0 ₁₀ = (0,0); k = l ₁₀ = (1,1); k = 2 ₁₀ = (0.2); k = 3 ₁₀ = (1.0); k = 4 ₁₀ = (0,1); k = 5 ₁₀ = (1,2); k = 6 ₁₀ = (0,0).

It can be seen that for a given set of bases m _i, the repetition period is m ₁ m ₂ = 6, and as k increases by 1, the residues for each base of the RNC increase to m _i -1 and then return to zero, that is, form an increasing 1 sequence can be done using sequentially connected binary triggers clocked synchronously, while the output of the last trigger in the line must be connected to the input of the first trigger (closed in a ring).

When the circuit is included in the first trigger of the line for each base m _i , a logical “1” should be written, and “0” in the rest. With the arrival of clock pulses from the clock, the logical “1” will advance along the ring of triggers, thereby simulating an increase in the number of k in the RNC by a code unit. It follows that the time t _k in (8) will be equal to the maximum possible switching frequency of the triggers (more than 400 MHz [3]), that is, t _k ≈ 2-2.5 ns.

As already noted, the multiplication of the numbers A and k in the RNS is performed separately for each base, that is, in parallel.

If the remainder of the number A-α _i and the remainder of the number k-χ _i , on the basis of m _{i are} represented by unitary codes, then the multiplier of these numbers on this basis can be made in the form of a matrix of m $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ two-input elements “AND” [6], and the signal upon receipt of the result of multiplication will propagate through two logical elements. It follows that t _smart in (8) will be equal to twice the delay time t _LE for the logic element: t _smart = 2 · t _LE = 1 ns (t _LE ≈ 0.5 ns [3]).

Thus, in the proposed device, the time to obtain a discrete sample of harmonic oscillations at its output will be equal to

t∑ = 2 ns + 1 ns + N · T + 10 · T.

For example, at N = 6 and T = 10 ^-11 s = 0.01 ns, t∑ ≈ 3.16 ns. Therefore, samples can be formed with a clock frequency F _T ≤ 1 / t∑ ≈ 300 MHz.

To restore harmonic oscillation from discrete samples, it is necessary to have at least two samples on its period. Thus, the maximum value of the synthesized frequency in the proposed device can reach 150 MHz.

In the prototype, the time to obtain a discrete sample of harmonic oscillation will be the sum of the time the two numbers are added in the position code in the accumulating adder (t _NS ), the time the number was taken from the read-only memory device (t _ROM ) and the time the number was converted to voltage in the DAC (t _DAC ). According to [3]: t _DAC ≈ 10-20 ns; t _ROM ≈ 20 ns; t _NS ≈ 10 ns.

Hence, the total sample formation time in the prototype: t _PR ≈ 10 + 20 + 10≈ 40 ns, and the maximum synthesized frequency f _max ≈ F _T / 2 = (l / 40) / 2 = 12.5 MHz, which is almost 10 times less than in the proposed device.

The invention has an inventive step, since it does not explicitly follow from the prior art for a specialist.

The invention is industrially applicable, as it can be used in various fields of national economy.

Figure 1 presents a structural diagram of a frequency synthesizer;

где 10.1-10.m_i - двоичные триггеры.Figure 2 presents the structural diagram of the line of triggers

where 10.1-10.m _i are binary triggers.

Figure 1 shows the structural diagram of a frequency synthesizer, where 1 is a clock generator, 2.1-2.N are the trigger lines, 3.1-3.N are modular table multipliers, 4 is a harmonic signal generator, 5.1-5.N are controlled phase shifters 6 — phase detector, 7 — sampling and storage device, 8 — low-pass filter, 9 — device output.

The output of the clock generator 1 (Fig. 1) is connected to the clock inputs of the rulers of triggers 2.1.-2.N and the input 2 of the device for fetching and storing 7, the outputs of the rulers of triggers 2.1.-2.N are connected to the inputs 1 (inputs of the first operand) of the corresponding table multipliers modulo 3.1-3.N, inputs 2 (inputs of the second operand) of which are connected to unitary codes of residues of the synthesizer frequency value, the output of the harmonic signal generator 4 is connected to input 2 of the controlled phase shifter 5.1, UV output 5.ii = (1, N- 1) - with input 2 UV 5. (i + 1), output UV 5.N - connected to input 1 of the phase detector torus 6, and the outputs of the corresponding table multipliers 3.1.-3.N are connected to the inputs 1 of the UV 5.1.-5.N, and the output of the harmonic signal generator 4 is connected to the input 2 of the phase detector 6, while the output of the phase detector 6 is connected to input 1 sampling and storage device 7, the output of which is connected to the input of the low-pass filter 8, and the output of the low-pass filter is the output 9 of the device.

Consider the operation of the device.

записывается логическая “1”, а в остальные триггеры - “0”. Это соответствует числу k=0 в коде СОК.When you turn on the frequency synthesizer in the trigger line 10.1 triggers

Logical “1” is written, and “0” in other triggers. This corresponds to the number k = 0 in the RNS code.

(входы второго операнда) поступает унитарный код остатка номинала синтезируемой частоты по модулю

Данный код остатка формируется с учетом значений разрядов позиционного представления значения номинала синтезируемой частоты [4, с.34]:

где α _p - значения р-го разряда позиционного кода; q_p - вес р-то разряда n-разрядного позиционного кода, по следующей формуле:The second inputs of the table multipliers modulo

(inputs of the second operand) the unitary code of the remainder of the nominal value of the synthesized frequency is received modulo

This code of the remainder is formed taking into account the values of the bits of the positional representation of the nominal value of the synthesized frequency [4, p. 34]:

where α _p are the values of the _pth digit of the position code; q _p - _p -th weight of the n-bit positional code, according to the following formula:

осуществляется умножение кодов остатков χ _i на остатки значения номинала синтезируемой частоты α _i по модулю m_i. В соответствии со значением результатов умножения c_i[k] в управляемых фазовращателях

устанавливаются сдвиги фазы

После прохождения гармонического сигнала с выхода генератора гармонического сигнала 4 через управляемые фазовращатели

на выходе фазовращателя 5.N будет набег фазы, равный

В результате обработки сигнала с этим набегом фазы с опорным сигналом с выхода генератора 4 в фазовом детектора 6, на его выходе образуется напряжение, прямо пропорциональное

Уровень, равный этому напряжению, с приходом следующего тактирующего сигнала с выхода тактового генератора 1 запоминается в устройстве выборки и хранения 7. Примеры практической реализации устройства выборки и хранения приведены в [3]. Этим же тактирующим сигналом логическая “1” продвигается в триггер 10.2 линеек триггеров

тем самым число k в коде СОК увеличивается на 1, и процесс формирования дискретных отсчетов синтезируемого гармонического колебания повторяется аналогично изложенному выше.In table multipliers modulo

the codes of residues χ _i are multiplied by the residuals of the nominal value of the synthesized frequency α _i modulo m _i . In accordance with the value of the multiplication results c _i [k] in the controlled phase shifters

phase shifts are set

After passing the harmonic signal from the output of the harmonic signal generator 4 through controlled phase shifters

at the output of the phase shifter 5.N there will be a phase advance equal to

As a result of processing the signal with this phase incursion with the reference signal from the output of the generator 4 in the phase detector 6, a voltage is generated at its output that is directly proportional

The level equal to this voltage, with the arrival of the next clock signal from the output of the clock generator 1, is stored in the sampling and storage device 7. Examples of practical implementation of the sampling and storage device are given in [3]. With the same clocking signal, logic “1” advances into trigger 10.2 trigger lines

thereby, the number k in the RNS code increases by 1, and the process of generating discrete samples of the synthesized harmonic oscillation is repeated similarly to the above.

The sequence of discrete samples from the output of the sampling and storage device 7 is fed to the input of the low-pass filter 8, in which the first harmonic is allocated, the frequency of which is equal to f _o (1). And finally, the harmonic oscillation formed from successive discrete samples goes to output 9 of the synthesizer.

Example: Let m ₁ = 2; m ₂ = 3 and m ₃ = 5; A = 3; F _T = 300 MHz. We get

M = m ₁ · m ₂ · m ₃ = 30; f _o = F _T · A / M = 30 MHz;

a ₁ = (A) modm ₁ = 1; a ₂ = 0; a ₃ = 3;

μ ₁ = 1; μ ₂ = 1; μ ₃ = 1.

φ ₂=0;

Суммарный набег фазы будет равен

. Соответственно с приходом следующего тактирующего сигнала с выхода тактового генератора 1 в устройство выборки и хранения запишется напряжение, прямо пропорциональное

Процесс формирования отсчетов будет продолжаться до k=29, а затем повторяться вновь с k=0. Из этой последовательности дискретных отсчетов в ФНЧ 8 формируется гармоническое колебание с частотой f_вых=30 МГц.When you turn on the frequency synthesizer in the trigger lines 2.1-2.3, the reference number k = 0 ₁₀ is written in the unit code of the RNS k = (0,0,0). The residues of the number k on the bases m ₁ , m ₂ and m ₃ are multiplied by the corresponding residues α ₁ , α ₂ and α ₃ in the factors 3.1-3.3. We get the number in the SOK code C [0] = (0 0, 0). In controlled phase shifters 5.1-5.3, phase shifts are set φ ₁ = 0; φ ₂ = 0 and φ ₃ = 0. Accordingly, the output of PD 6 will be a voltage directly proportional to X (Δ t · 0) = cos (0) = 1, which, with the arrival of the next clock signal, is recorded in the sampling and storage device 7. The data in the trigger lines 2.1–2.3 are the same clock signal. advance by one clock cycle, which corresponds to the reference number k = 1 ₁₀ = (1, 1, 1). This number is multiplied for appropriate reasons in the multipliers 3.1-3.3 with the remainders of the number A = (1, 0, 3). We get: C [1] = (1, 0, 3). UV 5.1-5.3 sets phase shifts

φ ₂ = 0;

The total phase advance will be equal to

. Accordingly, with the arrival of the next clock signal from the output of the clock generator 1, a voltage directly proportional to

The process of forming samples will continue until k = 29, and then repeat again with k = 0. From this sequence of discrete samples in the low-pass filter 8, a harmonic oscillation is formed with a frequency f _o = 30 MHz.

This device can be implemented on the following elements:

A table computer and a clock generator on semiconductor logic elements, a harmonic signal generator on microwave transistors, controlled phase shifters on PIN diodes.

The positive effect is that the proposed frequency synthesizer, by virtue of its capabilities, has high speed and a significantly expanded operating frequency range.

Sources of information

1. Bogatyrev Yu.K., Stankov B.C. Variational methods for constructing highly efficient systems for the computational synthesis of frequencies // Radioelectronics (Izv. Vyssh. Ucheb. Institutions). - 2002. - T. 45, No. 4, p. 18-24.

2. Starikov O. Direct digital synthesis of frequency and its application // СHIP news. Engineering microelectronics. - 2002. - No. 3, p. 56-64.

3. Digital radio receiving systems: Handbook / M.I. Zhodzishsky, R. B. Mazepa, E.P. Ovsyannikov et al. / Ed. M.I. Zhodzishsky. - M.: Radio and Communications, 1990. - 208 p.

4. Akushsky I.Ya., Yuditsky D.I. Machine arithmetic in residual classes. - M .: Owls. Radio, 1968 .-- 440 p.

5. Ovcharenko L.A. Implementation of a digital transverse filter in a system of residual classes // Radioelectronics (Izv. Vyssh. Ucheb. Institutions). - 2002. - T. 45, No. 4, p. 50-57.

6. Dolgov A.I. Diagnostics of devices operating in the system of residual classes. - M .: Radio and communications, 1982 - 64 p.

Claims (1)

A frequency synthesizer comprising a clock and a low-pass filter, the output of which is the output of the device, characterized in that N lines of triggers, N table modulators, N controlled phase shifters, a harmonic signal generator, a phase detector and a sampling and storage device are introduced, and i -th line of triggers contains m _i triggers, where

m ₁ , m ₂ , ..., m _N are coprime positive integers, while in the i-th line of triggers the output of the j-th trigger, where

is connected to the input of the (j + 1) th trigger, and the output of the m _i th trigger is connected to the input of the first trigger, and the clock inputs of all the triggers are connected to the output of the clock generator, the output of the kth trigger, where

i-th trigger line is connected to the (k-1) -th bit of the unitary code of the first operand of the i-th table multiplier modulo, to the corresponding bits of the second operand of which is connected the unitary code of the remainder modulo m _{i of} the synthesizer frequency value, the output of the i-th table modulo the multiplier is connected to the first input of the i-th controlled phase shifter, and the second input of the first controlled phase shifter is connected to the output of the harmonic signal generator, the output of the l-th controlled phase shifter, where

connected to the second input of the (l + 1) -th controlled phase shifter, and the output of the Nth controlled phase shifter is connected to the first input of the phase detector, the second input of which is connected to the output of the harmonic signal generator, and the output of the phase detector is connected to the first input of the sampling and storage device , the second input of which is connected to the output of the clock generator, and the output of the sampling and storage device is connected to the input of the low-pass filter.

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