RU2234762C1 - Flat evacuated fluorescent display - Google Patents

Abstract

FIELD: instrumentation and display engineering.

SUBSTANCE: proposed device designed to display various pieces of information incorporates provision for eliminating mutual impact of adjacent pixels and has sources and gates of its transistors connected to X and Y buses through resistors. In addition integrated control circuit is made on semiconductor chip periphery, its inputs being connected to X and Y buses of X-Y pixel matrix. Used as p MOS switching transistor is n MOS transistor.

EFFECT: enhanced quality of information displayed.

3 cl, 4 dwg

Description

The invention relates to low-voltage means of displaying information and can be used to create universal indicators designed to display any information: digital, text, symbolic, graphic, television, computer.

Vacuum luminescent indicators are known, containing a vacuum cylinder in which a circuit board, cathode and scattering grid are placed, anode electrodes coated with a phosphor layer are located on the circuit board (see Lisitsyn B. L. Indication elements. M .: Energy, 1978, p. 60, 67). The vacuum indicator, consisting of an electrovacuum system with a cathode and a grid and located on the substrate panes coated with a phosphor, is characterized in that, in order to increase the information capacity and simplify external circuitry, the substrate is made in the form of a crystal, the anodes are made in the form of an integrated circuit, and the phosphor the electrode sections of the circuit are covered (see RF patent No. 645460, MKI N 01 J 21/10, 1977, publ. 13.07.94).

A known vacuum luminescent indicator containing a filament cathode, a scattering grid and a circuit board with a semiconductor substrate with a passivating layer located on it, in which a control integrated circuit is made in the form of separate cells containing a phosphor on the surface (see ed. Certificate of the USSR No. 938332, MKI ³ H 01 J 21/10, publ. 06/23/82).

However, the above designs have significant disadvantages:

- vacuum luminescent indicators with high information capacity without built-in memory and control circuits require the use of a complex high-voltage and therefore expensive external control circuit, have more and more difficult to achieve acceptable brightness with increasing dynamic control duty cycle as the information capacity increases, a large number of external outputs (see. Lisitsyn B.L. Indication Elements.M .: Energy, 1978, p. 60, 67);

- vacuum luminescent indicators with a semiconductor substrate containing control and memory elements in each image element and peripheral control circuits, if there are connections not provided for by the semiconductor substrate design between the electrodes of one or more image elements, have inactive (uncontrolled) rows or columns of image elements (see RF patents No. 645460 and No. 938332).

The closest analogue prototype is a flat vacuum fluorescent television display with a matrix of p-MOS transistors, consisting of two groups of electrodes enclosed in a flat vacuum glass container, and one of the groups of electrodes operating at positive potentials consists of a number of image elements located in in the form of a matrix and consisting of r-MOS transistors and a light-emitting phosphor element deposited in the form of a phosphor layer on the drain of the r-MOS transistor, and another group of electrodes forms a ad cathode consisting of a number of thin filaments radiating electrons and an accelerating grid (see. IEEE NO.6. JUNE 1981. "Flat VFD Display Incorporating MOSFET Array").

The disadvantage of the design of the vacuum luminescent display is the low quality of information display due to insufficient uniformity of the phosphor luminescence due to differences in the density of the anode current.

The invention consists in the following.

The problem to which the invention is directed, is to improve the quality of the displayed information by preventing the mutual influence of one image element on the entire row or column.

The specified technical result in the implementation of the invention is achieved by the fact that in a flat vacuum luminescent display containing a cathode, a grid inside a vacuum cylinder, consisting of a glass front plate and an insulating substrate with at least one semiconductor crystal located on it, connected to external leads conductive tracks along the periphery with phosphor-coated electrodes arranged in the form of an X-Y image element matrix and representing a circuit from an address p-MOS trans a store, the drain of which is connected to the gate of the key p-MOS transistor, with a drain coated with a phosphor, while all the gates of the address transistors of each row of the X-Y matrix are connected to this address Y-bus, and all the sources of all address transistors of each column of the X-Y matrix connected to this address X-bus, a dielectric frame hermetically connecting the front plate and the substrate, resistors are additionally introduced, and the sources and gates of the address transistors are connected to the X- and U-buses through resistors. In addition, an integrated control circuit is made around the periphery of the semiconductor crystal, the inputs of which are connected to the X- and Y-buses X-U of the matrix of image elements; as a key p-MOS transistor, an n-MOS transistor is used.

In this design, if there are connections not provided by the design of the semiconductor chip between the electrodes of the image element, resistors included between the gate of the address transistor and the lower-case U-bus X-U of the matrix, and resistors included between the source of the address transistor and the column X-bus X -U matrix, prevent the mutual influence of one image element on the entire row or on the entire column.

The invention is illustrated by graphic materials, an example of a specific implementation and description.

Figure 1 shows a General view of the design of a flat vacuum fluorescent display.

Figure 2 shows the electrical circuit of the proposed option with r-MOSFET key transistor.

Figure 3 shows the electrical circuit of the image elements of the proposed option with n-MOSFET key transistor.

Figure 4 schematically shows an XY matrix of image elements.

The following notation is introduced in the drawings:

1 - glass front plate of a vacuum cylinder,

2 - insulating substrate of a vacuum cylinder,

3 - dielectric frame,

4 - cathode,

5 - mesh

6 - semiconductor crystals,

7 - contact pads,

8 - conductors

9 - external conclusions

T1 - address transistor,

T2 - key transistor,

R1, R2 - resistors,

X - column bus, for example, X ₁ , X ₂ , ... X _n ,

U - lower case tires, for example, U ₁ , U ₂ , ... U _m .

The flat vacuum luminescent display (see FIG. 1) contains a transparent front glass plate 1 and an insulating substrate 2, connected by a hermetic dielectric frame 3 to a vacuum cylinder, inside of which there is a cathode 4, a grid 5, the holders of which are not shown for ease of drawing. On the insulating substrate 2 inside the vacuum cylinder there are one or several semiconductor crystals 6 with the image elements shown in figure 2 or figure 3, arranged in the form of an X-Y matrix (see figure 4) and representing a circuit from the address p-MOS transistor T1, the drain of which is connected to the gate of the key p-MOS transistor T2 with the drain coated with a phosphor, while all the gates of all address transistors of each row of the X-Y matrix are connected to this address U-bus, and all the sources of all address transistors T1 of each column X-U ma The triceps are connected to this address X-bus. The contact pads 7 of the semiconductor crystals 6 are connected by conductors 8 to the external terminals 9 of the flat vacuum luminescent display.

The device operates as follows (see figure 2).

The semiconductor crystal 6 (Fig. 1) is under positive voltage relative to the heated cathode 4, the magnitude of which is sufficient for the occurrence of cathodoluminescence. Pulses generated by an external or internal driver are alternately fed to the U ... lower case buses - an integrated control circuit with a duration equal to the frame duration divided by the number of rows in the X-U matrix and exceeding the triple threshold voltage of the address transistor T1. These pulses through the resistor R1 enter the gate of the address transistor T1 and open it. X ... column buses are supplied with pulses generated by an external or internal driver, with a duration exceeding 1.1 times the duration of the row selection pulse Y, and with a value exceeding twice the threshold voltage of the address T1 and key T2 transistors, if the selected image element must be turned on, or not exceeding the threshold voltage of the address T1 and key T2 transistors, if the selected image element should be turned off. These pulses through the resistor R2 and the open address transistor T1 arrive at the gate of the key transistor. The potential supplied through the open address transistor T1 to the gate of the key transistor T2 at the time of the pulse of the sample string is stored on the gate capacitance of the key transistor T2 until the next call to this line. The key transistor T2 is in the open state if a potential exceeding the threshold voltage of the transistor is stored on its gate, and the phosphor deposited on the drain of this key T2 transistor is lit. The key transistor T2 is in the closed state, if a potential not exceeding the threshold voltage of the transistor is stored on its gate, and the phosphor deposited on the drain of this key transistor T2 does not glow. Thus, in the presence of a memory function built into each element of the X-Y matrix, the memory function (storing potential on the gate capacitance of the key transistor T2) is implemented in a quasistatic mode of information display, with a dynamic method of addressing the elements of the X-Y matrix.

A flat vacuum luminescent display with an integrated control circuit arranged on the periphery of the semiconductor crystal, the outputs of which are connected to the X- and Y-buses of the X-U matrix of image elements, while the n-MOS transistor is used as the key p-MOS transistor as follows, see Fig. 1 and Fig. 3.

The semiconductor crystal 6 is under positive voltage relative to the heated cathode 4, the magnitude of which is sufficient for the occurrence of cathodoluminescence. The lowercase buses U are alternately connected to the bus to which an analog brightness signal is supplied, having an amplitude equal to the anode voltage value, using an address transistor, the gate of which is controlled by pulses generated by an external or internal driver - an integrated control circuit, with a duration equal to the frame duration divided by by the number of rows in the X-Y matrix, and a value equal to the anode voltage. The impulses generated by the external or internal driver are fed to the column buses X _n - an integrated control circuit with a duration equal to the duration of the frame divided by the product of the number of rows and columns in the X-Y matrix and with an amplitude equal to the anode voltage. The potential supplied through the address transistor T1 to the gate of the key transistor T2 at the time of the pulse of the sample pulse R _m and column X _n is stored on the gate capacitance of the key transistor T2 until the next call to this image element. The key transistor T2 is in the open state if a potential exceeding the threshold voltage of the transistor is stored on its gate, and the phosphor deposited on the drain of this key transistor is lit. The key n-MOS transistor T2 in this embodiment operates in a stream follower mode. Its shutter stores an analog luminance signal recorded when accessing this element of the X-U matrix. At the same time, at the source of this transistor, a potential equal to U _g -U _t -Δ is established, where U _g is the gate voltage, U _t is the threshold voltage, Δ is the voltage, the value of which is determined by the influence of the substrate. In this case, the brightness of the luminophore deposited on the source of the p-MOS transistor T2 is proportional to the product of the current flowing through the transistor and the phosphor and the voltage at the source of this transistor. Thus, if there is a memory function built into each element of the X-Y matrix (storing potential at the gate capacitance of the key transistor T2), a quasistatic mode of information display is realized, with a dynamic way of addressing the image elements of the X-Y matrix, and the ability to display information with analog grayscale.

Using this design of a flat vacuum luminescent display in comparison with the known designs will improve the quality of the displayed information by increasing the uniformity of the phosphor glow and eliminating the mutual influence of image elements.

Claims (3)

1. A flat vacuum luminescent display containing a cathode, a grid inside a vacuum cylinder, consisting of a glass front plate and an insulating substrate with at least one semiconductor crystal located on it, connected to the external terminals of the current-carrying tracks along the periphery with the phosphor coated electrodes, arranged in the form of an X-Y matrix and representing a circuit from an address p-MOS transistor, the drain of which is connected to the gate of the key p-MOS transistor, with a drain coated with a phosphor, while all the gates of the address transistors of each row of the X-Y matrix are connected to this address Y-bus, and all the sources of all the address transistors of each column of the X-Y matrix are connected to this address X-bus, a dielectric frame hermetically connecting the face plate and the substrate, characterized in that resistors are additionally introduced, and the sources and gates of the address transistors are connected to the X- and Y-buses through resistors. 2. The flat vacuum luminescent display according to claim 1, characterized in that on the periphery of the semiconductor crystal an integrated control circuit is made, the outputs of which are connected to the X- and Y-buses XY of the image element matrix. 3. A flat vacuum luminescent display according to any one of claims 1 or 2, characterized in that an n-MOS transistor is used as the key p-MOS transistor.

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