RU219258U1 - DEVICE FOR SINGLE PULSE SELECTION - Google Patents

Abstract

The utility model relates to devices for isolating a single pulse. The technical result consists in eliminating the shortening of the selection of a single pulse and its skipping in case of violation of the multiplicity of the frequencies of the input and clock pulses and the disruption of their synchronization, in particular, under the influence of interference. For this, a device is proposed that contains three NAND elements and is distinguished by the introduction of a synchronous dynamic D-trigger and connections between NAND elements. Due to the introduction of synchronization and subsequent self-synchronization of the input and clock pulses, the reliability of the selection of a single pulse, equal in duration to the clock pulse, with the exception of its shortening and skipping, is increased, especially in noise conditions. 2 ill.

Description

The utility model relates to pulse technology and can be used in radio-electronic devices for processing discrete information, measuring and computer technology, as well as in automatic control systems under interference conditions.

A device for isolating a single pulse is known, which is described in the book Tietze U., Shenk K. Semiconductor circuitry, 12th ed., Vol. 1. Per. with him. - M: DMK Press, 2008. - 832 p., S. 770, fig. 9.46. The device contains two triggers synchronized by the front, an AND element, a control bus, a clock pulse bus and an output bus, the control bus is connected to the D-input of the first trigger, the output of which is connected to the D-input of the second trigger and the first input of the AND circuit, the second input of which is connected to the output of the second trigger, and the clock bus is connected to the clock inputs of both triggers, a second circuit is introduced to highlight the clock pulse _. the output of which is connected to the output bus, and the inputs are connected to the output of the first AND circuit and the clock bus.

The disadvantage of the device for isolating a single pulse is its complexity on a large amount of equipment required for its implementation according to the synchronous single vibrator circuit, which reduces its structural reliability, and the relatively high noise immunity due to synchronization by the front of the clock pulse does not provide rational non-redundant design and functional reliability.

A device for isolating a single pulse is known, which is described in the book Tietze U., Shenk K. Semiconductor circuitry, 12th ed., Vol. 1. Per. with him. - M.: DMK Press, 2008. - 832 p., p. 771, fig. 9.50. The device contains two triggers synchronized by the front, an XOR element, a control bus, a clock bus and an output bus, the control bus is connected to the D-input of the first trigger, the output of which is connected to the D-input of the second trigger and the first input of the XOR circuit, the second input of which connected to the output of the second trigger, and the clock bus is connected to the clock inputs of both flip-flops, an AND circuit is introduced to isolate the clock pulse, the output of which is connected to the output bus, and the inputs are connected to the output of the XOR circuit and the clock bus.

The disadvantage of the device for isolating a single pulse is its complexity on a large amount of equipment required for its implementation according to the change detector circuit, which reduces its design reliability, and the relatively high noise immunity due to synchronization by the front of the clock pulse does not provide rational non-redundant design and functional reliability, as and in the case of using a synchronous one-shot to extract a single full clock pulse.

A device for isolating a single pulse is known, which is described in the book of Spiridonov SB. "Circuit Engineering of Discrete Devices" Educational and Methodological Guide 2020 - 224 p., P. 117, Fig. 5.36.

The device contains a synchronous, combined with an asynchronous D-trigger, a synchronous dynamic D-trigger, an AND element, a control bus, an output bus and a clock pulse bus, which is connected to the clock input of the synchronous dynamic D-trigger, the D-input and output of which are connected, respectively , to the output of the combined D-trigger and the first input of the AND element, the output and the second input of which are connected, respectively, to the output bus and the clock bus, and the inverse output of the synchronous D-trigger is connected to the asynchronous setting input of the combined D-trigger, C-input which is connected to the control bus.

The disadvantage of the device for isolating a single pulse is its complexity on a large amount of equipment required for its implementation according to the scheme of two synchronous dynamic triggers, one of which is combined according to the used input of its asynchronous setting to the initial state, which complicates the entire device. The relatively high noise immunity of the device, due to synchronization by the front of the clock pulse of both D-flip-flops, does not provide rational non-redundant structural and functional reliability, since it requires a large number of logical transitions inside the flip-flops, as in the case of using similar analogues to select a single full clock pulse.

The closest to the claimed utility model in terms of technical essence and the achieved technical result is the Pulse Generator (RU 212188, 2022). The pulse generator contains three NAND elements, the first and second inputs, respectively, of the first and second of which are connected to the input bus, the output of the first element is connected to the first inputs of the second and third, the output of the second element is connected to the second input of the third element, the output of which is connected to the second the input of the first, the third input of the second element is connected to the clock bus, and the fourth and fifth elements of the AND-NOT are introduced, the clock bus is connected to the first input of the fourth element, the second input and output of which are connected respectively to the output and the third input of the first element, and the input bus is connected with the first input of the fifth element, the second input and output of which are connected respectively to the output and the third input of the third element.

The disadvantage of the device is its low reliability of selecting a single pulse with a duration equal to the clock pulse, which reduces the functionality of the entire device. This drawback is due to the fact that the device emits a complete single pulse of duration equal to the clock pulse only in the case of an exact frequency multiplicity acting on the input and clock buses. If the frequency multiplicity is violated, a single pulse is allocated with a duration less than the duration of the clock pulse, and the duration of the selected pulse can become so small that a single pulse will be missed, especially in the event of interference.

The technical problem is to increase the reliability of the selection of a single pulse and expand the functionality of the device, which consists in the selection of a single pulse with a duration equal to the clock pulse at any ratio of the frequencies of the input and clock pulses.

The technical result consists in eliminating the shortening of the selection of a single pulse and its skipping in case of violation of the multiplicity of the frequencies of the input and clock pulses and the disruption of their synchronization, in particular, under the influence of interference.

The essence of the utility model lies in the fact that the device for extracting a single pulse contains three NAND elements, the output of the first element is connected to the first inputs of the second and third, the output of which is connected to the second input of the first, and a synchronous dynamic D-trigger is introduced, the D-input which is connected to the input bus, the first input of the first element and the second input of the second element are connected to the output of the D-flip-flop, the C-input of which is connected to the clock bus and the second input of the third element.

In FIG. 1 shows a functional electrical diagram of a device for isolating a single pulse; in fig. 2 - timing diagrams at the inputs and outputs of the elements of the device for isolating a single pulse as a result of the operation of its model in the MULTISIM program.

The device for selecting a single pulse contains an input bus 1, a clock bus 2, a synchronous dynamic D-flip-flop 3, the first element of NAND 4, the second element of NAND 5, the third element of NAND 6, the output bus 7. To the input bus 1 the D-input of the D-flip-flop 3 is connected, to the C-input of which the clock bus 2 and the second input of the third element 6 are connected, the first input of which is connected respectively to the first input of the second element 5 and the output of the first element 4, the output of the third element 6 is connected to the second input the first element 4, the first input of which is connected to the output of the D-flip-flop and the second input of the second element 5, the output of which is connected to the output bus 7.

The device for selecting a single pulse works as follows.

In the initial state of the device for selecting a single pulse, the potentials on the input bus 1 and clock bus 2 correspond to the logic zero potential. The potential at the output Z _{1 of} the D-flip-flop 3 corresponds to the logic zero potential, which causes the formation of a potential of one at the output Z ₂ of element 4 and at the output U _of the element 5, and hence on the output bus 7. Zero potential on the clock bus 2 causes the transition Z ₃ to a single state at the output of element 6, so that at both outputs of elements 4 and 6, respectively, forming a bistable cell, potentials Z ₂ and Z ₃ of a logical unit act. Changes in the potential U _ti clock pulse on clock bus 2, when the potential of the control pulse U _y on input bus 1 is still zero, cannot change the zero potential Z ₁ at the output of D-flip-flop 3. This leads to the fact that at the output U _output element 5 and the output bus 7 continues to have a single potential, the potential Z ₂ of a logical unit acts at the output of element 4, and the inverted clock pulses Z ₃ follow at the output of element 6 with a delay t ₃ for the duration of signal propagation in element 6.

A change in the control potential U _y on input bus 1 during the action of clock pulses U _ti from clock bus 2 to the C-input of D-flip-flop 3 does not cause a change in the state of the entire device until the edge of the clock pulse is ahead of the front of the control potential U _y .

When the control potential U _y changes from bus 1 to unity, at the D-input of D-flip-flop 3 from the front of the clock pulse U _ti clock bus 2 with a delay for the signal propagation time in the trigger, a unit potential Z ₁ appears at its output. Since the potential of the logical unit Z ₂ acted at the output of element 4, then, under the influence of this potential and the unit potential of the clock pulse U _ti from the clock bus 2, the potential Z ₃ of logical zero will appear at the output of element 6. This zero potential Z ₃ at the output of element 6 does not cause a change in the unit potential Z ₂ of the output of element 4 until the potential U _of the clock pulse from one to zero changes from clock bus 2.

Since the outputs of D-flip-flop 3 and element 4 have unit potentials Z ₁ and Z ₂ , then at the output of element 5 and output bus 7 a zero potential U out will appear _with a duration equal to the duration of the inverted clock pulse Z ₃ at the output of element 6, after which the output of element 4 is formed zero potential Z ₂ . Zero potential Z ₂ at the output of element 4 returns the output potential U _{out of} element 5 to the initial single state. Consequently, at the output of element 5 and output bus 7, a pulse occurs, the zero potential U _{out of} which is equal to the duration of the clock pulse, i.e., the inverted value of this clock pulse.

The subsequent continuation of the action of the unit control potential U _y from the input bus 1 to the D-input of the D-flip-flop 3 does not cause it to change under the action of the edges of the subsequent clock pulses U _ty from the clock bus 2. Until the end of the action of the unit control potential U _y from the input bus 1, the single state Z ₁ at the output of the D-flip-flop 3 and the zero state Z ₂ of the output of element 4, since the single state Z ₃ at the output of element 6 is preserved. Therefore, at the output of element 5 and on the output bus 7 there is a unit potential U _out .

Thus, a complete single clock pulse in its inverted form is allocated on the output bus 7. The emerging identical states Z ₂ and Z ₃ of both outputs, respectively elements 4 and 6, do not cause an erroneous transition of element 5 until the end of transients in the bistable cell, which does not have any effect on the synchronous D-flip-flop 3 and the potential U _{out of} the output bus 7. The bistable cell on elements 4 and 6 stably switches from the clock pulse generation mode at the output of element 6 to the trigger mode after the inverted value of a single clock pulse generated at the output of element 5 and on output bus 7 is selected.

With the advent of bus 1 potential U _y corresponding to logical zero, when clock bus 2 is clocked U _ti , D-flip-flop 3 will change its state output Z ₁ to zero potential only when the front U _ti clock pulse from the input bus 1 will fall into the interval of the control potential U _y , which corresponds to a logical zero. Due to the action of the zero potential Z ₁ at the output of the D-flip-flop 3, the state of Z ₂ changes to a unit potential at the output of element 4, and the inverted clock pulses Z ₃ will occur at the output of element 6. The clock pulse is not allocated, since different potentials Z ₁ and Z ₂ operate at the inputs of element 5 from the output of D-flip-flop 3 and element 4.

With a change in the control potential U _y to a single one from the input bus 1 at the D-input of the D-flip-flop 3, changes at the output of element 5 and output bus 7 will not occur until the occurrence of the front U _ty clock pulse from clock bus 2. From the action of the front of the clock pulse from clock bus 2 at the output of element 5 and output bus 7 will be allocated a single pulse U _{out with} a duration equal to the inverted value of the clock pulse U _ti , similarly described after changing the initial state of the device.

In the future, the processes are repeated similarly to those described, and a complete single clock pulse is allocated on the output bus 7 in its inverted form. The emerging identical states of the potentials Z ₂ and Z ₃ at both outputs of elements 4 and 6 do not cause an erroneous transition of the output of the AND-NOT 5 element until the end of the transients and do not have any effect on the synchronous D-flip-flop 3, i.e. do not affect the potential Z ₁ from the output of this trigger. Element 5 self-synchronizes the bistable cell on elements 4 and 6 and is an indicator of the end of transient processes in this bistable cell.

Since the synchronous dynamic D-trigger 3 is usually executed according to the Webb scheme with full synchronization of the input potential from the front of the clock pulse, and the asynchronous part of the device is made according to the self-synchronization scheme, such combined synchronization does not shorten the output pulse and more reliably forms it in duration equal to the duration of the clock pulse. impulse. The output pulse at the output of element 5 is equal in duration to the inverted value of the clock pulse. The control consists in the fact that, after the formation of a zero potential Z ₂ at the output of element 4, the transition process of the formation of potentials Z ₃ of inverted clock pulses at the output of element 6 ends. The bistable cell on elements 4 and 6 steadily switches to the trigger mode. To select single pulses in duration equal to the clock pulse without inverting it, it is enough to use the AND logic element instead of the AND-NOT 5 logic element.

As a result, at the input of element 5, a pulse is allocated, equal in duration to the clock pulse U _ti when a unit potential Z ₁ from the output of the D-flip-flop 3 and a unit potential Z ₂ from the output of element 4 at any ratio of the frequencies of the input and clock pulses. Therefore, the proposed device performs the functions of a pulse synchronizer more reliably than the prototype device, which shortened the clock pulses to 3t ₃ in the absence of a multiplicity of input and clock pulse frequencies. Due to this, the reliability of the selection of a single pulse is higher than that of the prototype, and the device for the selection of a single pulse can be used without skipping the timing under interference conditions. In the proposed device, due to the elimination of transients in the asynchronous part of the device by combining synchronization and self-synchronization, the criticality of the parameters of the generated single pulse is eliminated and, accordingly, the possibilities of using the device as a synchronizer are expanded. The operability of the device for extracting a single pulse was verified by the MULTISIM simulation program.

The solution of the technical problem increase. the reliability of single pulse selection with bringing to the prevention of a possible failure due to interference, made it possible to provide the technical and economic advantages of the proposed circuit solution in comparison not only with the prototype, but also with the base object. When compared with the basic object, which is built on two synchronous triggers, and which is discussed in the last paragraphs on page 2, the proposed device is simpler in terms of the amount of equipment used. This is because dynamic triggers are built according to the Webb scheme on 6 elements, which is more complicated than the proposed one, which uses only 3 elements after the dynamic D-trigger.

Claims (1)

A device for extracting a single pulse, containing three NAND elements, the output of the first element is connected to the first inputs of the second and third, the output of which is connected to the second input of the first, characterized in that a synchronous dynamic D-trigger is introduced, the D-input of which is connected to the input bus, the first input of the first element and the second input of the second element are connected to the output of the D-flip-flop, the C-input of which is connected to the clock bus and the second input of the third element.

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