RU212188U1 - PULSE GENERATOR - Google Patents

Abstract

The utility model relates to microelectronics and can be used in radio-electronic devices for processing discrete information, computer technology and control systems under interference conditions. The technical result consists in the possibility of isolating a single full clock pulse and eliminating the memory error when clocking the pulse generator, which leads to the expansion of its functionality and increase its fault tolerance. The pulse generator contains five logic elements AND-NOT, clock and input buses. The first three elements form a single pulse generator, and the introduction of the fourth and fifth elements with their connections form two duplicate bistable cells. Duplication made it possible to isolate the full clock pulse. The selection of a full clock pulse expands the possibilities of using the functions of the pulse generator not only in its quality, but also as a synchronizer and a synchronized dD flip-flop with greater resistance to failure than the extremely short clock pulse of the prototype, the duration of which was critical to load changes and reduced the generator's error immunity single impulse. 2 ill.

Description

The utility model relates to microelectronics and can be used in radio-electronic devices for processing discrete information, computer technology and control systems under interference conditions.

A well-known pulse generator, which is built according to the scheme of a synchronous D-trigger (Pukhalsky G.I. Digital devices: textbook for higher education institutions / G.I. Pukhalsky, T.Ya. Novoseltseva. - St. Petersburg: Polytechnic, 1996. - S. 404 -405.). The pulse generator contains a Webb D flip-flop, a control bus, a clock bus, and two reset buses.

The disadvantage of the pulse generator is the complexity and low functionality, which ensure its use as a single pulse generator - a single vibrator, a trigger and a simple timing circuit, which require at least six, for example, NAND elements to ensure error immunity. Such a pulse generator cannot be used as a full clock burst generator.

Known pulse generator (patent No. 678659, 1992). Such a pulse generator contains three NAND elements, the first and second inputs, respectively, of the first and second of which are connected to the input bus, the output of the first element is connected to the first inputs of the second and third, the output of the second element is connected to the second input of the third element, the output of which is connected to the second input of the first.

The disadvantage of the pulse generator is low functionality, which is limited to its use as a shortened pulse generator. Such a pulse generator is used as a differentiating (shortening) circuit, and its use as a trigger is problematic due to a possible load change, at which the pulse generator may fail in the trigger mode due to a missed shortened pulse.

The closest to the claimed utility model in terms of technical essence and the achieved technical result is a pulse generator (article by Krekhova E.V. Analysis and synthesis of a trigger comparator / E.V. Krekhov, I.V. Krekhov // Measuring equipment. - 2002. - No. 11. - S.46-50.). The pulse generator contains three NAND elements, the first and second inputs, respectively, of the first and second of which are connected to the input bus, the output of the first element is connected to the first inputs of the second and third, the output of the second element is connected to the second input of the third element, the output of which is connected to the second input of the first, the third input of the second element is connected to the clock bus.

The disadvantage of such a pulse generator is low functionality, which is limited to its use as a synchronized shortened pulse generator and low error stability. Such a pulse generator is used as a shortening circuit, for example, in a synchronous trigger comparator, and its use as a trigger is problematic due to a possible load change, at which the pulse generator may fail due to a shortened pulse missed.

The technical problem is to expand the functionality of the pulse generator when it is used by a synchronizer and to increase the error resistance of the pulse generator when it is used by a synchronized dD trigger.

The technical result consists in the possibility of isolating a single full clock pulse and eliminating a memory error when clocking the pulse generator.

The essence of the utility model lies in the fact that the pulse generator contains five AND-NOT logic elements, a clock bus and an input bus, the first and second inputs, respectively, of the first and second of the AND-NOT elements are connected to the input bus, the output of the first element is connected to the first inputs second and third, the output of the second element is connected to the second input of the third element, the output of which is connected to the second input of the first, the third input of the second element is connected to the clock bus, which is connected to the first input of the fourth element, the second input and output of which are connected respectively to the output and the third input of the first element, and the input bus is connected to the first input of the fifth element, the second input and output of which are connected respectively to the output and third input of the third element.

In FIG. 1 shows a functional electrical circuit of a pulse generator based on AND-NOT elements;

in fig. 2 - screenshots of timing diagrams at the outputs Z ₁ , Z ₂ , Z ₃ , Z ₄ , Z ₅ of elements 1 - 5 AND-NOT, buses 6, 7 as a result of the operation of the pulse generator model in the MULTISIM program.

The pulse generator contains logic elements 1-5 AND-NOT, clock bus 6 and input bus 7, output Z _{1 of} element 1 is connected to the first inputs of elements 2, 3 and the second input of element 4, output Z _{2 of} element 2 is connected to the second input of element 3 , output Z _{3 of} element 3 - with the second input of element 2 and the second input of element 5, output Z _{4 of} element 4 - with the third input of element 1, output Z ₅ of element 5 - with the third input of element 3. Clock bus 6 and input bus 7 are connected respectively to the third and first inputs of elements 2, 4 and to the first and second inputs of elements 1, 5 and 2.

The pulse generator works as follows.

In the initial static state of the pulse generator, built on the elements of AND-NOT, when there are logical zero potentials on buses 6 and 7, the potential of a logical unit is set at the outputs Z ₁ , Z ₂ , Z ₅ elements 1, 2, 5, and at the output Z ₄ elements 4 with a delay lt ₃ , where t ₃ is the signal delay in one element AND-NOT, provided that all elements are technologically the same, inverted clock pulses are formed - transitions 8 and 9. At the output Z _{3 of} element 3 is the potential of logical zero.

Changes in the potential of the clock pulse on bus 6, when the potential of the input pulse on bus 7 is still zero, cannot change the unity potential at the outputs Z ₁ , Z ₂ of elements 1 and 2. Therefore, the output Z _{3 of} element 3 remains low (zero) potential, and at the output Z ₄ element 4 followed by inverted clock pulses with a delay lt ₃ .

From the front of the control pulse that occurs between clock pulses from bus 6, which follow at a higher frequency than the input pulses from bus 7, changes in the pulse generator circuit occur only during the first clock pulse following the front of the input pulse. At the first coincidence of the input signal level affecting elements 1, 2, 5, and the clock pulse acting on the input of element 4, after a delay time t ₃ equal to the duration of signal propagation in one element AND-NOT, the state of the output Z _{2 of} element 2 changes to zero - transition 10, which, for the duration of the clock pulse, changes the state at the output Z _{3 of} element 3 to one - transition 11. At the output Z ₅ of element 5, zero occurs - transition 12, which blocks the state of output Z _{3 of} element 3 in unity for everything the duration of the input signal from the bus 7. At the slice of the clock pulse, a unit again appears at the output Z _{2 of} element 2 - transition 13. Therefore, at the output Z _{2 of} element 2, an inverted clock pulse will be selected from the continuously following clock pulses, and at the output Z _{1 of} the element 1, a zero-transition 14 occurs, which blocks the output state Z _{4 of} element 4 in a single state - transition 15 until the end of the input pulse from bus 7.

On the cut of the input pulse from bus 7, element 1 is triggered, which, at the output Z ₁ , goes into a single state - transition 16, which returns the zero potential at the output Z _{3 of} element 3 - transition 17, which means that at the output Z ₅ of element 5, a stable unit potential - transition 18. During the action of the zero potential of the clock pulse, the output Z _{4 of} element 4 continues to be in a single state, and with the action of the front of the clock pulse - transition 19, clock pulses again occur at the output Z _{4 of} element 4.

Thus, only one inverted pulse with a duration equal to the duration of one clock pulse is removed from the output Z _{2 of} element 2. At the direct and inverse outputs of two bistable cells formed by elements 1, 4 and 3, 5, respectively, opposite potentials arise that do not have forbidden states. A bistable cell of elements 1 and 3 eliminates a possible forbidden state due to the action of negative feedback from the output of element 2. Subsequently, the processes are repeated similarly to those described.

The proposed pulse generator generates one inverted clock pulse without shortening it over the entire range of the input pulse from bus 7, which includes all periods of pulses from bus 6, regardless of their number. As a result of blocking the output Z _{3 of} element 3 and the output Z _{4 of} element 4, which reserve their positive feedback on the output Z _{1 of} element 1, the proposed pulse generator can be used as a synchronizer, and, therefore, its capabilities are wider than that of the prototype. Due to the longer duration of the full selected pulse than the shortened output pulse, the error resistance of the proposed generator will be higher than that of the prototype.

In the proposed pulse generator, due to the introduction of additional elements 4 and 5 with their connections, the elimination of the criticality of the parameters of the generated single pulse is achieved. As a result of the possibility of extracting a single full clock pulse, the pulse generator can be used as a device for extracting a full such pulse or a synchronizer, as well as a synchronized dD flip-flop, since its error immunity is ensured by reducing the causes of failure due to criticality to the action of an extremely shortened impulse. The operability of the pulse generator has been verified by the "PROTEUS" simulation program.

Solving the technical problem of expanding the possibilities of using the proposed device as a device for extracting a full clock pulse or a synchronizer and bringing the fault tolerance of the pulse generator to prevent failure in the operating mode of a clocked dD flip-flop in a circuit design with only five AND-NOT logic elements made it possible to provide technical and economic advantages the proposed pulse generator compared with the prototype.

Claims (1)

A pulse generator containing three NAND elements, the first and second inputs, respectively, of the first and second of which are connected to the input bus, the output of the first element is connected to the first inputs of the second and third, the output of the second element is connected to the second input of the third element, the output of which is connected to the second input of the first, the third input of the second element is connected to the clock bus, characterized in that the fourth and fifth elements of the AND-NOT are entered, the clock bus is connected to the first input of the fourth element, the second input and output of which are connected respectively to the output and third input of the first element, and the input bus is connected to the first input of the fifth element, the second input and output of which are connected respectively to the output and the third input of the third element.

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