RU2192038C1 - Device for measuring channel error parameters - Google Patents

Abstract

FIELD: telecommunications and computer engineering. SUBSTANCE: device that may be used for measuring parameters of errors distorting data in transmission channels or for reproducing data with stuffing/drop- in bits has shift registers, sync-character-to-locator converter, subtracter, counter, relative-locator buffer, code comparison circuit, significant relative locator finding unit, significant relative locator buffer, available relative locator weighing buffer, error yes or not decision unit, and channel status train shaping unit. Device functions to determine size and location of stuffing and drop-in bits in data stream from channel minimizing impact of adjacent additive errors and also to more accurately recover stream of additive errors minimizing impact of stuffing and drop- in bits. EFFECT: enhanced measurement accuracy. 24 cl, 1 tbl

Description

 The invention relates to telecommunication systems and computer technology and can find application for measuring error parameters that distort data in transmission or reproduction channels with bit inserts / drops.

 A device is known for testing communication channels using a pseudo-random sequence (PN sequence) [1], the receiving part of which contains two PN sequence generators, two sequence comparison circuits, a counter that counts the number of matching bits, four triggers and AND, OR logic elements , NOT.

 The known device generates a stream of erroneous bits detected in a test signal received from the channel by comparing the sequence of bits of the test signal with the bits of the PN sequence reconstructed by the first generator. The device detects a synchronization violation (due to insertions or bit drops) between the bit sequence of the test signal and the reconstructed PN sequence, and resynchronizes to prevent incorrect generation of the error bit stream. Detection of synchronization is carried out using the second generator of the PN sequence by recognizing in the stream of erroneous bits the PN sequence shifted in phase.

The disadvantages of the device:
- a relatively high probability of an erroneous determination of a synchronization violation due to the small length of the portion of the error bit stream analyzed when recognizing the PN sequence;
- the addition of a sufficiently large number of false error bits to the generated stream of error bits due to a violation of synchronization, which is explained by the relatively large delay in the decision to restore synchronization;
- the inability to measure the values of the inserts or loss of bits and their location.

 A device for measuring the level of errors in the channel [2], which measures the level of errors in the process of transmitting data using the PN sequence. The device contains a serial-parallel converter, a network of correlators, a multiplier in the final field, a comparison circuit, a buffer data memory, a number of additional blocks.

 Device [2], like device [1], generates a stream of erroneous bits by comparing the sequence of bits of the test signal with the bits of the reconstructed network of PN sequence correlators. The correlator network maintains proper synchronization between the sequence of bits of the test signal and the reconstructed PN sequence, even if there are inserts or occurrences of bits in the test signal. The device [2] eliminated the addition of false error bits to the generated error stream due to a synchronization violation.

The disadvantages of the device [2] are:
- additive errors that are possible after inserting or dropping bits can lead to a significant delay in switching to the required phase of the PN sequence of the output of the correlator network and, therefore, to the addition of a number of incorrectly defined errors to the error bit stream;
- the inability to measure the values of the inserts or loss of bits and their location.

 A device [3] is known for determining a synchronization violation between a sequence of bits of a test signal and a PN sequence restored in a receiving device, which provides for restoration of synchronization to prevent incorrect formation of a stream of erroneous bits. The device comprises a PN sequence generator, a sequence comparison scheme for bits, i correlators, i threshold detectors, an analyzer of the sum of cross-correlation functions, a bit slippage analyzer, an error level analyzer.

 To determine the synchronization violation, i correlators are used, each of which calculates a cross-correlation function between one of the i segments of the PN reference sequence and the test sequence received from the channel. The output signals of the correlators are processed by threshold detectors and summed. The shift of the maxima in the resulting sum of cross-correlation functions indicates a violation of synchronization. To limit the incorrect formation of a stream of erroneous bits, the generator of the reference PN sequence is synchronized for each selected maximum.

The disadvantages of the device:
- adding a sufficiently large number of false error bits to the generated error bit stream due to a synchronization violation, since a relatively large value of the time interval between inserting (dropping) bits and resynchronization of the PN sequence generator, which is carried out discretely (i times on the PN- period, is possible sequence);
- the impossibility of sufficiently accurate determination of the place of insertion or loss of bits (you can only determine the interval between two maxima in which they occurred).

 The closest in technical essence to the claimed invention is a device selected as a prototype, designed to measure the level of bit errors in the channel [4], containing two PN sequence generators, two bit sequence comparison schemes, four shift registers for frame delay, four slip detectors (insertions or dropouts) frames, error bit counter, slippage counter, controller, various logic.

 A prototype device, similarly to devices [1, 2, 3], generates a stream of error bits detected in a test signal received from a channel by comparing the sequence of bits of the test signal with the bits of the PN sequence restored by the main PN generator. The device also detects a synchronization violation (due to insertions or dropped frames) between the bit sequence of the test signal and the reconstructed PN sequence, and resynchronizes to prevent incorrect generation of the error bit stream. Slippage detection and determination of their magnitude is carried out using four slippage detectors, each of which compares the reconstructed PN sequence with one of the four shifted bit sequences of the test signal.

 In contrast to the previously discussed devices [1, 2], the prototype device implements a calculation of the number of slippages.

The disadvantages of the prototype include:
- slippage of only a small number of frames (one or two) is determined;
- additive errors that are possible after slippage can lead to a significant delay in detecting synchronization errors and, therefore, to add to the counter of erroneous bits a certain number of incorrectly defined errors;
- the inability to measure the location of erroneous bits and slippages in the data stream.

 An object of the invention is to determine the size and location of the inserts and bit drops in the data stream from the channel, minimizing the influence of additive errors located nearby, as well as more accurate recovery of the additive error stream, minimizing the effect of bit inserts and bit drops.

 The technical problem posed is solved by  what's in a known device,  containing the first shift register,  second shift register  sequence comparison scheme,  moreover, the input of the first shift register is the input of the device for the analyzed bit sequence,  the first output of the first shift register is connected to the input of the second shift register,  the output of the second shift register is connected to the first input of the sequence comparison circuit,  according to the invention, a converter of sync symbols to locators is introduced,  first subtractor  first counter  relative locator buffer  first code comparison scheme,  block finding a significant relative locator,  buffer of significant relative locators,  weight buffer of significant relative locators,  a decision unit for errors,  a channel state flow forming unit,  moreover, the inputs of the sync converter to the locators are connected to the second outputs of the first shift register,  the first inputs of the first subtractor are connected to the outputs of the sync symbol to locator converter,  the second inputs of the first subtractor are connected to the outputs of the first counter,  the outputs of the first subtractor are connected to the inputs of the buffer relative locators,  with the first inputs of the first code comparison circuit and with the first inputs of the block of finding a significant relative locator,  the outputs of the relative locator buffer are connected to the second inputs of the first code comparison circuit and to the second inputs of the block for finding the significant relative locator,  the output of the first code comparison circuit is connected to the third input of the block of finding a significant relative locator,  the first outputs of the block of finding the significant relative locator are connected to the inputs of the buffer of the significant relative locators and with the first inputs of the block making decisions about errors  the second outputs of the block of finding the significant relative locator are connected to the inputs of the buffer of the weights of the significant relative locators and to the second inputs of the block making decisions about the presence of errors,  the outputs of the buffer of significant relative locators are connected to the third inputs of the decision block on the presence of errors,  the outputs of the buffer weights of significant relative locators are connected to the fourth inputs of the decision block on the presence of errors,  the first output of the decision-making unit for errors is connected to the first input of the channel state flow forming unit,  the second output of the decision-making unit for errors is connected to the second input of the channel state flow forming unit,  the third outputs of the decision-making unit for errors are connected to the third inputs of the channel state flow forming unit,  the fourth output of the decision-making unit for errors is connected to the fourth input of the channel state flow forming unit,  the fifth output of the decision block on the presence of errors is the output "Measurement Failure" of the device,  the first output of the channel state flow forming unit is the output of the recording strobe device,  the second outputs of the channel state flow forming unit are the “Error Type” outputs of the device,  the third outputs of the channel state flow forming unit are the “Error size” outputs of the device,  moreover, the block finding a significant relative locator contains a first multiplexer,  first to eleventh bus formers,  first to sixth buffer registers,  first null code selector,  random access memory  first element AND,  initialization device  control device,  moreover, the first inputs of the first multiplexer are the first inputs of the block finding a significant relative locator,  the second inputs of the first multiplexer are the second inputs of the block finding a significant relative locator,  the enable input of the control device is the third input of the block finding a significant relative locator,  the control input of the first multiplexer is connected to the first output of the control device,  the outputs of the first multiplexer are connected to the data inputs of the first bus driver and to the data inputs of the second bus driver,  the control input of the first bus driver is connected to the second output of the control device,  the control input of the second bus driver is connected to the third output of the control device,  the outputs of the first bus driver are connected to the address bus,  the outputs of the second bus driver are connected to the data bus,  the first address inputs of random access memory are connected to the address bus,  the second address input of random access memory is connected to the third input of the first element And,  with the fourth output of the control device and with the third output of the initialization device,  the third address input of random access memory is connected to the second input of the first element And,  with the fifth output of the control device and with the fourth output of the initialization device,  the read / write control input of random access memory is connected to the first input of the first AND element and to the sixth output of the control device,  a random access memory sample input is connected to a twenty-fourth output of the control device,  RAM outputs are connected to a data bus,  the inputs of the first zero code selector are connected to the address bus,  the output of the first zero code selector is connected to the fourth input of the first AND element,  the data inputs of the first buffer register are connected to the data bus,  the first control input of the first buffer register is connected to the eighth output of the control device,  the second control input of the first buffer register is connected to the ninth output of the control device,  the outputs of the first buffer register are connected to the data inputs of the third bus driver and to the data inputs of the fourth bus driver,  the control input of the third bus driver is connected to the tenth output of the control device,  the outputs of the third bus driver are connected to the address bus,  the control input of the fourth bus driver is connected to the eleventh output of the control device,  the outputs of the fourth bus driver are connected to the data bus,  the data inputs of the second buffer register are connected to the data bus,  the first control input of the second buffer register is connected to the twelfth output of the control device,  the second control input of the second buffer register is connected to the thirteenth output of the control device,  the third control input of the second buffer register is connected to the fourteenth output of the control device,  the outputs of the second buffer register are connected to the data inputs of the fifth bus driver and to the data inputs of the sixth bus driver,  the control input of the fifth bus driver is connected to the fifteenth output of the control device,  the outputs of the fifth bus driver are connected to the address bus,  the control input of the sixth bus driver is connected to the sixteenth output of the control device,  the outputs of the sixth bus driver are connected to the data bus,  the data inputs of the third buffer register are connected to the data bus,  the control input of the third buffer register is connected to the seventeenth output of the control device,  the outputs of the third buffer register are connected to the data inputs of the seventh bus driver and to the data inputs of the eighth bus driver,  the control input of the seventh bus driver is connected to the eighteenth output of the control device,  the outputs of the seventh bus driver are connected to the address bus,  the control input of the eighth bus driver is connected to the nineteenth output of the control device,  the outputs of the eighth bus driver are connected to the data bus,  the data inputs of the fourth buffer register are connected to the data bus,  the first control input of the fourth buffer register is connected to the twentieth output of the control device,  the second control input of the fourth buffer register is connected to the twenty-first output of the control device,  the outputs of the fourth buffer register are connected to the data inputs of the ninth bus driver and to the data inputs of the tenth bus driver,  the control input of the ninth bus driver is connected to the twenty second output of the control device,  the outputs of the ninth bus driver are connected to the address bus,  the control input of the tenth bus driver is connected to the twenty-third output of the control device,  the outputs of the tenth bus driver are connected to the data bus,  the data inputs of the fifth buffer register are connected to the data bus,  the control input of the fifth buffer register is connected to the output of the first element And,  the outputs of the fifth buffer register are connected to the data inputs of the eleventh bus driver and are the first outputs of the block finding a significant relative locator,  the outputs of the eleventh bus driver are connected to the address bus,  the control input of the eleventh bus driver is connected to the control input of the sixth buffer register and to the seventh output of the control device,  the inputs of the sixth buffer register are connected to the data bus,  the outputs of the sixth buffer register are the second outputs of the block finding a significant relative locator,  the first input of the initialization device and the clock input of the control device are connected to the bus of the second clock signal,  the second inputs of the initialization device are connected to the window size code bus,  the third input of the initialization device is connected to the initialization bus,  the first outputs of the initialization device are connected to the address bus,  the second outputs of the initialization device are connected to the data bus,  moreover, the initialization device contains a second counter,  second multiplexer  third multiplexer  fourth multiplexer,  second null code selector,  a second code comparison scheme,  twelfth bus driver  thirteenth bus driver  fourteenth bus former  moreover, the clock input of the second counter is the first input of the initialization device,  the second inputs of the second multiplexer are connected to the first inputs of the second code comparison circuit and are the second inputs of the initialization device,  the first inputs of the second multiplexer and the second inputs of the third multiplexer are connected to the zero code bus,  the first inputs of the third multiplexer are connected to the unit code bus,  the first outputs of the second counter are connected to the inputs of the second selector of the zero code,  with the second inputs of the second code comparison circuit,  with the third and fourth inputs of the fourth multiplexer and with the data inputs of the fourteenth bus driver,  the second outputs of the second counter are connected to the control inputs of the fourth multiplexer and to the data inputs of the thirteenth bus driver,  the output of the second selector of the zero code is connected to the control input of the second multiplexer,  the output of the second code comparison circuit is connected to the control input of the third multiplexer,  the outputs of the second multiplexer are connected to the first inputs of the fourth multiplexer,  the outputs of the third multiplexer are connected to the second inputs of the fourth multiplexer,  the outputs of the fourth multiplexer are connected to the data inputs of the twelfth bus driver,  the control input of the twelfth bus driver is connected to the control input of the thirteenth bus driver,  with the control input of the fourteenth bus driver and is the third input of the initialization device,  the outputs of the twelfth bus driver are the second outputs of the initialization device,  the outputs of the thirteenth bus driver are the third and fourth outputs of the initialization device,  the outputs of the fourteenth bus driver are the first outputs of the initialization device,  moreover, the decision-making unit for errors contains a second subtractor,  third subtractor  first adder  second adder  third code comparison scheme,  a fourth code comparison scheme,  fifth code comparison scheme,  sixth code comparison scheme,  seventh code comparison scheme,  fifth multiplexer,  sixth multiplexer,  third counter  fourth counter  synchrobit converter;  sequence comparison scheme,  second element AND,  third element AND,  fourth element AND,  first inverter  JK trigger  third null code selector,  multiplier by two,  element NAND,  moreover, the second inputs of the second subtractor are connected to the first inputs of the third subtractor,  with the second inputs of the sixth multiplexer and are the first inputs of the decision block on the presence of errors,  the first inputs of the fourth code comparison circuit are connected to the second inputs of the sixth code comparison circuit and are the second inputs of the decision block for errors  the first inputs of the second subtractor are connected to the second inputs of the third subtractor,  with the first inputs of the sixth multiplexer and are the third inputs of the decision block on the presence of errors,  the second inputs of the fourth code comparison circuit are connected to the first inputs of the fifth code comparison circuit and are the fourth inputs of the decision block for errors  the output of the fourth circuit comparing codes connected to the first control input of the fourth counter,  with the control input of the sixth multiplexer,  with the J-input of the JK trigger and with the third input of the fourth And element,  the outputs of the sixth multiplexer are connected to the first inputs of the first adder,  the outputs of the third counter are connected to the second inputs of the first adder,  the outputs of the first adder are connected to the Converter locators in sync bits,  the output of the sync-to-sync converter is connected to the second input of the sequence comparison circuit,  the output of the sequence comparison circuit is connected to the first input of the third AND element,  the second inputs of the fifth code comparison circuit and the first inputs of the sixth code comparison circuit are connected to the threshold code bus,  the output of the fifth code comparison circuit is connected to the first input of the second AND element,  the output of the sixth code comparison circuit is connected to the second input of the second AND element,  the output of the second element And is connected to the second input of the third element And,  with the input of the first inverter and with the first input of the fourth element And,  the output of the third element And is the fourth output of the decision block on the presence of errors,  the output of the first inverter is the fifth output of the decision block on the presence of errors,  the outputs of the second subtractor are connected to the first inputs of the fifth multiplexer and to the first inputs of the third code comparison circuit,  the outputs of the third subtractor are connected to the second inputs of the fifth multiplexer and to the second inputs of the third code comparison circuit,  the output of the third code comparison circuit is connected to the control input of the fifth multiplexer,  with the second input of the AND-NOT element and is the second output of the decision block on the presence of errors,  the outputs of the fifth multiplexer are connected to the inputs of the third selector zero code,  with the second inputs of the second adder and are the third outputs of the decision block on the presence of errors,  the inverse output of the third selector of the zero code is connected to the fourth input of the fourth element And,  the direct output of the third selector of the zero code is connected to the K-input of the JK trigger and to the second control input of the fourth counter,  the clock input of the JK trigger and the clock input of the fourth counter are connected to the bus of the first clock signal,  the inverse output of the JK trigger is connected to the second input of the fourth element And,  the output of the fourth element And is the first output of the decision block on the presence of errors,  the outputs of the fourth counter are connected to the inputs of the multiplier by two,  the outputs of the multiplier by two are connected to the first inputs of the second adder,  the outputs of the second adder are connected to the first inputs of the seventh code comparison circuit,  the second inputs of the seventh code comparison circuit are connected to the window size code bus,  the output of the seventh code comparison circuit is connected to the first input of the AND-NOT element,  the output of the AND element is NOT connected to the third input of the third AND element,  moreover, the block forming the state stream of the channel contains a D-trigger,  the element is EXCLUSIVE OR,  fifth element AND,  the sixth element And  first element OR  second element OR  second inverter  fifth counter  seventh multiplexer,  eighth multiplexer,  moreover, the D-input of the D-trigger is connected to the second input of the EXCLUSIVE OR element and is the fourth input of the channel state flow generating unit,  the clock input of the D-trigger is connected to the second input of the fifth element And,  with the input of the second inverter,  with the clock input of the fifth counter and with the bus of the third clock signal,  the output of the D-trigger is connected to the first input of the EXCLUSIVE OR element and to the first input of the seventh multiplexer,  the output of the EXCLUSIVE OR element is connected to the first input of the fifth AND element and to the first input of the second OR element,  the output of the fifth AND element is connected to the first input of the first OR element,  the second input of the first OR element is connected to the second input of the second OR element and is the first input of the channel state flow forming unit,  the output of the first OR element is connected to the second input of the sixth AND element,  the first input of the sixth element And is connected to the bus of the fourth clock signal,  the output of the sixth element And is the first output of the channel state flow forming unit,  the output of the second OR element is connected to the load input of the fifth counter,  the fifth counter data inputs are connected to the unit code bus,  the outputs of the fifth counter are connected to the first inputs of the eighth multiplexer,  the second input of the seventh multiplexer is the second input of the channel state flow generating unit,  the second inputs of the eighth multiplexer are the third inputs of the channel state flow generating unit,  the output of the second inverter is connected to the control input of the seventh multiplexer and to the control input of the eighth multiplexer,  the output of the seventh multiplexer and the output of the second inverter are the second outputs of the channel state flow generating unit,  the outputs of the eighth multiplexer are the third outputs of the channel state flow generating unit.

 The interaction of the introduced functional blocks makes it possible to use the proposed device for measuring error parameters in any bit channels and to obtain with it in real time a direct stream of states of the channel under study, which, in addition to information about additive error packets and the intervals between them, also contains exhaustive information about synchronization errors (type of error : insertion or loss of bits and the size of the synchronization error - the number of bits of insertions or drops). The introduction (in addition to some auxiliary elements) of the block for finding the essential locator 8 (providing for the processing of relative locators according to the majority principle) to assess the location of the processed bit in the test sequence allows you to obtain accurate information about synchronization errors in the investigated section of the sequence at the next processing stage (decision block on the availability of Errors 11). The introduction of the channel state flow generation block allows one to obtain information convenient for registration that is received from the output of the decision block on the presence of errors 11.

 The invention consists in the following. To detect synchronization errors, test sequences (M-sequences, De Bruin sequences, modified De Bruin sequences) are used, which are characterized by the fact that any consecutive m bits of a sequence (sync symbols) uniquely determine its phase. The test sequence received from the channel is converted into a stream of sync symbols, in which two sequences of the same length (windows) are distinguished. Based on the analysis of sync symbols, in each window, the left and right estimates of the location of the current analyzed bit of the test sequence (located in the center between the windows) are formed. The found estimates make it possible to determine the presence and value of insertions or bit drops in the analyzed section of the test sequence. By the difference in the estimates, one can judge the size of the insertion or loss. If the difference in the estimates is zero, then there are no inserts or bits in the analyzed section of the test sequence. The use of the majority principle of the analysis of synchronization symbols in determining estimates allows localization of synchronization errors against the background of additive errors and the determination of the number of bits of insertions and drops out with high accuracy.

In FIG. 1 shows a functional diagram of the proposed device for measuring error parameters in the channel; figure 2 shows the functional diagram of the block finding a significant relative locator; figure 3 shows the functional diagram of the initialization device (block finding a significant relative locator); figure 4 shows the functional diagram of the decision-making unit on the presence of errors; figure 5 shows the functional block diagram of the formation of the channel state stream; in Fig.6 shows a linear shift register with feedback for the case m = 5, the M-sequence generated by this register, as well as the correspondence table of locators and sync symbols for this sequence; Fig. 7 illustrates the principle of replacing two blocks for finding a significant relative locator with one with buffering its output data; in Fig.8 shows the algorithm of operation of the block finding a significant relative locator; figure 9 shows an example of the contents of the buffer relative locators and the corresponding contents of four arrays (which are allocated in the random access memory), as well as the table shows the values that fill the arrays at the beginning of the device; figure 10 shows a table of control signals y ₁ ... y ₂₃ . generated by the control unit finding the significant relative locator; 11 is a table explaining the operation of the block forming the channel state stream; on Fig shows timing diagrams of the clock signals of the device for measuring error parameters in the channel; 13-16 are examples of the operation of the device for measuring error parameters at various error configurations.

In the description of the device and in the drawings, the following notation is used:
m is the degree of the generating polynomial of the M-sequence (the number of steps of the linear shift register with feedbacks),
n is the period of the pseudo-random sequence,
A is a sync symbol
L is the sync symbol locator,
CT2 - binary counter,
RG - register,
SM - adder
SB is a subtractor,
FIFO - buffer (a set of registers connected in series by m-bit buses),
BF - bus driver
RAM - random access memory
MUX - multiplexer,
ША - address bus,
SD - data bus,
UI - initialization device,
UU - control device,
INLOC - incoming relative locator (in locator),
OUTLOC - outgoing locator,
ENABLE - the signal of permission of the operation of the block finding the significant relative locator,
RLOC - the relative relative locator
NUM - weight of the significant relative locator (number),
LRLOC - the essential relative locator of the left window (left relative locator),
LNUM - weight of the significant relative locator of the left window,
RRLOC - the right relative locator,
RNUM - weight of the significant relative locator of the right window,
CB - central bit (common for the left and right windows) (central bit),
SYNCERR, SE - synchronization error signal,
INS / DEL - type of synchronization error: insertion or loss of bits (insertion / deletion),
DL - size of the synchronization error (number of bits),
NOISE - signal of impossibility of correct measurement of error parameters (noise),
ADDERR, AE - additive error signal,
WRITE - recording strobe for an external device for recording error information,
ERRTYPE - error type
ERRSIZE - error size
WINSIZE, WS - buffer size of relative locators (window size),
INIT - the initialization signal for the initialization device of the block finding significant relative locators,
THRESHOLD - threshold for the weights of the significant relative locators of the left and right windows,
CLK is the first clock
CLK2 - the second clock signal,
CLK3 - the third clock signal,
CLK4 - the fourth clock signal,
REG1 - buffer register 16,
REG2 - buffer register 19,
REG3 - buffer register 22,
REG4 - buffer register 25.

Num - an array designed to store the number of corresponding locators (number),
Loc - an array in which locators are stored in descending order of their frequency of occurrence in the buffer of relative locators (locator),
Pos - an array mutually inverse to the Loc (position) array,
LB - an array designed to store the left borders of groups of the same number of locators, as if the locators were sorted (left bound),
Numi, Loci, Posi, LB1 - designations reflecting the contents of the buffer registers REG1, REG2, REG3, REG4 and related to the processing of the incoming significant relative locator (INLOC),
Num2, Eoc2, Pos2, LB2 - designations reflecting the contents of the buffer registers REG1, REG2, REG3, REG4 and related to the processing of the outgoing significant relative locator (OUTLOC),
ROM - read-only memory.

 The device for measuring error parameters (Fig. 1) contains a first shift register (1), a second shift register (5), a converter of sync symbols to locators (2), a first subtractor (3), a first counter (4), a buffer of relative locators (6) , the first code comparison scheme (7), the block for finding the significant relative locator (8), the buffer for the significant relative locators (9), the buffer for the weights of the relative relative locators (10), the block for deciding whether there are errors (11), the block for generating the channel state stream (12).

 An analyzed bit sequence is fed to the input of the first shift register (1). The first output of the first shift register (1) is connected to the input of the second shift register (5). The output of the second shift register (5) is connected to the first input of the sequence comparison circuit (52). The inputs of the sync converter to the locators (2) are connected to the second outputs of the first shift register (1). The first inputs of the first subtractor (3) are connected to the outputs of the sync symbol converter into locators (2), the second inputs of the first subtractor (3) are connected to the outputs of the first counter (4), the outputs of the first subtractor (3) are connected to the inputs of the relative locator buffer (6), with the first inputs of the first circuit for comparing codes (7) and with the first inputs of the block for finding a significant relative locator (8). The outputs of the relative locator buffer (6) are connected to the second inputs of the first code comparison circuit (7) and to the second inputs of the block of finding the significant relative locator (8). The output of the first code comparison circuit (7) is connected to the third input of the block for finding a significant relative locator (8). The first outputs of the block of finding the significant relative locator (8) are connected to the inputs of the buffer of the significant relative locators (9) and to the first inputs of the block for deciding the presence of errors (11), the second outputs of the block of finding the significant relative locator (8) are connected to the inputs of the buffer of the weights of significant relative locators (10) and with the second inputs of the decision block on the presence of errors (11). The outputs of the buffer of significant relative locators (9) are connected to the third inputs of the decision block on the presence of errors (11). The outputs of the weight buffer of the significant relative locators (10) are connected to the fourth inputs of the decision block on the presence of errors (11). The first output of the error decision block (11) is connected to the first input of the channel state flow generation block (12), the second output of the error decision block (11) is connected to the second input of the channel state flow generation block (12), third outputs an error decision block (11) is connected to the third inputs of the channel state flow generation block (12), the fourth output of the error decision block (11) is connected to the fourth input of the channel state flow generation block (12), the fifth output of the block making a decision about the presence of errors (11) generates a signal "Measurement Failure" for the error information recording device. The first output of the channel state stream generating unit (12) generates a “recording strobe” signal for the error information recording device, the second outputs of the channel state stream generating unit (12) generate the error type signal for the error information registration device, the third outputs of the forming unit the channel state stream (12) generates an error size signal for the error information recording device.

 The essential relative locator locator (FIG. 2) contains a first multiplexer (13), a first bus driver (15), a second bus driver (14), a third bus driver (17), a fourth bus driver (18), and a fifth bus driver (20) ), the sixth bus driver (21), the seventh bus driver (23), the eighth bus driver (24), the ninth bus driver (26), the tenth bus driver (27), the eleventh bus driver (32), the first buffer register (16) , second buffer register (19), third buffer register (22 ), the fourth buffer register (25), the fifth buffer register (31), the sixth buffer register (33), the first zero code selector (28), random access memory (29), the first AND element (30), the initialization device (34) control device (35).

 The first inputs of the first multiplexer (13) are the first inputs of the block finding the significant relative locator (8), the second inputs of the first multiplexer (13) are the second inputs of the block finding the significant relative locator (8), the enable input of the control device (35) is the third block input finding a significant relative locator (8). The control input of the first multiplexer (13) is connected to the first output of the control device (35), the outputs of the first multiplexer (13) are connected to the data inputs of the first bus driver (15) and to the data inputs of the second bus driver (14). The control input of the first bus driver (15) is connected to the second output of the control device (35), the control input of the second bus driver (14) is connected to the third output of the control device (35), the outputs of the first bus driver (15) are connected to the address bus, the outputs of the second bus driver (14) connected to the data bus. The first address inputs of random access memory (29) are connected to the address bus, the second address input of random access memory (29) is connected to the third input of the first element And (30), to the fourth output of the control device (35) and to the third output of the initialization device (34 ), the third address input of random access memory (29) is connected to the second input of the first AND element (30), to the fifth output of the control device (35) and to the fourth output of the initialization device (34), the read / write control input is operative memory device (29) is connected to the first input of the first element And (30) and to the sixth output of the control device (35), a sample input of random access memory (29) is connected to the twenty-fourth output of the control device (35), data outputs of random access memory (29) connected to the data bus. The inputs of the first zero code selector (28) are connected to the address bus, the output of the first zero code selector (28) is connected to the fourth input of the first AND element (30). The data inputs of the first buffer register (16) are connected to the data bus, the first control input of the first buffer register (16) is connected to the eighth output of the control device (35), the second control input of the first buffer register (16) is connected to the ninth output of the control device (35) , the outputs of the first buffer register (16) are connected to the data inputs of the third bus driver (17) and to the data inputs of the fourth bus driver (18). The control input of the third bus driver (17) is connected to the tenth output of the control device (35), the outputs of the third bus driver (17) are connected to the address bus. The control input of the fourth bus driver (18) is connected to the eleventh output of the control device (35), the outputs of the fourth bus driver (18) are connected to the data bus. The data inputs of the second buffer register (19) are connected to the data bus, the first control input of the second buffer register (19) is connected to the twelfth output of the control device (35), the second control input of the second buffer register (19) is connected to the thirteenth output of the control device (35) , the third control input of the second buffer register (19) is connected to the fourteenth output of the control device (35), the outputs of the second buffer register (19) are connected to the data inputs of the fifth bus driver (20) and to the data inputs of the sixth bus ormirovatelya (21). The control input of the fifth bus driver (20) is connected to the fifteenth output of the control device (35), the outputs of the fifth bus driver (20) are connected to the address bus. The control input of the sixth bus driver (21) is connected to the sixteenth output of the control device (35), the outputs of the sixth bus driver (21) are connected to the data bus. The data inputs of the third buffer register (22) are connected to the data bus, the control input of the third buffer register (22) is connected to the seventeenth output of the control device (35), the outputs of the third buffer register (22) are connected to the data inputs of the seventh bus driver (23) and data inputs of the eighth bus driver (24). The control input of the seventh bus driver (23) is connected to the eighteenth output of the control device (35), the outputs of the seventh bus driver (23) are connected to the address bus. The control input of the eighth bus driver (24) is connected to the nineteenth output of the control device (35), the outputs of the eighth bus driver (24) are connected to the data bus. The data inputs of the fourth buffer register (25) are connected to the data bus, the first control input of the fourth buffer register (25) is connected to the twentieth output of the control device (35), the second control input of the fourth buffer register (25) is connected to the twenty-first output of the control device (35) ), the outputs of the fourth buffer register (25) are connected to the data inputs of the ninth bus driver (26) and to the data inputs of the tenth bus driver (27). The control input of the ninth bus driver (26) is connected to the twenty-second output of the control device (35), the outputs of the ninth bus driver (26) are connected to the address bus. The control input of the tenth bus driver (27) is connected to the twenty-third output of the control device (35), the outputs of the tenth bus driver (27) are connected to the data bus. The data inputs of the fifth buffer register (31) are connected to the data bus, the control input of the fifth buffer register (31) is connected to the output of the first element And (30), the outputs of the fifth buffer register (31) are connected to the data inputs of the eleventh bus driver (32) and are the first outputs of the block finding a significant relative locator (8). The outputs of the eleventh bus driver (32) are connected to the address bus, the control input of the eleventh bus driver (32) is connected to the control input of the sixth buffer register (33) and to the seventh output of the control device (35). The data inputs of the sixth buffer register (33) are connected to the data bus, the outputs of the sixth buffer register (33) are the second outputs of the block of finding a significant relative locator (8). A second clock signal is supplied to the first input of the initialization device (34) and to the clock input of the control device (35), a window size code is supplied to the second inputs of the initialization device (34), an initialization signal is sent to the third input of the initialization device (34), the first outputs of the device initialization (34) are connected to the address bus, the second outputs of the initialization device (34) are connected to the data bus.

 The initialization device (Fig. 3) contains a second counter (36), a second multiplexer (39), a third multiplexer (40), a fourth multiplexer (41), a second zero code selector (37), a second code comparison circuit (38), and a twelfth bus driver (42), thirteenth bus driver (43), fourteenth tire driver (44).

 The clock input of the second counter (36) is the first input of the initialization device (34). The second inputs of the second multiplexer (39) are connected to the first inputs of the second code comparison circuit (38) and are the second inputs of the initialization device (34). A zero code is supplied to the first inputs of the second multiplexer (39) and to the second inputs of the third multiplexer (40), a unit code is supplied to the first inputs of the third multiplexer (40). The first outputs of the second counter (36) are connected to the inputs of the second zero code selector (37), with the second inputs of the second code comparison circuit (38), with the third and fourth inputs of the fourth multiplexer (41) and with the data inputs of the fourteenth bus driver (44). The second outputs of the second counter (36) are connected to the control inputs of the fourth multiplexer (41) and to the data inputs of the thirteenth bus driver (43). The output of the second zero code selector (37) is connected to the control input of the second multiplexer (39). The output of the second code comparison circuit (38) is connected to the control input of the third multiplexer (40). The outputs of the second multiplexer (39) are connected to the first inputs of the fourth multiplexer (41). The outputs of the third multiplexer (40) are connected to the second inputs of the fourth multiplexer (41). The outputs of the fourth multiplexer (41) are connected to the data inputs of the twelfth bus driver (42). The control input of the twelfth bus driver (42) is connected to the control input of the thirteenth bus driver (43), with the control input of the fourteenth bus driver (44) and is the third input of the initialization device (34). The outputs of the twelfth bus driver (42) are the second outputs of the initialization device (34), the outputs of the thirteenth bus driver (43) are the third and fourth outputs of the initialization device (34), the outputs of the fourteenth bus driver (44) are the first outputs of the initialization device (34).

 The error decision block (Fig. 4) contains a second subtractor (45), a third subtractor (46), a first adder (50), a second adder (65), a third code comparison scheme (60), a fourth code comparison scheme (47 ), a fifth code comparison scheme (54), a sixth code comparison scheme (55), a seventh code comparison scheme (66), a fifth multiplexer (61), a sixth multiplexer (48), a third counter (49), a fourth counter (63), a sync-to-sync converter (51), a sequence comparison circuit (52), a second I element (56), a third I element (53), a fourth I element (59), trans high inverter (57), JK-trigger (58), third zero code selector (62), two multiplier (64), AND-NOT element (67).

 The second inputs of the second subtractor (45) are connected to the first inputs of the third subtractor (46), with the second inputs of the sixth multiplexer (48) and are the first inputs of the decision block on the presence of errors (11). The first inputs of the fourth code comparison circuit (47) are connected to the second inputs of the sixth code comparison circuit (55) and are the second inputs of the decision block for errors (11). The first inputs of the second subtractor (45) are connected to the second inputs of the third subtractor (46), with the first inputs of the sixth multiplexer (48) and are the third inputs of the decision block on the presence of errors (11). The second inputs of the fourth code comparison circuit (47) are connected to the first inputs of the fifth code comparison circuit (54) and are the fourth inputs of the error decision block (11), the output of the fourth code comparison circuit (47) is connected to the first control input of the fourth counter ( 63), with the control input of the sixth multiplexer (48), with the J-input of the JK trigger (58) and with the third input of the fourth AND element (59). The outputs of the sixth multiplexer (48) are connected to the first inputs of the first adder (50). The outputs of the third counter (49) are connected to the second inputs of the first adder (50), the outputs of the first adder (50) are connected to the sync-to-sync converter (51), the output of the sync-to-sync converter (51) is connected to the second input of the sequence comparison circuit (52) , the output of the sequence comparison circuit (52) is connected to the first input of the third AND element (53). A threshold code is supplied to the second inputs of the fifth code comparison circuit (54) and to the first inputs of the sixth code comparison circuit (55). The output of the fifth code comparison circuit (54) is connected to the first input of the second AND element (56). The output of the sixth code comparison circuit (55) is connected to the second input of the second AND element (56). The output of the second element And (56) is connected to the second input of the third element And (53), with the input of the first inverter (57) and with the first input of the fourth element And (59). The output of the third element And (53) is the fourth output of the decision block on the presence of errors (11). The output of the first inverter (57) is the fifth output of the decision block on the presence of errors (11). The outputs of the second subtractor (45) are connected to the first inputs of the fifth multiplexer (61) and to the first inputs of the third code comparison circuit (60). The outputs of the third subtractor (46) are connected to the second inputs of the fifth multiplexer (61) and to the second inputs of the third code comparison circuit (60). The output of the third code comparison circuit (60) is connected to the control input of the fifth multiplexer (61), with the second input of the AND-NOT element (67) and is the second output of the decision block on the presence of errors (11). The outputs of the fifth multiplexer (61) are connected to the inputs of the third selector of the zero code (62), with the second inputs of the second adder (65) and are the third outputs of the decision block on the presence of errors (11). The inverse output of the third zero code selector (62) is connected to the fourth input of the fourth AND element (59), the direct output of the third zero code selector (62) is connected to the K-input of the JK trigger (58) and to the second control input of the fourth counter (63) . The clock input of the JK trigger (58) and the clock input of the fourth counter (63) are supplied with the first clock signal. The inverse output of the JK trigger (58) is connected to the second input of the fourth element And (59), the output of the fourth element And (59) is the first output of the decision block on the presence of errors (11). The outputs of the fourth counter (63) are connected to the inputs of the multiplier by two (64), the outputs of the multiplier by two (64) are connected to the first inputs of the second adder (65), the outputs of the second adder (65) are connected to the first inputs of the seventh code comparison circuit (66) . The window size code is supplied to the second inputs of the seventh code comparison circuit (66), the output of the seventh code comparison circuit (66) is connected to the first input of the AND-NOT element (67), the output of the AND-NOT element (67) is connected to the third input of the third AND element (53).

 The channel state flow generating unit (FIG. 5) contains a D-trigger (68), an EXCLUSIVE OR element (69), a fifth AND element (70), a sixth AND element (75), a first OR element (71), a second OR element ( 72), the second inverter (74), the fifth counter (73), the seventh multiplexer (76), the eighth multiplexer (77).

 The D-input of the D-trigger (68) is connected to the second input of the EXCLUSIVE OR element (69) and is the fourth input of the channel state flow generating unit (12), the clock input of the D-trigger (68) is connected to the second input of the fifth AND element (70) , with the input of the second inverter (74), with the clock input of the fifth counter (73) and the third clock signal is applied to it, the output of the D-trigger (68) is connected to the first input of the EXCLUSIVE OR element (69) and to the first input of the seventh multiplexer (76) ) The output of the EXCLUSIVE OR element (69) is connected to the first input of the fifth AND element (70) and to the first input of the second OR element (72). The output of the fifth AND element (70) is connected to the first input of the first OR element (71). The second input of the first OR element (71) is connected to the second input of the second OR element (72) and is the first input of the channel state flow forming unit (12). The output of the first OR element (71) is connected to the second input of the sixth AND element (75). The fourth clock signal is supplied to the first input of the sixth element And (75), the output of the sixth element And (75) is the first output of the channel state flow forming unit (12). The output of the second OR element (72) is connected to the boot input of the fifth counter (73). The unit code is supplied to the data inputs of the fifth counter (73), the outputs of the fifth counter (73) are connected to the first inputs of the eighth multiplexer (77). The second input of the seventh multiplexer (76) is the second input of the channel state flow generating unit (12). The second inputs of the eighth multiplexer (77) are the third inputs of the channel state flow forming unit (12). The output of the second inverter (74) is connected to the control input of the seventh multiplexer (76) and to the control input of the eighth multiplexer (77). The output of the seventh multiplexer (76) and the output of the second inverter (74) are the second outputs of the channel state flow generating unit (12). The outputs of the eighth multiplexer (77) are the third outputs of the channel state flow forming unit (12).

 The operation of the device for measuring error parameters in a channel is based on the use of sequences, characterized by the fact that any consecutive m bits of a sequence uniquely determine its phase (location of all bits of a sequence) as test sequences transmitted through the channel. Such sequences include M-sequences, De Bruin binary sequences, as well as modified De Bruin binary sequences.

M-sequence is a binary linear recurrence sequence, each member of which with the number j + m is a linear combination of the previous m members:
a _{j + m} = c ₁ a _{j + m-1} + c ₂ a _{j + m-2} + ... + c _m a _j ,
where the coefficients with _k take values from a binary field. To build such a sequence, it is enough to know m following symbols in a row (bits).

The M-sequence has a period n = -2 ^m -l (m is the degree of the generating polynomial of the sequence). A selection from a sequence of n consecutive m-bit characters is a permutation of numbers from 1 to 2 ^m -1 A _j = (a _j , a _{j + 1} , ..., a _{j + m-1} ), j = 0,1 ,. .., n-1. In the invention, A _j will be called the sync symbol, and the index _j will be called the sync symbol locator (the locator is actually the serial number of the sync symbol on one period of the test sequence). In this case, the element a _j will be called synchrobite, and the index j with it will be called the sync bit locator.

In FIG. 6a shows a linear feedback shift register, which corresponds to the generating polynomial f (x) = x ⁵ + x ² +1 (in this case m = 5), and the M-sequence generated by this register. The subsequent bits of the M-sequence are located in the figure on the left with respect to the previous bits. On figb shows a table of correspondence of locators and sync symbols for this sequence. Below this sequence will be used to illustrate the operation of the device.

 The determination of the values of the inserts and depositions using the considered test sequences can be performed as follows.

The test sequence received from the channel is converted into a stream of sync symbols, in which two sequences of the same length k are allocated, having one common sync bit a _i :
(A _{i + k-1} , A _{i + k-2} , ..., A _{i + 1} , A _i )
and
(A _{i-m + 1} , A _im , ..., A _{i-k + 2-m + 1} , A _{i-k + 1-m + 1} ).

 In the invention, these sequences will be referred to as left and right windows.

In each window, you can find the sync locators and count them modulo n relative to the sync bit a _i . Thus, two vectors of estimates of the locator of the current bit a _i are obtained:
{L (A _{i + k-1} ) -k + 1, L (A _{i + k-2} ) -k + 2, ..., L (A _{i + 1} ) -l, L (A _i )}
and
{L (A _{i-m + 1} ) + m-1, L (A _im ) + m, ..., L (A _{i-k + 2-m + 1} ) + k-2 + m-1;
L (A _{i-k + 1-m + 1} ) + k-1 + m-1}.

Here L (A _i ) denotes the operator of finding the sync locator A _i .

By analyzing these vectors, it is possible to form estimates of locators on the left L _l and on the right L _r . As an assessment, it is advisable to choose the locator, which is most often found in the window vector. In the invention, it will be called an essential locator. The number of occurrences of the locator in the window vector will be called its weight.

An essential locator uniquely determines the phase of a sequence in a window. By the difference between the essential locators of the left and right windows ΔL, one can judge the size of the insertion ΔL _insertion or loss ΔL _deletion .

ΔL _insertion = (L _r -L _l ) mod n; (1)
ΔL _deletion = (L _l -L _r ) mod n.

If ΔL = 0, then there is no insertion or loss of bits. The value of insertions and depositions is determined accurate to a period n
M-sequences. The smaller of ΔL _insertion and ΔL _deletion determines what happened: insert or drop out.

 The location of the inserts or drops in the test sequence is determined by the time when the weight of the essential locator of the left window exceeds the weight of the essential locator of the right window.

 To determine the insertions and depositions, the difference between the estimates of the locators of the current bit on the right and left is important; estimates of the values of the locators themselves are not necessary to find explicitly. Therefore, the procedure for finding insertions and depositions can be modified in order to simplify the implementation as follows.

First, the stream of sync symbols A _{i is} converted into a stream of locators L (A _i ). Then the locators are converted into relative locators rL _i by subtracting _i from them modulo n, where i is a variable that identifies the current processed bit of the test sequence, which is incremented at each clock cycle of the device. The sequence of relative locators in the absence of errors will be a constant sequence. For any ith bit of the test sequence, the corresponding locator can be restored by adding the value of i modulo n to the relative locator.

To evaluate the relative locator of the current bit, two windows are allocated in the sequence of relative locators on the left and right:
{rL _{i + k-1} , rL _{i + k-2} , ..., rL _{i + 1} , rL _i }
and
{rL _{i-m + l} , rL _im , ..., rL _{i-k + 2-m + 1} , rL _{i-k + 1-m + 1} }.

The significant relative locators of these windows will give estimates of the relative locators of the current bit on the left rL _i and on the right rL _r . Formula (1) in this case takes the form
ΔL _insertion = (rL _r -rL _l ) mod n; (2)
ΔL _deletion = (rL _l -rL _r ) mod n.

 A device for measuring error parameters in a channel operates as follows.

The m-bit shift register 1 (FIG. 1) converts the input bit test sequence into a sequence of sync symbols, which in turn converts the sync symbols to locators 2 into a sequence of locators. The sync converter to locators 2 can be implemented on ROM (with a capacity of 2 ^m m-bit words).

Subtractor 3 subtracts from each locator received at the input the current value of counter 4 containing the variable i. Thus, a sequence of relative locators is obtained, which from the output of the subtractor 3 goes to the input of the buffer of relative locators 6. In the case of using the M-sequence as a test sequence, the reference test sequence does not have a zero sync symbol (Fig.6), which corresponds to the locator 2 ^m - l (all units). But he can meet in the test sequence received from the channel due to errors. Therefore, the subtractor 3 must track the appearance of the locator 2 ^m -l at the input and output the value 2 ^m -1 (without actually subtracting it). This is necessary to exclude the influence of deliberately erroneous locators that do not exist in the reference sequence on the decision on the presence of synchronization errors. In the case of using De Bruyne as test sequences, this is not required and subtractor 3 is the usual subtraction scheme (since in this case the period of the sequence and, accordingly, the module are n = 2 ^m ).

 The shift register 5 is designed to delay the bits of the test sequence, which is then used to detect additive errors. This delay is necessary to agree on the decision points about the presence of additive errors and synchronization errors. The number of steps in shift register 5 is WINST7E-1 (one less than the size of the window).

The unit for finding the essential relative locator 8, which is based on the majority principle, forms a locator (RLOC) in each clock cycle, which at the moment is most often found in the buffer of relative locators 6. This essential locator corresponds to the weight (NUM), t. e. the number of occurrences of the locator in the buffer of relative locators 6, which is also present at the output of block 8. The number of steps in the buffer of relative locators is equal to WINSIZE (window size) and should not exceed a threshold of 2 ^m -1 (this is due to the capacity of random access memory 29 in the block finding significant relative locators 8). If the relative locators coming to the input of the buffer of relative locators 6 and the ones coming out of it coincide, then processing is not required and the essential relative locator does not change. Therefore, the block for finding a significant relative locator is activated only if the incoming and outgoing relative locators are different. The enable signal (ENABLE) of the block finding the significant relative locator 8 is generated by the circuit for comparing codes 7. In the absence of any errors, the block finding the significant relative locator 8 is inactive.

 The flow of significant relative locators and their weights is delayed by a buffer of significant relative locators 9 and a buffer of weights of significant relative locators 10, respectively, which each contain WTNSIZE + m-2 steps. Locators and weights at the inputs of buffers correspond to the left window, and delayed locators and delayed weights at the output of buffers correspond to the right window. The use of one block finding a significant relative locator for two windows greatly simplifies the device. This is possible due to the complete functional equivalence of the aggregate of 6, 7, 8, 9 and 10 blocks of the device (as illustrated in Fig. 7a) of the aggregate of blocks shown in Fig. 7b.

 The decision block on the presence of errors 11 based on the analysis of the difference between the essential relative locators of the left and right windows (LRLOC and RRLOC), as well as the values of their weights (LNUM and RNUM) makes a decision on the presence of a synchronization error at the given time (insert / drop bits) . If a synchronization error is detected, the SYNCERR signal is issued to the output of the decision-making unit about the presence of errors 11, as well as its accompanying signals: INS / DEL (type of detected synchronization error: insert or drop out) and DL (size of the synchronization error - number of bits). The decision-making unit on the presence of errors also reconstructs the correct value of the central bit of the analyzed section of the test sequence using essential relative locators and compares it with its real (delayed) value, which comes from the second shift register 5. In case of inequality of these bits, an additive error is fixed. If this error was not caused by the insertion of bits, then the output of the decision block on the presence of errors 11 gives a signal about the presence of the additive error ADDERR. If the level of additive errors has exceeded a predetermined threshold and the weights of significant relative locators have decreased so that it is impossible to correctly decide on the presence of errors at the moment, then a NOISE signal (impossibility of correctly measuring error parameters) is generated for the error information recording device. The presence of this signal indicates that all information issued by the device for measuring error parameters is currently incorrect, and this should be taken into account in the subsequent processing of the channel state stream.

 The channel 12 state flow generation unit, based on the information received from the decision block on the presence of errors 11, generates WRITE recording strobes for error information recording device and the channel status information accompanying them for a certain period of time: error type ERRTYPE and error size ERRSIZE. Error-free states and additive errors are collected by the channel state flow forming unit in packets. The block identifies 4 types of channel states, as shown in the table.

 Let us consider in more detail the operation of the main blocks of the device for measuring error parameters in the channel.

The unit for finding a significant relative locator (Fig. 2) is an automaton containing random access memory, in which four identical sections of memory, six buffer registers, a control device, an initialization device, and a number of auxiliary elements are allocated. This machine allows you to implement the following simple operations: transferring data between random access memory and one of four registers, transferring data between two registers (bus shapers are used for this), increment operations (adding units) and decrements (subtracting units) of registers. The forwarding operation is implemented as follows. Data is transferred from one register to another directly via the data bus. Data transfer between the random access memory cell and one of the four registers is also performed via the data bus, but requires the selection of one of four memory sections by setting the values from zero to three on the upper bits of the address bus, and the cell numbers on the lower bits of the address bus. Signals y ₁ ... y ₂₃ determine the source and receiver during data transfer, and also specify the type of arithmetic operation for buffer registers.

 The block for finding a significant relative locator implements the algorithm shown in Fig. 8. In the algorithm, two independent parts can be arbitrarily distinguished: processing the incoming locator and then processing the output locator. The right side of the table shows the contents of each of the four buffer registers (16, 19, 22, and 25) before performing the operation indicated in the left half of the table.

 Four sections of memory allocated in the random access memory are intended for storing the following arrays. The Num array stores the number of corresponding relative locators that are currently present in the relative locator buffer (the index in the array is the locator). The Loc array is designed to store locators in decreasing order of their number, i.e., the locator, most often found at the moment in the relative locators buffer (essential locator), is stored at the zero address, and the locator, least often found at this address, is stored moment in the buffer of relative locators (the index in the array is the serial number of the locator). The Pos array is designed to store the positions of locators in a sorted array (the index in the array is a locator). The Pos array is mutually inverse to the Loc array, i.e. for the Loc and Pos arrays, the relations Loc [Pos [i]] = i and Pos [Loc [i]] = i are satisfied, where i is an arbitrary index. The LB array is designed to store the left borders of groups of equal numbers of locators, as if the locators were sorted.

 Fig. 9a shows an example of the contents of the buffer of relative locators 6 and the corresponding correct contents of four arrays (Num, Loc, Pos and LB) of the block for finding significant relative locators 8 for the case m = 3.

 Using the null code selector 28 and the And 30 element, the entry is tracked to the Loc locator array at the zero address. In this case, the value (significant relative locator) present on the data bus is written to the buffer register 31. Thus, elements 28, 30 reduce the operating time of the block for finding the significant relative locator 8 by eliminating the additional read operation from the Loc array at the zero address to determine significant relative locator.

To implement the algorithm (Fig. 8), the control device 35 provides for 21 cycles CLK2 the issuance of control signals y ₁ ... y ₂₃ shown in Fig. 10. The signal at ₂₄ , which is responsible for selecting the RAM chip 29, is set to a logical unit in each CLK2 clock some time after the data are installed on the address and data buses and is reset after a certain period of time, which ensures guaranteed recording. The data at the output of the block of finding the significant relative locator 8 (the value of the significant relative locator and its weight) is ready by the end of clock 18 of CLK2.

The initialization device (figure 3) is intended for the initial filling of the cells of random access memory. At the very beginning of the operation of the device for measuring error parameters in the channel, it is assumed that the buffer of relative locators 6 is initialized to zero values. Therefore, the initialization device 34 fills the four arrays with the values given in the table in FIG. 9b. The cells of the random access memory 29 will be filled with the indicated values after 2 ^{m + 2} clock cycles after the INTT signal. After that, the INIT signal should be removed. The initialization device is clocked by the signal CLK2.

 The decision block on the presence of errors (figure 4) operates as follows. The subtractor 45 subtracts the locator of the left window from the locator of the right window, and the locator of the right window subtracts the locator of the right window from the locator of the left window. Both subtractors subtract modulo n. From the two values obtained, the smaller ΔL value is selected by the comparison circuit 60 and the multiplexer 61, thereby determining the size of the synchronization error that is currently present within two windows. If ΔL = 0, then there are no synchronization errors on the analyzed segment of the sequence (this fact is determined by the selector of the zero code 62). At the output of the code comparison circuit 60, a logical unit code is present in case of insertion of bits and a logic zero code in case of detection of bit loss (or in case ΔL = 0).

 If a synchronization error is detected (a logical unit is present on the inverse output of the zero code selector 62) and the weight of the significant relative locator of the left window exceeds the weight of the significant relative locator of the right window (the logic unit is present on the output of the code comparison circuit), and in the previous clock (state JK- 58) was the opposite (the weight of the significant relative locator of the right window was greater than the weight of the significant relative locator of the left window), this means that the center of the synchronization error is currently between two windows and registration is required. At this moment, the output of the AND 59 element contains a synchronization error detection signal (logical unit). Thus, information on the parameters of the synchronization error (INS / DEL, DL) is present all the time at the output of the decision block on the presence of errors, while the synchronization error is within two windows, but a signal about its detection is issued only when the center of the synchronization error is in the center between two windows (where they virtually overlap one bit). In the absence of synchronization errors, the JK-trigger 58 is reset. The use of the JK-trigger in the circuit is due to the need to eliminate the possible "bounce" of the signal at the output of element 47 when a synchronization error is detected (the presence of a logic zero at the direct output of the zero code selector 62), which will lead to logging more than one synchronization error.

The chain of elements 48, 49, 50, 51 (the counter 49 and the adder 50 function modulo n) is designed to restore the correct value of the central bit. With the help of multiplexer 48, a substantial relative locator having a greater weight is selected. The counter 49 (clocked by the CLK signal), operating modulo n, is shifted down (modulo n) relative to counter 4 by the number of steps of shift register 5, i.e. on WINSIZE-1. This is necessary for the inverse conversion of the relative locator from the output of multiplexer 49 to a true locator, which, in turn, is converted by the converter of locators to sync bits 51 into the correct bit located in the center between two windows. In fact, the operation is performed that is inverse to the operation performed by elements 2, 3, 4 at the initial stage, except that it does not require complete restoration of the sync symbol, but it is enough to restore one bit of it. Further, the sequence comparison circuit 52 (which is actually the EXCLUSIVE OR element) compares the reconstructed correct bit and the actual central bit delayed by the shift register 5. The logical unit present at the output of the And 53 element means that an additive error has been detected. The converter of locators to sync bits 51 can be implemented on ROM (with a capacity of 2 ^m 1-bit words, i.e., bit).

 If the weight of at least one significant locator (a chain of elements from two schemes for comparing codes 54, 55 and the And 56 element serves to determine this fact) has significantly decreased (which is determined by the THRESHOLD threshold), this means that a large level is observed in the channel additive errors. The latter circumstance in this case makes it impossible to correctly measure the error parameters, therefore at this moment a logical zero is present at the output of the And 56 element, which blocks the output of error information (ADDERR and SYNCERR signals) and a noise signal is output to the decision block about the presence of errors ( NOISE), which should be used by the device for recording error information during further processing of the channel state stream.

The chain of elements, consisting of a counter 63, a two 64 multiplier, an adder 65, a code comparison circuit 66, and an And 67 element, is designed to block the registration of additive errors for a while when a synchronization error such as bit insertion is detected, since in this case the additive errors are caused by the latter . The counter 63 is reset in the absence of synchronization errors, and upon detection, it starts to count upwards until the center of the synchronization error is within the left window (which is determined by the ratio of the weights of the significant relative locators), and then downward when the center of the synchronization error will move to the right window. Note that the synchronization error begins to be recorded from the moment when its center is in the center of the left window, and until the moment when its center is in the center of the right window. In fact, the specified chain of elements checks the condition:
CNT + ΔL / 2> WINSIZE / 2
or
2 • CNT + ΔL> WINSIZE,
where CNT is the current state of the counter, ΔL is the size of the synchronization error.

 If the specified condition is met and if the type of synchronization error is insert, then registration of additive errors is blocked (until the insert bits completely move to the right window).

 Counter 63 is a counter with a zero lock, i.e. the current value of the counter does not change when the counter reaches a value of zero during the countdown (from large values to smaller ones). A two-multiplier is not actually a functional element, since it is realized by a simple rearrangement of conductors in the bus.

The channel state flow generation unit (Fig. 5), based on the information received from the decision block on the presence of errors 11 (SYNCERR, ADDERR, INS / DEL, and DL signals), collects successive error-free channel states and error sequences into packets, as well as Distributes in time the registration of synchronization errors and additive errors with the simultaneous appearance of the ADDERR and SYNCERR signals (for this, the CLK3 clock signal is used). D-flip-flop 68 is designed to determine the end of a stream of identical channel states (error-free states, or additive errors). For this, the EXCLUSIVE OR 69 element compares the previous channel status (D-trigger state) and the current (current ADDERR signal value). When this event is detected, the unit code is loaded into the counter 73 by supplying a logical unit to the load input of the counter L (load). Counter 73 is intended for counting intervals of error-free states of a channel, as well as the lengths of additive error packets. Therefore, the dimension of the counter and the bus at the output of the counter 73 (P) is determined by the longest length of the interval of identical states (2 ^p ). The operation of the channel 12 state flow forming unit is explained in the table of FIG. 11, which shows the actions taken by the unit and the output signals depending on the input signals and the current state of the D-trigger 68. The first three columns of the table show all possible combinations of input signals at the input AE, SE (ADDERR and SYNCERR, respectively) and status D-flip-flop (C / L). If C / L = 0, then this means that the counter 73 of the error-free states of the channel is currently being counted, otherwise the equality C / L = 1 means that the additive errors are being counted. C / L '- the state of the D-flip-flop, in which the transition is carried out in the next measure. The last column of the table shows a part of the state flow of the SYNCERR (SE) and ADDERR (AE) signals at the previous time points corresponding to each of the situations under consideration (the current state of the SYNCERR and ADDERR signals is in bold).

 Notes to the table.

Control signals:
C is the clock input of the counter 73,
L - counter boot input 73,
W - write signal WRITE,
ERRTYPEO, ERRTYPE1 - ERRTYPE bus lines.

Actions:
CNT = CNT + 1 - increment counter 73,
Per. S - registration of a synchronization error,
Per. L - registration of the additive error package,
Per. C - registration of an error-free interval.

 In FIG. 12 shows timing diagrams of clock signals of a channel error measuring device. One CLK clock corresponds to the arrival time of one bit of the test sequence in the device. The clock signal CLK2 is necessary for the operation of the unit for finding a significant relative locator 8. The control unit 35 skips one clock cycle of the clock signal CLK2, this is due to the fact that it takes some time for the sync converter to locators 2 to work and, therefore, the output data will not appear at the beginning tact (since it is assumed that the converter of sync symbols to locators will be implemented on ROM). The channel 12 state flow forming unit starts working in parallel with the significant relative locator 8 block from the twentieth cycle. This is possible, since the output data of the latter is ready by the end of the eighteenth measure. This saves two clock cycles (CLK2) of the entire device as a whole. The CLK3 clock signal is necessary for the separation in time of registration of additive errors and synchronization errors. The CLK4 clock signal is designed to generate a recording strobe (WRITE signal) for an error information recording device that should record error information on the leading edge of the WRITE signal.

 In FIG. 13-16 are examples of the operation of the device for measuring error parameters in cases of four different error configurations. As a test, the M-sequence obtained using the linear feedback shift register shown in Fig. 6a (m = 5) is used. Subsequent bits of the M-sequence are located in the figures to the left with respect to the previous bits.

 Conditional abbreviations used in tables (in order).

N is the measure number,
SS - current sync symbol (shift register 1 output),
L - current locator (output of the sync symbol to locator 2 converter),
CNT - current counter value 4,
R is the current value of the relative locator (subtractor 4 output),
CB is the value of the central bit (shift register 5 output),
LL is the essential relative locator for the left window (the output of the block finding the essential relative RLOC locator),
LN is the weight of the significant relative locator for the left window (the output of the block finding the significant relative locator NUM),
RL - essential relative locator for the right window (output buffer essential relative locators 9),
RN is the weight of the significant relative locator for the right window (the output of the block finding the significant relative locator 10),
SC - the current value of the offset counter 49 (shifted counter),
DO - current value at the direct output of the zero code selector 62 (DL = 0),
IJ - the current value at the J-input of the JK trigger 58,
JK - the current value at the direct output of the JK trigger 58,
LC - current counter value 63,
EN - current value at the output of the AND-NOT 67 element (signal for allowing the registration of additive errors),
ae - the presence of an additive error (the output of the sequence comparison circuit 52),
AE - current value at the output of element And 53 (additive error signal),
SE - current value at the output of element 59 (synchronization error signal),
DL - the current value at the output of the multiplexer 61 (size of the synchronization error),
ID is the current value at the output of the code comparison circuit 60 (type of synchronization error),
DC - the current state of the D-trigger (type of interval),
L is the current value at the input of the download counter 73,
IC - current counter value 73 (interval size),
W is the current value of the write signal WRITE at the output of the device,
T - the current value of the type of error (ERRTYPE) at the output of the device (in decimal),
S - current value of the error size (ERRSIZE) at the output of the device.

 Note: WRITE, ERRTYPE and ERRSIZE signals are given for two CLK4 measures (when CLK3 = 1 and when CLK3 = 0).

 In FIG. Figure 13 shows the situation when a packet of additive errors and a single additive error are encountered in a data stream received from a channel. As can be seen from the table, on the 24th clock cycle, the first WRITE signal is issued for the external error information logging device — an empty interval without errors of length 24 is recorded. Next, on the 29th clock, a 5-bit additive error packet (ERRTYPE = 1) is recorded. On the 30th step, an empty interval (ERRTYPE = 0) of 1 bit is recorded, and, finally, on the next step, a 1-bit additive error packet is recorded (ERRTYPE = 1), which fully corresponds to the picture of errors present in the analyzed stream.

 In FIG. Figure 14 shows a situation when a synchronization error of the type of loss of 3 bits occurred in the stream received from the channel. As can be seen from the table, an empty error-free interval of length 39, preceding the loss, is recorded on clock cycle 39, and then a synchronization error, such as loss (ERRTYPE = 2), 3 bits long, is recorded in the same clock cycle.

 Fig. 15 shows a situation when an insertion of 4 bits occurred in a bit stream received from a channel. At measure 29, this synchronization error (ERRTYPE = 3) is recorded, as well as an empty error-free interval (ERRTYPE = 0) of length 29 preceding it.

 Fig. 16 shows a situation where the analyzed bitstream contains a 3-bit loss and several additive errors. In this case, due to additive errors, a situation of ambiguity arises when the synchronization error is localized. And therefore, in addition to the actual loss of 3 bits, registered on the 37th clock cycle (ERRTYPE = 2) and two additive errors, one extra additive error is recorded.

 The proposed device consists of simple in its functional purpose elements and is therefore easily implemented on commercially available microcircuits and radio elements. To reduce the dimensions of the device, it is advisable to implement the device on an FPGA or a specialized LSI.

 The proposed device in comparison with the prototype has the advantage of more accurately determining the location of the inserts and bits in the data stream, as well as a more accurate restoration of the stream of additive errors that accompany synchronization failure. In the proposed device there is no hard limit on the maximum sizes of detected synchronization errors. The device allows you to receive real-time error information, reduced to a compact form and convenient for further processing.

Sources of information
1. US patent 4158193. IPC G 08 C 025/00; H 04 L 017/00. Data transmission test set with synchronization detector. / D'Antonio Renato A. - stated 06.06.77; 803987; publ. 06/12/79.

 2. US patent 5392289. IPC G 06 F 11/00; H 04 L 12/00; H 04 L 7/00; H 03 M 13/00. Error rate measurement using a comparison of received and reconstructed PN sequences. / George R. Varian, Palo Alto, Calif - Declared 10/13/93; 136075; publ. 02.21.95.

 3. US patent 5727018. IPC N 04 B 001/69; H 04 B 003/46. Process for obtaining a signal indicating a synchronization error between a pseudo-random signal sequence from a transmitter and a reference pseudo-random signal sequence from a receiver. / Wolf Andreas, Arweiler Hans-Wemer - Declared 11/28/95 553447; publ. 03/10/98.

 4. US patent 5282211. IPC G 06 F 11/00. Slip detection during bit-error-rate measurement. / Robert M. Manlick, Matthew L. Fitchtenbaum - Declared 10/15/91 776850; publ. 01/25/94.

 5. McEliece R. J. Finite fields for computer scientists and engineers. Borton, Kluwer Academic Publishers, 1987.

 6. Lidl R., Niederreiter G. Finite fields: In 2 volumes, Trans. from English - M .: Mir, 1988.

Claims (1)

 A device for measuring error parameters in the channel, containing the first and second shift registers, a sequence comparison circuit, the input of the first shift register being the input of the device for the analyzed bit sequence, the first output of the first shift register connected to the input of the second shift register, the output of the second shift register with the first the input of the sequence comparison circuit, characterized in that a sync symbol to locator converter, a first subtractor, a first counter, a buffer real locators, the first scheme for comparing codes, a block for finding a significant relative locator, a buffer for significant relative locators, a buffer for weighing significant relative locators, a block for deciding on the presence of errors, a block for generating a channel state stream, and the inputs of the sync converter to the locators are connected to the second outputs of the first register shift, the first inputs of the first subtractor - with the outputs of the sync symbol converter to the locators, the second inputs of the first subtractor - with the outputs of the first count The outputs of the first subtractor are with the inputs of the relative locator buffer, with the first inputs of the first code comparison circuit and with the first inputs of the block of finding the significant relative locator, the outputs of the relative locator buffer are with the second inputs of the first code comparison circuit and with the second inputs of the block of finding the significant relative locator , the output of the first circuit comparing codes with the third input of the block finding the significant relative locator, the first outputs of the block finding the significant relative locator the ator — with the inputs of the buffer of significant relative locators and with the first inputs of the block for deciding on the presence of errors, the second outputs of the block for finding the significant relative locator — with the inputs of the buffer of the weight of significant relative locators and with the second inputs of the block for deciding on errors, the outputs of the buffer of significant relative locators - with the third inputs of the decision-making block on the presence of errors, the outputs of the weight buffer of the relative relative locators - with the fourth inputs of the decision-making block on cash errors, the first output of the decision-making block about errors - with the first input of the channel state flow generation block, the second output of the decision-making block about errors - with the second input of the channel status flow-generating block, the third outputs of the decision block about errors - with the third the inputs of the channel state flow forming unit, the fourth output of the channel decision making unit — with the fourth input of the channel state flow forming unit, the fifth output of the channel decision making unit is the “Measurement failure” output of the device, the first output of the channel state stream generation unit — the recording strobe output of the device, the second outputs of the channel state stream generation block — the device error type outputs, the third outputs of the channel state stream generation unit — the error size outputs "devices, and the unit for finding a significant relative locator contains the first multiplexer, the first - the eleventh bus drivers, the first - the sixth buffer registers, the first selector of the zero code, operational memory the detecting device, the first AND element, the initialization device, the control device, the first inputs of the first multiplexer being the first inputs of the block finding the significant relative locator, the second inputs of the first multiplexer being the second inputs of the block finding the significant relative locator, the enable input of the control device is the third input of the finding block significant relative locator, the control input of the first multiplexer is connected to the first output of the control device, the outputs of the first multiplexer - with data inputs of the first and second bus drivers, the control input of the first bus driver is connected to the second output of the control device, the control input of the second bus driver is connected to the third output of the control device, the outputs of the first bus driver - with the address bus, the outputs of the second bus driver - with a data bus, the first address inputs of random access memory - with an address bus, the second address input of random access memory - from a third by the input of the first element And, with the fourth output of the control device and with the third output of the initialization device, the third address input of random access memory - with the second input of the first element And, with the fifth output of the control device and with the fourth output of the initialization device, read / write control input operational a storage device - with the first input of the first AND element and with the sixth output of the control device, a sample input of random access memory - with the twenty-fourth output of the device control, data outputs of random access memory - with a data bus, inputs of the first zero code selector - with an address bus, output of the first zero code selector - with the fourth input of the first AND element, data inputs of the first buffer register - with the data bus, the first control input of the first the buffer register with the eighth output of the control device, the second control input of the first buffer register with the ninth output of the control device, the outputs of the first buffer register with data inputs of the third and fourth of other drivers, the control input of the third bus driver - with the tenth output of the control device, the outputs of the third bus driver - with the address bus, the control input of the fourth bus driver - with the eleventh output of the control device, the outputs of the fourth bus driver - with the data bus, data inputs of the second buffer register - with a data bus, the first control input of the second buffer register - with the twelfth output of the control device, the second control input of the second buffer register - from trine the fifth output of the control device, the third control input of the second buffer register with the fourteenth output of the control device, the outputs of the second buffer register with the data inputs of the fifth and sixth bus drivers, the control input of the fifth bus driver with the fifteenth output of the control device, the outputs of the fifth bus driver with address bus, control input of the sixth bus driver - with the sixteenth output of the control device, outputs of the sixth bus driver - with the data bus, data inputs the third buffer register with the data bus, the control input of the third buffer register with the seventeenth output of the control device, the outputs of the third buffer register with data inputs of the seventh and eighth bus drivers, the control input of the seventh bus driver with eighteenth output of the control device, the outputs of the seventh bus driver - with the address bus, the control input of the eighth bus driver - with the nineteenth output of the control device, the outputs of the eighth bus driver - with the data bus , data inputs of the fourth buffer register with the data bus, the first control input of the fourth buffer register with the twentieth output of the control device, the second control input of the fourth buffer register with the twenty-first output of the control device, the outputs of the fourth buffer register with the data inputs of the ninth and tenth bus shapers, the control input of the ninth bus driver - with the twenty-second output of the control device, the outputs of the ninth bus driver - with the address bus, the control input de the last bus driver - with the twenty-third output of the control device, the outputs of the tenth bus driver - with the data bus, data inputs of the fifth buffer register - with the data bus, the control input of the fifth buffer register - with the output of the first AND element, the outputs of the fifth buffer register - with data inputs eleventh bus driver and are the first outputs of the block finding a significant relative locator, the outputs of the eleventh bus driver are connected to the address bus, the control input is eleven the bus driver - with the control input of the sixth buffer register and with the seventh output of the control device, the data inputs of the sixth buffer register - with the data bus, the outputs of the sixth buffer register are the second outputs of the significant relative locator locator, the first input of the initialization device and the clock input of the control device are connected with the bus of the second clock signal, the second inputs of the initialization device with the bus code window size, the third input of the initialization device with the initialization bus , the first outputs of the initialization device with the address bus, the second outputs with the data bus, the initialization device containing the second counter, the second - fourth multiplexers, the second zero code selector, the second code comparison circuit, the twelfth - fourteenth bus drivers, and the clock input of the second counter is the first input of the initialization device, the second inputs of the second multiplexer are connected to the first inputs of the second code comparison circuit and are the second inputs of the initialization device, the first inputs to the second multiplexer and the second inputs of the third multiplexer are connected to the zero code bus, the first inputs of the third multiplexer are connected to the unit code bus, the first outputs of the second counter are connected to the inputs of the second zero code selector, to the second inputs of the second code comparison circuit, to the third and fourth inputs of the fourth multiplexer and with the data inputs of the fourteenth bus driver, the second outputs of the second counter with the control inputs of the fourth multiplexer and with the data inputs of the thirteenth bus driver, the course of the second zero code selector is with the control input of the second multiplexer, the output of the second code comparison circuit is with the control input of the third multiplexer, the outputs of the second multiplexer are with the first inputs of the fourth multiplexer, the outputs of the third multiplexer are with the second inputs of the fourth multiplexer, the outputs of the fourth multiplexer are with the inputs data of the twelfth bus driver, the control input of the twelfth bus driver - with the control inputs of the thirteenth and fourteenth bus drivers it is the third input of the initialization device, the outputs of the twelfth bus driver are the second outputs of the initialization device, the outputs of the thirteenth bus driver are the third and fourth outputs of the initialization device, the outputs of the fourteenth bus driver are the first outputs of the initialization device, and the decision block for errors contains the second and third subtractors, first and second adders, third to seventh code comparison schemes, fifth and sixth multiplexers, third and fourth counters, a sync-to-sync converter, a sequence comparison circuit, the second to the fourth AND element, the first inverter, JK trigger, the third zero code selector, the two multiplier, the NAND element, the second inputs of the second subtractor being connected to the first inputs of the third subtractor, with the second inputs of the sixth multiplexer and are the first inputs of the decision-making unit for errors, the first inputs of the fourth code comparison circuit are the second inputs of the sixth code comparison circuit and are the second inputs of the accept block I have decisions about the presence of errors, the first inputs of the second subtractor are with the second inputs of the third subtractor, with the first inputs of the sixth multiplexer and are the third inputs of the decision-making unit for errors, the second inputs of the fourth code comparison circuit are the first inputs of the fifth code comparison circuit and are fourth inputs of the decision-making unit for errors, the output of the fourth code comparison circuit is with the first control input of the fourth counter, with the control input of the sixth multiplexer, with the J-input of the JK trigger and with the third the input of the fourth element And, the outputs of the sixth multiplexer - with the first inputs of the first adder, the outputs of the third counter - with the second inputs of the first adder, the outputs of the first adder - with the converter of locators to sync bits, the output of the converter of locators to sync bits - with the second input of the sequence comparison circuit, circuit output sequence comparison - with the first input of the third AND element, the second inputs of the fifth code comparison circuit and the first inputs of the sixth code comparison circuit - with the threshold code bus, the output of the fifth circuit entering codes - with the first input of the second element And, the output of the sixth circuit comparing codes - with the second input of the second element And, the output of the second element And - with the second input of the third element And, with the input of the first inverter and with the first input of the fourth element And, the output of the third element And it is the fourth output of the decision block on the presence of errors, the output of the first inverter is the fifth output of the decision block on the presence of errors, the outputs of the second subtractor are connected to the first inputs of the fifth multiplexer and to the first inputs of the third circuit entering codes, the outputs of the third subtractor — with the second inputs of the fifth multiplexer and with the second inputs of the third code comparison circuit, the output of the third code comparison circuit — with the control input of the fifth multiplexer, with the second input of the AND gate and is the second output of the decision block for errors , the outputs of the fifth multiplexer - with the inputs of the third selector of the zero code, with the second inputs of the second adder and are the third outputs of the decision block on the presence of errors, the inverse output of the third selector is zero code - with the fourth input of the fourth element AND, direct output of the third selector of the zero code - with the K-input of the JK trigger and with the second control input of the fourth counter, the clock inputs of the JK trigger and the fourth counter are connected to the bus of the first clock signal, inverse output JK- trigger - with the second input of the fourth element And, the output of the fourth element And is the first output of the decision block on the presence of errors, the outputs of the fourth counter are connected to the inputs of the multiplier by two, the outputs of the multiplier by two - with the first inputs of the second the adder, the outputs of the second adder with the first inputs of the seventh code comparison circuit, the second inputs of the seventh code comparison circuit with the window size code bus, the output of the seventh code comparison circuit with the first input of the AND-NOT element, the output of the AND-NOT element with the third input the third element AND, wherein the channel state flow generation unit contains a D-trigger, an EXCLUSIVE OR element, the fifth and sixth elements AND, the first and second OR elements, the second inverter, the fifth counter, the seventh and eighth multiplexer, and the D-input of the D-trigger is connected with the second input ohm of the element EXCLUSIVE OR and is the fourth input of the channel state flow generating unit, the clock input of the D-trigger is connected to the second input of the fifth element And, with the input of the second inverter, with the clock input of the fifth counter and with the bus of the third clock signal, the output of the D-trigger is with the first input of the EXCLUSIVE OR element and with the first input of the seventh multiplexer, the output of the EXCLUSIVE OR element with the first inputs of the fifth element and the second OR element, the output of the fifth element AND with the first input of the first OR element, the second input is the first about the OR element - with the second input of the second OR element and is the first input of the channel state flow forming unit, the output of the first OR element - with the second input of the sixth AND element, the first input of the sixth AND element - with the bus of the fourth clock signal, the output of the sixth AND element is the first the output of the channel state flow forming unit, the output of the second OR element is connected to the load input of the fifth counter, the data inputs of the fifth counter are with the unit code bus, the outputs of the fifth counter are with the first inputs of the eighth multiplex ora, the second input of the seventh multiplexer is the second input of the channel state stream generating unit, the second inputs of the eighth multiplexer are the third inputs of the channel state stream forming unit, the output of the second inverter is connected to the control inputs of the seventh and eighth multiplexers, the outputs of the seventh multiplexer and the second inverter are second outputs of the block channel state stream generation, the eighth multiplexer outputs are the third outputs of the channel state stream forming unit.

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