RU2185686C2 - Method for manufacturing integrated circuits around cmos transistors - Google Patents

Abstract

FIELD: microelectronics. SUBSTANCE: combined process of forming separate and insulating silicon dioxide including thermal cleaning of plate surfaces with trichloroethylene and oxygen, modifying silicon dioxide precipitated from tetraethoxysilane at reduced pressure, followed by thermal annealing in trichloroethylene and oxygen improves and stabilizes electrophysical properties of silicon dioxide. EFFECT: enhanced yield of integrated circuits. 3 dwg

Description

 The scope of the invention is microelectronics, namely the manufacturing technology of ICs, and can be used in the manufacture of BIP, CMOS and BICMOP ICs.

 One of the features of manufacturing CMOS ICs is the formation of high-quality dioxide layers with a minimum density of effective and mobile charges and stability of properties during physical and thermal treatments.

 There is a "Method for the manufacture of semiconductor devices", proposed in Japanese patent 63-217655 H 01 L 27/08, published 9.09.88, [1]. According to this method, regions (pockets) of the second type of conductivity are formed in the substrate of the first type of conductivity, anti-channel regions and LOCOS isolation are created, gate silicon dioxide is formed on the entire plate, a layer of polycrystalline silicon is deposited, and gate regions of n- and p-channel transistors are formed using shutter regions and photoresist regions as a mask form the regions of drains and sources of the first conductivity type in the regions of the second conductivity type, the regions of drains and the sources of the second conductivity type in regions of the first conductivity type. Silicon dioxide is deposited on the entire surface by chemical deposition, and contact holes are formed at predetermined locations of the aluminum wiring. The disadvantages of the method include: the lack of thermal cleaning of the plates before chemical deposition of silicon dioxide and the subsequent modification of pyrolysis silicon dioxide in order to improve and stabilize the electrophysical properties. The closest technical solution is the "Method of manufacturing a semiconductor device" application of Japan 60-38482 B 4 H 01 L 27/092 [2], including the formation in the substrate of the first type of conductivity of the regions of the second type of conductivity, anti-channel regions of the first type of conductivity and the dielectric insulation between transistor structures, the formation of a gate silicon dioxide on the entire substrate, the deposition of a layer of polycrystalline silicon, the formation of the gate regions of p- and n-channel transistors using gates and photocores m as a mask, the formation of areas is performed drains and sources of the second conductivity type in a substrate of first conductivity type and the source and drain region of the first conductivity type in regions of the second conductivity type (pockets). On the entire substrate by the pyrolysis of organosilicon compounds, an insulating layer is formed, anisotropic etching of which separating silicon dioxide is formed on the side walls of the gate regions. The entire surface is covered with a layer of titanium and form titanium silicide on the gate, runoff and source areas. An insulating silicon dioxide is formed on a substrate by pyrolysis of organosilicon compounds. Using a photoresist mask, layers with a high concentration of impurity are formed in regions of the first conductivity type formed in regions of the second conductivity type. Contact windows are formed in the insulating silica and metallized wiring is carried out. The disadvantage of the prototype is the lack of thermal cleaning of the plates before the formation of separation and insulating silicon dioxide on the vertical walls of the gates, the modification of pyrolysis silicon dioxide in order to improve and stabilize the electrophysical properties of silicon dioxide.

 The problem to which this invention is directed, is to achieve a technical result, which consists in improving and stabilizing the electrophysical properties of silicon dioxide, leading to an increase in the percentage of yield of ICs.

The problem is solved in a method for manufacturing integrated circuits on CMOS transistors, including the formation of regions of the second type of conductivity in the substrate of the first type of conductivity, anti-channel regions, dielectric insulation, the formation of gate silicon dioxide, the deposition of a layer of polycrystalline silicon, the formation of gate regions of p- and n-channel transistors, the formation of silicon dioxide on the vertical walls of the gates, the formation of areas of drains and sources of the second type of conductivity in the substrate the first type of conductivity and regions of the source and drain of the first conductivity type in regions of the second conductivity type, prior to forming the separating of silicon dioxide on the vertical walls of the gate and an insulating silicon dioxide by pyrolysis of the organosilicon compounds under reduced pressure to produce thermal cleaning surface plates in trichlorethylene, and oxygen (TCE + O ₂ ), its modification by thermal annealing in trichlorethylene and oxygen, the formation of contact windows in insulating silicon dioxide and the formation of meta lysed wiring.

Thus, the distinguishing feature of the present invention is the combined process of forming insulating silicon dioxide, including thermal cleaning of the surface of the plates in trichlorethylene and oxygen (TCE + O ₂ ) and after deposition of silicon dioxide it is modified by thermal annealing in trichlorethylene and oxygen (TCE + O ₂ ). Patent studies have shown that the combination of features of the invention is new, which proves the novelty of the proposed method. In addition, patent research showed the absence in the literature of data showing the influence of the distinguishing features of the claimed invention on the achievement of a technical result, which confirms the inventive step of the proposed method. This set of distinctive features allows us to solve the problem. The test carried out according to the proposed technical solution showed an increase in the yield of suitable crystals from the wafer by 12%.

The invention is illustrated in figures 1 to 3:
1. silicon substrate KEF-4,5 (100),
2. p-type pocket,
3. dielectric insulation,
4. p-type anti-channel areas,
5. gate silica,
6. polysilicon shutter,
7. combined separation silicon dioxide, including thermal cleaning of the plates in trichlorethylene and oxygen, deposition of silicon dioxide from TEOS and its thermal annealing in trichlorethylene and oxygen,
8. drains and sources of the p-channel transistor,
9. drains and sources of the n-channel transistor,
10. combined insulating silicon dioxide, including thermal cleaning of the plates in trichlorethylene and oxygen, deposition of silicon dioxide from TEOS and its thermal annealing in trichlorethylene and oxygen,
11. aluminum contacts to the drain and source regions of the n-channel transistor,
12. aluminum contacts to the drain and source regions of the p-channel transistor.

при 950^oС. С помощью фотомаски вскрывали окна в фотомаске под р-карман и вводили бор ионным легированием с Е=100 кэВ и Д=2,2 мкКл•см^-2. После химической обработки производили разгонку примесей при 1150^oС в течение 17 ч.Example. On a KEF-4.5 (100) single crystal substrate, 0.165 μm thick silicon dioxide was formed at 920 ^° C. Using a photomask in silicon dioxide, windows were opened under the n-pocket and with ion doping E = 60 keV and D = 0.8 μC • cm ^-2 introduced phosphorus. After chemical treatment, silicon dioxide was formed thick

at 950 ^o C. Using the photomask, the windows in the photomask were opened under the p-pocket and boron was introduced by ion doping with E = 100 keV and D = 2.2 μC • cm ^-2 . After chemical treatment, the impurities were distilled at 1150 ^o C for 17 hours

The resistance of the n-pocket is (800 ± 50) Ohm / sq.,
The resistance of the p-pocket is (2000 ± 150) Ohm / sq.,
χ _jp = (5 ± 0.2) μm, the thickness of silicon oxide over n-pockets is (0.33 ± 0.015) μm, and p-pockets are (0.27 ± 0.015) μm.

в ТХЭ+О₂ и осаждали нитрид кремния из дихлорсилана и аммиака при 785^oС и Р= (15÷20)Па толщиной (0,11÷0,13) мкм. С помощью фоторезиста вскрывали окна в двухслойном диэлектрике Si₃N₄-SiO₂ под локальное окисление и ионным легированием бором с Е=20 кэВ и Д=10мкКл•см^-2 формировали р-охрану. После химической обработки осуществляли локальное окисление под защитой Si₃N₄ при 920^oС, при этом толщина диоксида кремния составляла (0,6÷0,7) мкм, p_sр= (5±1,5) Oм/кв., χ_jp=(1,5±0,3) мкм. Стравливали диэлектрики, SiO₂ в травителе HF: H₂O= 1:10, а Si₃N₄ в ортофосфорной кислоте при (170-180)^oС. Далее формировали предварительный диоксид кремния толщиной

в трихлорэтилене и кислороде. В фоторезистивной маске вскрывали окна и с Е=80 кэВ и Д=20 мкКл•см^-2 вводили фосфор, после химической обработки производили термический отжиг при 1000^oС 30 мин. в N₂. С помощью фотолитографии осуществляли подгонку порогов ионным легированием бора Е=30 кэВ, Д=0,25мкКл•см^-2. После стравливания предварительного оксида кремния и химической обработки формировали затворный диоксид кремния в трихлорэтилене с кислородом толщиной

Осаждали слой поликристаллического кремния из моносилана при 620^oС и 40 Па толщиной 0,5 мкм, легирование поликремния производили РСl₃ при 920^oС, при этом ρ_s поликремния - (17±3) Oм/кв. Методом фотолитографии формировали маску под затворы n- и р-канальных транзисторов. Плазмохимическим травлением в SF₆+O₂ травили поликремний при P=(2-3) Па мощности ВЧ-разряда 100 Вт. После химической обработки производили термическую обработку пластин при 850^oС в трихлорэтилене и кислороде (20÷30) мин. Осаждали диоксид кремния из ТЭОСа при 715^oС и 80 Па толщиной (0,2±0,02) мкм, производили термический отжиг при 900^oС в ТХЭ+O₂ 30 мин. ПХ травлением в СНF₃+СF₄-Аr при P=(60-70) Па и мощности ВЧ-разряда (350÷380) Вт. Формировали разделительный диэлектрик на боковых стенках затворов. После химической обработки в фоторезистивной маске формировали окна под стоковые и истоковые области n-канального транзистора, ионным легированием последовательно вводили фосфор с E=40 кэВ и Д= 15 мкКл•см^-2 и мышьяк с Е=100 кэВ и Д=800 мкКл•см^-2, после химической обработки производили термический отжиг при 550^oС 60 мин. Далее в фоторезистивной маске формировали окна под стоковые и истоковые области р-канальных транзисторов, ионным легированием вводили бор с Е=25 кэВ и Д=500 мкКл•см^-2. После химической обработки производили термическую очистку при 850^oС в ТХЭ+O₂ 30 мин, осаждали диоксид кремния из ТЭОСа при 715^oС и 80 Па толщиной (0,3÷0,4) мкм и производили модификацию осажденного диоксида кремния термическим отжигом в ТХЭ+O₂ при 900^oС 30 мин.After chemical treatment, silicon dioxide was formed.

in TCE + O ₂ and silicon nitride was precipitated from dichlorosilane and ammonia at 785 ^o C and P = (15 ÷ 20) Pa with a thickness of (0.11 ÷ 0.13) μm. Using a photoresist, windows were opened in a bilayer insulator Si ₃ N ₄ -SiO ₂ under local oxidation and ion doped with boron with E = 20 keV and D = 10 μC · cm ^-2 formed p-guard. After chemical treatment, local oxidation was carried out under the protection of Si ₃ N ₄ at 920 ^o C, while the thickness of the silicon dioxide was (0.6 ÷ 0.7) μm, p _sp = (5 ± 1.5) Ohm / sq., Χ _jp = (1.5 ± 0.3) μm. The dielectrics were etched, SiO ₂ in the etchant HF: H ₂ O = 1:10, and Si ₃ N ₄ in orthophosphoric acid at (170-180) ^o С. Then, preliminary silicon dioxide was formed with a thickness

in trichlorethylene and oxygen. Windows were opened in the photoresist mask and phosphorus was introduced with E = 80 keV and D = 20 μC · cm ^-2 , after chemical treatment, thermal annealing was performed at 1000 ^° C for 30 minutes. in N ₂ . Using photolithography, thresholds were adjusted by ion doping of boron E = 30 keV, D = 0.25 μC · cm ^-2 . After etching of the preliminary silicon oxide and chemical treatment, gate silica was formed in trichlorethylene with oxygen thick

A layer of polycrystalline silicon from monosilane was precipitated at 620 ^° C and 40 Pa, 0.5 μm thick, polysilicon was doped with PCl ₃ at 920 ^° C, and ρ _{s of} polysilicon was (17 ± 3) Ohm / sq. Using a photolithography method, a mask was formed for the gates of n- and p-channel transistors. Plasma-chemical etching in SF ₆ + O ₂ etched polysilicon at P = (2-3) Pa RF power of the discharge of 100 watts. After chemical treatment, the plates were thermally treated at 850 ^o С in trichlorethylene and oxygen (20 ÷ 30) min. Silicon dioxide was precipitated from TEOS at 715 ^° С and 80 Pa with a thickness (0.2 ± 0.02) μm, and thermal annealing was performed at 900 ^° С in TCE + O _{2 for} 30 min. HRP etched in CHF ₃ + CF ₄ -Ar at P = (60-70) Pa and RF power (350 ÷ 380) W. An isolation dielectric was formed on the side walls of the gates. After chemical treatment, windows were formed in the photoresist mask under the drain and source regions of the n-channel transistor, phosphorus with E = 40 keV and D = 15 μC • cm ^-2 and arsenic with E = 100 keV and D = 800 μC • were sequentially introduced by ion doping. cm ^-2 , after chemical treatment produced thermal annealing at 550 ^o C for 60 minutes Then, windows were formed in the photoresist mask under the drain and source regions of the p-channel transistors, boron with E = 25 keV and D = 500 μC • cm ^-2 was introduced by ion doping. After chemical treatment, thermal purification was carried out at 850 ^° C in TCE + O ₂ 30 min, silicon dioxide was deposited from TEOS at 715 ^° C and 80 Pa with a thickness of (0.3 ÷ 0.4) μm, and the deposited silicon dioxide was modified by thermal annealing in TCE + O ₂ at 900 ^o C for 30 minutes

The following parameters of the sink and source regions of n- and p-channel transistors were obtained: ρ _{sn +} = (75 ± 25) Ohm / sq., Χ _{jn +} = (1.1 ± 0.1) μm, ρ _{sp +} = (115 ± 35) Ohm / sq., χ _{jp +} = (1.1 ± 0.1) μm.

In the photoresist mask, contact windows and PX were formed by traction in CHF ₃ + CF ₄ -Ar at a pressure of (60-70) Pa and an RF discharge power (350 ÷ 380) W etched with silicon dioxide. After chemical treatment, Al + Si was sprayed with a thickness of 1 μm, and PCBs formed a wiring by etching.

Claims (1)

 A method of manufacturing integrated circuits based on CMOS transistors, including the formation of regions of the second type of conductivity in the substrate of the first type of conductivity, anti-channel regions, dielectric insulation, the formation of gate silicon dioxide, the deposition of a layer of polycrystalline silicon, the formation of the gate regions of n- and p-channel transistors, separation dioxide silicon on the vertical walls of the gates, areas of drains and sources of the second type of conductivity in the substrate of the first type of conductivity, areas of drains, and currents of the first type of conductivity in areas of the second type of conductivity, insulating silicon dioxide by deposition under reduced pressure from organosilicon compounds, opening contact windows and metallization, characterized in that before the formation of the separation of silicon dioxide on the vertical walls of the gates and insulating silicon dioxide by pyrolysis of organosilicon compounds under reduced pressure perform thermal cleaning of the surface of the plates in trichlorethylene and oxygen, and after deposition of silicon dioxide it is modified by thermal annealing in trichlorethylene and oxygen, contact windows are formed in insulating silicon dioxide and a metallized wiring is formed.

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