RU2184427C2 - Edge sharpening circuit - Google Patents

Abstract

FIELD: digital displays; video signal generation. SUBSTANCE: circuit that enables displaying contoured image without tonal distortions of white and black and preventing distortions due to edge sharpening process has facilities that function to process brightness component of digital chrome signals for separating edge component and adding it to output signal. EFFECT: enlarged functional capabilities. 7 cl, 26 dwg

Description

 The invention relates to a contour emphasizing circuit in which a digital video signal with underlined contours is generated from an inputted analog color signal and which can be used in a digital display device (e.g., a matrix type display device), such as a plasma display (hereinafter referred to as abbreviated PD) and a liquid crystal display (hereinafter referred to as the abbreviated LCD), for displaying color video signals with underlined contours.

 In a conventional cathode ray tube (CRT) display device, visual highlighting (underlining) of the image contours is used to obtain high-quality images and provide high-frequency correction. The underline outline shown in FIG. 1, consists of a Y / C extraction circuit 10, a color demodulation circuit 12, a loop allocation circuit, a phase adjustment circuit 16, 18, and 20, an adder 22 and a matrix circuit 24.

 The Y / C extraction circuit 10 extracts a luminance signal (Y) and a color signal (C) from a complete video signal (for example, a full color television signal) received at input 26, a color demodulation circuit 12 extracts a signal Y from a signal Y and C, a color difference signal RY and color difference signal BY.

 The loop extraction circuit 14 extracts a loop component Ye, which is a high frequency component of the video signal, based on the adder 22.

 The matrix circuit 24 prepares the signal by adding the component Ye of the loops, respectively, to the signals R (red), G (green) and B (blue), based on the signals (Y + Ye) summed in the adder 22, while in the circuits 18 and 20 phase adjustments, the phase of the signals (RY) and (BY) are adjusted. The matrix circuit 24 generates signals R + Ye, G + Ye and B + Ye in accordance with the equations below (1), (2) and (3). As a result of the supply of R + Ye, G + Ye and B + Ye signals from the outputs 28r, 28g and 28b to the CRT display device, this device shows contoured images.

(RY) + (Y + Ye) = R + Ye ... (1),
(GY) + (Y + Ye) = G + Ye ... (2),
(BY) + (Y + Ye) = B + Ye ... (3),
wherein (GY) in equation (2) is obtained from equation (4) below.

 If the image with underlined contours is displayed on a matrix-type display device operating on digital video signals (for example, R, G, B signals), such as PD and LCD, then each signal (R + Ye), (G + Ye), (B + Ye) obtained at outputs 28r, 28g and 28b shown in FIG. 1, enters the display device after it is converted to digital form in an analog-to-digital conversion (ADC) circuit. However, in this known solution, if a signal with a large amplitude is input to input 26 or in the case of a "large" amount of underlining of the contours (or the coefficient of underlining of the contours, the definition of which is not given, since this is ultimately the same), then it is impossible to ensure correct operation in the dynamic range of the ADC circuit.

 For example, if a signal with a large amplitude is input to input 26, then when a signal is output from the outputs 28r, 28g, 28b in the dynamic range of the ADC circuit, as shown in the left part of Fig. 2 (a), signals exceeding the upper value of the conversion reference voltage are cut off VRT (for example, 5 volts) for a given dynamic range, as shown in the right part of Fig. 2 (a), which leads to gradation distortion of white, or signals with a VRT conversion reference voltage lower than the minimum (for example, 3 volts) for this dynamic range zone, which leads to gradation distortion of black.

 In the case of a "large" amount of underlining of the loops, in the loop isolating circuit 14, signals are cut off above the dynamic range of the ADC circuit, as shown on the left side of FIG. 2 (b), which causes gradation distortion of white, or signals are cut off below the lower value of the VRB conversion reference voltage, which causes gradation distortion of black.

 In FIG. Figure 3 shows the outline underlining scheme proposed in a separate application by the same applicant, which can be used to solve the above problems.

 The underline outline shown in FIG. 3, contains ADC circuits 30r, 30g and 30b, a signal processing / phase adjustment circuit 32, loop adders 34r, 34g and 34b, a Y signal generating circuit, a loop extraction circuit 38, a loop component gain control 40, and a coefficient multiplier circuit 42.

 Thus, the analog signals R, G, B received at the inputs 44r, 44g and 44b are converted to digital signals in the ADC circuits 30r, 30g, 30b, they are processed and the phase is adjusted in the signal processing / phase adjustment circuit 32, and fed to the adders 34r, 34g and 34b loops. The Y signal generating circuit 36 generates Y signals from the digital signals R, G, B, the loop extraction circuit 38 extracts the loop components from the Y signals, then these loop components are supplied to the loop adders 34r, 34g and 34b through the gain controller 40 and a multiplication circuit 42 by coefficient, are added to the original signals R, G, B and fed to the display device through outputs 86r, 86g and 86b.

 As noted above, due to the fact that the components of the loops are added after converting the analog signals to digital signals R, G, B in the ADC circuits 30r, 30g and 30b, the underlining component of the loops does not go beyond the dynamic range of the ADC circuit, as is the case in well-known solution. Therefore, even if the inputs 44r, 44g and 44b shown in FIG. 3, large color analog color signals, or the amount of underline emphasis, are received “large” when displaying digital signals R, G, B coming from the underline circuit shown in FIG. 3, in the digital display device, gradation distortion of white and black does not occur in the contoured image.

 However, since in the underline outline shown in FIG. 3, the loop extraction circuit 38 extracts a component of the vertical loops from signals delayed by a certain number of lines (e.g., 1 or 2 lines), a signal Y generated by the signal generating circuit 36 of this signal and this signal, and the horizontal loop component is extracted from the signals delayed by a certain number of raster points (for example, 2 or 4 raster points), a signal Y delayed by a certain number of lines (for example, 1 line) and this signal, then, as shown in FIG. 4 (a) and (b), there is a distortion at the periphery of the image screen 11 due to this processing (for example, a white edge). FIG. 4 (a) shows a case where an image with a 4: 3 aspect ratio is shown on a screen of a conventional television receiver with a 4: 3 aspect ratio, and FIG. 4 (b) shows a case where a 4: 3 image is shown on a widescreen television with a 16: 9 aspect ratio, with the number 13 indicating a side color (for example, black) without a video image.

 The periphery 11 of the image screen in FIG. 4 (a) corresponds to the blanking part of the image and the boundary part of the actual video signal, the upper and lower parts of the periphery 11 in FIG. 4 (b) correspond to the blanking part of the image and the boundary part of the actual video signal, and the right and left parts of the periphery 11 correspond to the side color 13 and the boundary part of the actual video signal, and since the processing for underlining the contours is performed between lines or between raster points without correlation in these boundary parts the actual video signal, then due to interference between the significant signal and the insignificant signal, distortion occurs due to processing performed to emphasize the contours.

 For example, as shown in FIG. 5 (a), since in the boundary part of the actual video signal described above, the signal VW of the vertical image region and the component of the vertical contours obtained from the signals Y and corresponding to the signals VW1 (images of the same phase) and VW2 delaying the signal VM of the vertical image region and this signal VM vertical area of the image on 1 line and 2 lines, then the large components of the contours are highlighted at the upper edge (1 line) 11u and at the lower edge (1 line) 11d of the image screen, and processing aimed at underlining the contour s becomes excessive, which leads to deterioration of image quality. In addition, as shown in FIG. 5 (b), since the components of the horizontal contours are extracted from the signals Y corresponding to the signal HW1 (image of the same phase) and HW2, the delayed signal HW of the horizontal image region and the signal HW1 of the horizontal image region by 1 line and 2 lines, the large components of the contours stand out on the left edge (2 points) 11l and on the right edge (2 points) 11r of the image screen, which makes redundant processing of underlining outlines and degrades image quality.

 The present invention is aimed at solving the above problems in the case of signals with a large amplitude or with a "large" amount of underlining by implementing an underlining circuit that allows you to get a contoured image without gradation distortion of white or black in a digital display device, as well as prevent distortion, due to underlining processing in the part of the image corresponding to the boundary part of the actual video signal.

 The proposed circuit for emphasizing the image paths is characterized in that it contains an analog-to-digital conversion (ADC) circuit designed to convert analog color video signals (for example, R, G, B signals) to digital color video signals, a signal generation circuit Y from the output signal of the ADC circuit, a circuit allocation circuitry for isolating a circuit component from a signal Y generated in a signal generating circuit Y, and a circuit combiner for receiving a signal with an underlined circuit by adding the component of the circuits, selected circuit allocation circuitry, with the output signal of the ADC circuit, while also providing a scheme for resolving underlining circuits, designed to control the period during which the circuit component highlighted circuit allocation circuit is fed to the circuit adder.

 Since the Y signal is formed after the analogue color video signals are converted into digital signals by the ADC circuit, and the loop component extracted from the Y signal is added to the digital color video signal obtained from the ADC circuit, the underline loop component does not go beyond the dynamic range of the ADC circuit, as in the case shown in FIG. 1. For this reason, even if analog color video signals with a large amplitude and even a "large" amount of underlining are supplied to the input of the proposed underline circuit, the signal received by the digital display device from the output of the proposed underline circuit will produce a contoured image without gradation white or black distortion.

 Also, since the contour emphasis resolution scheme controls the period during which the contour component extracted by the contour allocation circuit is supplied to the contour adder, and does not add the contour component so as not to introduce distortion caused by the contour emphasis processing into a part of the image, this prevents distortion caused by processing at the periphery 11 of the image screen shown in FIG. 4 (a) and (b).

 In addition, to simplify the configuration of the underline resolution resolution circuit, the simple outline underline resolution circuit consists of a resolution signal generation circuit that generates an underline resolution resolution signal based on the image area signal, and a path adding control circuit that determines whether or not to supply the path component to the loop adder, based on the presence of the loop underlining enable signal generated by the enable signal generating circuit.

 Also, to provide functions for determining whether to control underline underlining, an output control circuit is provided that determines whether or not to provide a resolution signal generated by a circuit for generating an enable signal with a control signal indicating whether underline underlining should be performed.

 In order to prevent distortions caused by the underline processing in the vertical and horizontal directions at the boundary of the actual video signal, the resolution signal generation circuit includes a vertical resolution signal generation circuit that generates a vertical underline resolution signal, a horizontal resolution signal generation circuit, which generates enable signals, and an OR circuit that generates an OR signal from the enable signal I emphasize contours in the vertical direction and in horizontal direction as contour emphasizing enable signal.

 To obtain a screen with underlined contours without much distortion caused by the underlining processing, the contour allocation circuit contains the first and second memory, a vertical contour allocation circuit, an underline frequency setting circuit, a vertical resolution signal generation circuit, consists of a delay circuit for a vertical direction generating signals VW1 and VW2, delaying the signal VW of the vertical region of the image sequentially by 1 line, and circuits AND for the vertical direction, cut pulling signals And from signals VW, VW1 and VW2 of the vertical image region, as underline resolution signals in the vertical direction, and the horizontal resolution signal generating circuit consists of a delay circuit for the horizontal direction generating signals HW2 and HW4, which delay the signals HW of the horizontal image region sequentially at 2 raster points, and the AND circuit for the horizontal direction generating the AND signals from the signals HW, HW2 and HW4 of the horizontal image region as a signal in resolution in the horizontal direction underscore circuits.

 To eliminate the influence of noise, a ring core block is provided in the loop allocation circuitry to suppress the loop component below a certain level.

 In addition, to increase the amount of underlining the contours, a gain controller is provided that regulates the size of the component of the circuits supplied from the circuit for selecting the contours through the resolution scheme for underlining the contours, and a multiplication circuit by a coefficient that outputs signals from the output of the gain control of the circuit component multiplied by the coefficients , Kg and Kb, which are less than 1.

на фиг. 8, (b) - форма сигнала

на фиг. 8, (b) - форма сигнала

на фиг. 8, (d) - форма сигнала

на фиг. 8 и (e) - форма сигнала составляющей в горизонтальном направлении на выходе 86r на фиг. 6;
фиг. 12 показывает формы сигналов, относящихся к подчеркиванию контуров в вертикальном направлении, где (а) - форма сигнала

по фиг. 8, (b) - форма сигнала

по фиг. 8, (с) - форма сигнала

по фиг. 8, (d) - форма сигнала

по фиг. 8 и (e) форма сигнала составляющей в вертикальном направлении на выходе 86r на фиг. 3;
фиг. 13 поясняет соотношение между экраном изображения и сигналом разрешения подчеркивания контуров, сформированным в схеме формирования сигнала разрешения, изображенной на фиг. 6, где (а) показывает соотношение между верхним краем 11u и нижним краем 11d экрана изображения и сигнал VE разрешения подчеркивания контуров в вертикальном направлении, а (b) соотношение между левым краем 11l и правым краем 11r экрана изображения и сигнал НЕ разрешения подчеркивания контуров в горизонтальном направлении;
фиг. 14 иллюстрирует другой вариант схемы формирования сигнала разрешения, изображенной на фиг. 6.FIG. 1 depicts a functional diagram of a known outline underline circuit;
FIG. 2 illustrates problems encountered when signals received in the circuit of FIG. 1 are converted to digital signals in an ADC and output to a digital display device, wherein in FIG. (a) the occurrence of gradation distortions of white and black when inputting large amplitude signals is shown, and in FIG. (b) shows the occurrence of gradation distortions of white and black with a "large" amount of underline contours;
FIG. 3 depicts a functional diagram of an exemplary embodiment of an underline circuit claimed in a separate co-pending application of the same applicant;
FIG. 4 depicts an exemplary embodiment of distortion caused by the underline processing generated by the circuit of FIG. 3, where in FIG. 4 (a) shows a case of displaying a 4: 3 format image on a conventional television receiver with a 4: 3 aspect ratio, and FIG. 4 (b) shows a case of showing a 4: 3 format image on a widescreen television receiver with a 16: 9 aspect ratio;
FIG. 5 explains in detail FIG. 4 (a), where (a) shows the processing-induced distortion in the vertical direction, and (b) shows the processing-induced distortion in the horizontal direction;
FIG. 6 is a functional block diagram of an exemplary embodiment of an underline contour "according to the present invention;
FIG. 7 is a functional diagram of an exemplary embodiment of a signal conditioning circuit Y shown in FIG. 6;
FIG. 8 is a functional diagram of an exemplary embodiment of a circuit for isolating in FIG. 6;
FIG. 9 illustrates the characteristics of the ring core block shown in FIG. 8;
FIG. 10 is a functional diagram illustrating an exemplary embodiment of a resolution signal generating circuit of FIG. 6;
FIG. 11 shows waveforms related to underlining loops in the horizontal direction, where (a) is the waveform

in FIG. 8, (b) - waveform

in FIG. 8, (b) - waveform

in FIG. 8, (d) - waveform

in FIG. 8 and (e) is the horizontal waveform of the component at the output 86r in FIG. 6;
FIG. 12 shows waveforms related to underline contours in the vertical direction, where (a) is the waveform

in FIG. 8, (b) - waveform

in FIG. 8, (c) - waveform

in FIG. 8, (d) - waveform

in FIG. 8 and (e) the waveform of the vertical component at the output 86r in FIG. 3;
FIG. 13 illustrates the relationship between the image screen and the underline resolution resolution signal generated in the resolution signal generation circuit shown in FIG. 6, where (a) shows the relationship between the upper edge 11u and the lower edge 11d of the image screen and the vertical underline resolution signal VE, and (b) the ratio between the left edge 11l and the right edge 11r of the image screen and the underline resolution signal NOT horizontal direction;
FIG. 14 illustrates another embodiment of a resolution signal generating circuit of FIG. 6.

 The following is a detailed description of the invention with reference to the accompanying drawings.

 In FIG. 6 shows an exemplary embodiment of the invention in which the same notation is used as in FIG. 3, for identical elements. In FIG. 6 the following notation is used: 30r, 30g and 30b are ADC circuits, 32 is a signal processing / phase adjustment circuit, 34r, 34g and 34b are circuit loops, 36 is a signal generation circuit Y, 38 is a circuit for isolating circuits, 39 is a circuit for resolving underlining circuits , 40 - gain control component of the loops and 42 - multiplication by a coefficient.

 In the ADC circuits 30r, 30g and 30b, respectively, the analog signals R, G, B received at the inputs 44r, 44g and 44b are converted, respectively, into digital signals R, G, B with 8-bit resolution.

 The signal processing / phase adjustment circuit 32 performs signal processing, such as converting the number of image elements, gamma correction, and the like, on the R, G, B signals from the ADC circuits 30r, 30g, 30b, and also adjusts the phases for correcting the difference delays. By converting the number of image elements is meant the operation of converting the frequency of the number of samples of 8-bit digital signals R, G, B, to bring it into line with the number of image elements in the display device, and gamma correction means processing aimed at correcting the light characteristic of the display device . To adjust the phase, a delay element by 1 raster point is used, for example, a delay trigger (D-FF), and phase adjustment means processing aimed at adjusting the delay difference between the delay necessary for signal processing, such as converting the number of picture elements, gamma correction, etc., and the delay necessary for processing the signal in the Y signal generating circuit 36, the loop allocation circuit 38, the gain control 40 and the coefficient multiplier circuit 42.

 The Y signal generating circuit 36 generates Y (luminance) signals from the digital signals R, G, and B generated by the ADC circuits 30r, 30g, and 30b. The Y signal generation circuit 36, using, for example, read-only memory (ROM) as a function of the conversion table, is implemented by the method of obtaining the Y signal by adding the R, G, B signals at a mixing coefficient set by NTSC (National Television System Committee) to satisfy Equation (5) below, or by the method of obtaining an approximate value of a signal Y satisfying Equation (6) below by adding a bit offset, as shown in FIG. 7.

Y = (0.3 • R) + (0.59 • G) + (0.11 • V) ... (5)
Y = 0.3125 • R + 0.5625 • G + 0.1250 • B ... (6)
In the circuit 38 for isolating the circuits from the signals Y generated in the circuit 36 for generating the signal Y, a circuit component is extracted. In more detail, a circuit 38 is shown in FIG. 8. In FIG. 8 the following notation is used: 46 - input for signal Y; 48 and 50 - the first and second memory lines, implemented as delay elements per 1 line, 52 - a scheme for highlighting vertical contours, 54 - a scheme for setting the frequency of underline contours, 56 - a scheme for allocating horizontal contours, 58 - gain control component of the vertical contours, 60 - gain control component of the horizontal circuits, 62 - circuit synthesis circuit, 64 - ring core block and 66 - gain control.

 The first and second memories of 48 and 50 lines are formed from the signal Y received at input 46, signals Y, sequentially delayed by 1 line (1 scan line).

 The vertical contouring circuitry 52 includes an adder 68 in which the signal Y received at input 46 and the signal Y delayed by 2 lines from the second line memory 50 are added, a multiplier 70, in which the output signal of the adder 68 is multiplied by a factor (1 / 4), a multiplier 72, in which the signal Y, delayed by 1 line, from the first memory of the lines 48 is multiplied by a factor (1/2), and a subtractor 74, in which the output of the multiplier 70 is subtracted from the output of the multiplier 72.

 The underline frequency setting circuit 54 sets the underline frequency to a specific frequency (e.g. 1/2 of the sampling frequency Fs), and specifically, as shown in FIG. 5, has 5 taps, consisting of four delay elements D1-D4 per 1 raster point, which sequentially delay the Y signals from the output of the first 48-line memory to 1 raster point (a part of 1 image element). Each of these delay elements D1-D4 at 1 raster point is, for example, a delay trigger (D-FF). However, the circuit 54 for setting the frequency of underlining the contours is not limited to 5 taps and may also contain 7 taps, consisting respectively of six series-connected delay elements D1-D6 per 1 raster point.

 The horizontal loop extraction circuit 56 contains an adder 76 that adds the Y signal from the output of the first memory 48 with the Y signal delayed by 4 raster points from the fourth delay element D4 by 1 raster point, a multiplier for multiplying the output signal of the adder 76 by a factor (1/4 ), a multiplier 80 for multiplying the signal Y, delayed by 2 points, from the second delay element D2 by 1 raster point by a factor (1/2), and a subtractor 82 to subtract the output of the multiplier 78 from the output of the multiplier 80.

 The gain controller 58 multiplies the vertical loop component extracted by the vertical loop extraction circuit 52 by a variable coefficient Kv.

 The gain controller 60 multiplies the horizontal loop component extracted by the horizontal loop extraction circuit 56 by a variable coefficient Kh.

 Circuit synthesis circuit 62 synthesizes circuit components from gain amplifiers 58 and 60.

 The ring core unit 64 eliminates noise and minor circuit components from the component circuits obtained from the circuit synthesis circuit 62, and suppresses those circuit components that are below a certain level in these introduced components. The ring core unit 64 may be implemented, for example, with the I / O characteristics shown in FIG. 9. In particular, if the component of the loops received from the circuit synthesis circuit 62 is positive and greater than 0, then -δ (δ is a positive constant) is added to the original component, if it is negative and less than 0, then + δ is added to the original component if the result of the operation is greater than -δ and less than + δ, the output is set to 0.

 The gain controller 66 multiplies the loop component obtained from the output of the ring core block 64 by a variable short-circuit coefficient. and issued to the output terminal 88.

 The underline underline resolution circuit 39 is composed of an enable signal generation circuit and a contour adding control circuit 43.

 The resolution signal generating circuit 41 generates an underline enhancement resolution signal EE based on the input vertical image region signal VW and the horizontal image region signal HW.

 The resolution signal generating circuit 41, shown in detail in FIG. 10, consists of a delay circuit 45 for the vertical direction and circuitry And 47, a delay circuit 49 for the horizontal direction and circuitry And 51 and circuitry And 53.

 The delay circuit 45 for the vertical direction is not limited to the presented embodiment, however, to match the delay values of the first and second memory 48 and 50 lines in the circuit 38, it contains 1H shift circuits 57 and 59 for generating signals VW1 and VW2 that delay the signals VW the vertical region of the image received at input 55, sequentially on 1 line, and the circuit And 47 for the vertical direction, which produces signals VE vertical resolution, which are signals And obtained from signals VW, VW1 and VW2 vertical image area.

 The delay circuit for the horizontal direction is not limited to the presented option, however, to match the delay value of the circuit underscore frequency setting circuit 54 as part of the circuit 39, it contains four D-FF delay triggers for generating signals HW2 and HW4 that delay the horizontal signals HW areas of the image received at input 61, sequentially at 2 raster points, and an AND circuit for the horizontal direction, which produces NOT horizontal resolution signals like AND signals received from the signals of the horizontal image region HW, HW2 and HW4.

 The AND 53 circuit produces the underline resolution signals EE, which are AND signals obtained from the vertical resolution signal VE and the NOT horizontal resolution signal.

 The loop adding control circuit 43 is connected between the loop allocation circuit 38 and the gain controller 40, and based on the presence of the underline underlining resolution signal EE taken from the enable signal generating circuit 41, it controls by turning on and off the supply of the loop component highlighted by the loop allocation circuit 38 , into the gain control 40, or by locking it.

 The gain controller 40 multiplies the components of the circuits taken from the circuit 38, by a variable coefficient K2.

 If necessary, one of the gain controls 66 and 40 can be turned off (for example, 66).

 The coefficient multiplier circuit 42 consists of multipliers 84Rr, 84g, and 84b, which produce the circuit components Yer, Yeg, and Yeb for R, G, B by multiplying the component of the circuit Ye obtained from the gain controller 40 by the coefficients Kr, Kg, and Kb. These coefficients, although not limited to the given values, are set to the same values of 0.3125, 0.5625 and 0.1250 (Kr + Kg + Kb = l) as the coefficient values for R, G, B (Fig. 7 ), which are used in generating the Y signal in the Y signal generating circuit 36, and are obtained by adding a bit shift.

 The loop adders 34r, 34g, and 34b add the loop components Yer, Yeg, Yeb obtained from the multipliers 84r, 84g, and 84b in the coefficient multiplier circuit 42 to the signals R, G, B subjected to phase processing and phase adjustment in the signal processing circuit 32 / phase adjustment, and output them to the display device through the outputs 86r, 86g and 86b.

 For a better understanding of the principle of operation of the device, we explain the essence of the work, which consists in the following.

 (1) As shown in FIG. 6, the analog signals R, G, and B received at the inputs 44r, 44g, and 44b are converted to 8-bit digital signals R, G, B in the ADC circuits 30r, 30g, and 30b, and they undergo phase processing and adjustment in the signal processing circuit 32 / phase adjustment, and fed to the input of one side of the adders 34r, 34g and 34b circuits.

 (2) The Y signal generating circuit 36 generates Y signals from the digital signals R, G, B received from the ADC circuits 30r, 30g and 30b. For example, Y signal conditioning circuit 36 generates Y signals from digital signals R, G, B by adding a bit offset using the circuit shown in FIG. 7.

 (3) The loop extraction circuit 38 extracts the loop component from the Y signals generated by the Y signal generating circuit 36. The loop component extraction function performed by the loop extraction circuit 38 is explained below with reference to FIG. 8.

 (3a) The function of extracting a component of the horizontal circuits, which is the high-frequency component of the signal Y in the horizontal direction, is explained with reference to FIG. eleven.

 The vertical dashed lines SI, S2, S3, S4, and S5 in FIG. 11 show sample points of each image element sequentially in the horizontal direction along scan lines including image elements of the processed object.

 When the signal Y obtained from the second delay element D2 by 1 raster point in the circuit underlining frequency setting circuit 54 has the form shown in FIG. 11 (a), then at the output of the multiplier 80 of the horizontal loop extraction circuit 56, the signal shown in FIG. 11 (b) is obtained, which is supplied to the plus side of the subtractor 82.

, показанного на фиг. 11(d).The signal Y from the first memory of 48 lines and the signal Y from the output of the fourth delay element D4 to 1 raster point in the circuit for setting the underline voltage are added to the adder 76 of the horizontal circuit extraction circuit 56, multiplied by 1/4 in the multiplier 78, and the signal is supplied to the side the minus of the subtractor 82 in the form of the signal shown in Fig. 11 (c). Y signals processed by the subtractor 82 are multiplied by Kh in the gain controller 60 and fed to the input of one side of the circuit synthesis circuit 62 as a signal

shown in FIG. 11 (d).

 (3b) Next, with reference to FIG. 12 describes the functions of extracting a component of the vertical circuits, which is the high-frequency component of the signal Y in the vertical direction.

 The vertical dashed lines S1, S2, S3 in FIG. 12 mean image elements on three scan lines: a scan line including a processing object and scan lines in front and behind it, and show sample points of three image elements in a vertical direction, including an image element in a processed object.

 When a signal Y delayed by 1 line from the first 48 line memory has the form shown in FIG. 12 (a), the signal from the multiplier 72 of the vertical contour extraction circuit 52 has the shape shown in FIG. 12 (b), and is fed to the plus side of the subtractor 74.

Y сигналы после обработки в вычитателе 74 умножаются на Kv в регуляторе 58 усиления и подаются на другой вход схемы 62 синтеза контуров в виде сигнала

показанного на фиг. 12(d).The signal Y received at input 46 is summed with the signal Y, delayed by 2 lines, taken from the second memory of 50 lines, in the adder 68 as part of the circuit 52 for selecting the vertical contours, multiplied by 1/4 in the multiplier 70 and in the form shown in Fig. 12 (c), fed to the minus side of the subtractor 74 in the form of a signal

Y signals after processing in the subtractor 74 are multiplied by Kv in the gain controller 58 and supplied to the other input of the circuit synthesis circuit 62 as a signal

shown in FIG. 12 (d).

представляющий составляющую горизонтальных контуров, и сигнал

представляющий составляющую вертикальных контуров, синтезируются в схеме 62 синтеза контуров, в блоке 64 кольцевого сердечника подавляются те составляющие контуров, уровень которых ниже некоторого определенного уровня, и исключаются влияния шумов, в регуляторе 66 усиления сигнал подвергается регулировке уровня посредством умножения на коэффициент К1 и выдается на выходную клемму 88.(3s) Signal

representing the component of the horizontal contours, and the signal

representing the component of the vertical circuits, are synthesized in the circuit synthesis circuit 62, in the ring core block 64, those circuit components whose level is below a certain level are suppressed and noise effects are eliminated, in the gain controller 66 the signal is adjusted by multiplying by the coefficient K1 and outputted to output terminal 88.

 (4) Circuit components from the output terminal 88 of the circuit allocation circuit 39 after controlling the period for adding underline resolution in the circuit 39, adjusting the level by multiplying by a factor in the gain controller 40, multiplying by the coefficients Kr, Kg and Kb in the multipliers 84r, 84g and 84b coefficient multiplier circuits 42 become components of the circuits Yer, Yeg, Yeb for R, G, B, and are input to the other side of the respective circuit adders 34r, 34g, 34b. This allows you to increase the number of underline contours.

 (5) Hereinafter, the functions for controlling the period of adding the component of the loops to the loop underline resolving circuit 39 according to claim 4 are described with reference to FIG. 10 and 13.

 (5a) First, vertical underline emphasis resolution functions are explained.

 In the resolution signal generating circuit 41 shown in FIG. 10, the vertical delay circuit 45 generates vertical image region signals VW1 and VW2 that delay the vertical image region signal VW at the input 55 by 1 line and 2 lines due to the delay functions of the 1H shift circuits 57 and 59.

 Scheme And 47 for the vertical direction, as shown also in FIG. 13 (a), produces an AND signal from signals VW, VW1 and VW2 as a vertical underline enable signal.

 (5b) The functions for resolving underline contours in the horizontal direction are now explained.

 In the resolution signal generating circuit 41 shown in FIG. 10, the delay circuit 49 for the horizontal direction outputs signals HW2 and HW4 of the horizontal image region, which delay the signal HW of the horizontal region of the image received at input 61 by 2 points and 4 points of the raster.

 Scheme And 51 for the horizontal direction, as shown also in FIG. 13 (b), produces an AND signal from the horizontal image region signals HW, HW2 and HW4 as a signal for NOT allowing underline contours in the horizontal direction.

 (5c) Scheme AND 53 shown in FIG. 10, generates AND signals from the enable signals VE and NOT in the vertical and horizontal direction as the loop underline enable signals EE, which are supplied to the loop adding control circuit 43 through the output 63.

 (5d) The loop addition control circuit shown in FIG. 6, controls whether or not the loop components selected by the loop isolation circuit 38 will be output to the gain controller 40 based on the presence (level H or level L) of the loop underline enable signal EE at the output 63 of the enable signal generation circuit 41.

 For this reason, since for the vertical direction, the component of the loops is output to the gain controller 40 only for the period of the level H of the vertical loop underline enable signal (Fig. 13 (a)) and is not output during the level L period, in parts 11u and 11b, shown by oblique hatching, there is no distortion due to processing aimed at underlining the contours.

 In addition, since for the horizontal direction, the component of the loops is output to the gain controller 40 only for the period of the level H of the signal NOT to allow underlining of the loops in the horizontal direction (Fig. 13 (b) and is not output during the period of the L level, in parts 11l and 11r shown inclined hatching, there is no distortion due to processing aimed at emphasizing the contours.

 (6) Signals R, G, B, subjected to phase processing and adjustment in the signal processing / phase adjustment circuit 32, and components Yer, Yeg, Yeb of the circuits for R, G, B, taken from the multipliers 84r, 84g, 84b as part of the circuit 42 multiplications by a coefficient are added to the adders 34r, 34g, 34b and output to the display device through the outputs 86r, 86g, 86b to display the outlined image.

 (7) In this case, the component of the signals (R + Yeg) in the horizontal direction at the output 86r has the form shown in FIG. 11 (e), and the component in the vertical direction has the form shown in FIG. 12 (e). Rh and Rv shown by dashed lines in FIG. 11 (e) and 12 (e) represent a component in the horizontal direction and a component in the vertical direction of the signal R at the output of the signal processing / phase adjustment circuit 32.

 Similarly, the component in the horizontal direction and the component in the vertical direction of the signals (G + Yeg) and (B + Yeb) at the outputs 86g and 86b are similar to the component in the horizontal direction and the component in the vertical direction of the signals (R + Yer) at the output 86r.

 (8) As noted above, since the signal Y is formed after the conversion of analog signals R, G, B into digital signals R, G, B in the ADC circuits 30r, 30g and 30b, and the circuit component extracted from this signal Y is added to the initial signals R, G, B, the components of underlining the circuits do not go beyond the dynamic range of the ADC circuit, as is the case with the known solution shown in FIG. 1. For this reason, even if the analog signals R, G, B at the inputs 44r, 44g and 44b of the proposed underline circuitry are signals with a large amplitude, or even with a "large" amount of underline circuitry, when applying signals from the underline circuitry according to invention in a display device that runs on digital signals R, G, B, in the image does not occur gradational distortion of white and black.

 (9) In addition, due to the presence of the contour underline resolution circuit 39 for controlling the period during which the contour components extracted by the contour extraction circuit 38 are supplied to the contour adders 34r, 34g, 34b, in order to control the period of adding the component contours, it is possible not to add components of the contours to that part of the image in which the outline underline resolution circuit 39 creates distortion due to the underline processing, thereby preventing distortion caused by underlining the outlines at the periphery 11 (or 11u, l1d. 11l, 11r) of the image screen of FIG. 4 (a) and (b) (or FIG. 13 (a) and (b)).

 In this embodiment, the underline enhancement resolution circuitry consists of an enable signal generation circuit and a circuit addition control circuit, however, this is not a limiting feature of the invention, and it may be advisable that the circuitry component selected by the circuitry circuitry control the feeding period to the circuit adder.

 For example, the underline resolution enable circuit may consist of an enable signal generating circuit 41a, the output control circuit 65 shown in FIG. 14 and the loop adding control circuit 43 shown in FIG. 6. The resolution signal generating circuit 41 shown in FIG. 14 consists of delay circuits 45 and 49, circuits AND 47a and 51a, and circuit 53, similar to FIG. 10, and the output control circuit 65 consists of an input unit 67 and a CPU (central processing unit). An output control circuit 65 is implemented as part of the functions of the system minicomputer, and on-off signals are sent from the CPU 69 based on input received from an input unit 67, such as a keyboard, a remote controller, and the like, during the signal the “turn on” component of the loops highlighted by the loop selector 38 is supplied to the gain controller 40, and during the “turn off” signal the loop component that is highlighted by the loop selector 38 is cut off and not fed to the gain regulator. Due to the presence of an output control circuit 65, it is possible to control whether or not to underline outlines.

 In this embodiment, the first and second memories of 48 and 50 lines generate Y signals with a delay of 1 line and 2 lines in the circuit 38, and, similarly, the delay circuit 45 generates signals VW1 and VW2 of the vertical image area with a delay of 1 line and 2 lines in the resolution signal generating circuits 41 and 41a, in order to prevent distortion caused by the underlining processing that appears in 1 line of the upper and lower edges of the image screen and to obtain the largest possible image area without distortion, although the invention is not limited to this option.

 For example, the first and second memory for generating Y signals with a delay of 2 lines and 4 lines are introduced into the circuit 38, and similarly there is a delay circuit for generating signals VW1 and VW2 of the vertical image area with a delay of 2 lines and 4 lines in the resolution signal generation circuits 41 and 41a, this allows the invention to be used to prevent distortions caused by processing to emphasize the contours in 2 lines of the upper and lower edges of the image.

 In this embodiment, a loop emphasis frequency setting circuit 54 for generating Y signals with a 2-line and 4-line delay is included in the loop-selecting circuit 28, and, similarly, a delay circuit 49 for generating the horizontal region of the image signals HW2 and HW4 with a delay of 2 dots and 4 dots is provided in the resolution signal generation circuits 41 and 41a, this helps to prevent distortion caused by processing to emphasize the contours at the points of the left and right edges of the image and obtain the maximum possible area images without distortion caused by processing, however, this does not limit the invention.

 For example, the circuit for setting the frequency of underlining the contours for generating signals Y with a delay of 3 points and 6 points is introduced into the circuit 38 for selecting contours, and similarly, a delay circuit for generating signals HW3 and HW6 of the horizontal image region with a delay of 3 points and 6 points for the circuits 41 and 41a of the formation of resolution signals, while the invention eliminates distortion caused by the processing of underlining the contours at 3 points of the right and left edges of the video image.

 In this embodiment, the resolution signal generating circuits 41 and 41b consist of a delay circuit 45 and an AND 53 circuit for a vertical direction, a delay circuit 49 and an And 51 circuit for a horizontal direction, and an And 53 circuit to prevent distortion caused by the underline processing in the boundary parts of the vertical and horizontal directions of the actual video signals, however, this does not limit the invention and at least one side of the delay circuit and the And circuit for the vertical direction and the delay circuit can be used AND circuit for horizontal direction.

 In this embodiment, due to the fact that the gain controller 40 controls the size of the loop component extracted in the loop extraction circuit 38, and the coefficient multiplication circuit 42 outputs signals multiplied by the coefficients Kr, Kg, Kb to the adders 34r, 34g, 34b of the loops, which less than 1 (Kr + Kg + Kb = 1), it is possible to increase the number of underline contours for R, G, B, but this is not a limiting feature of the invention and you can do without the gain control 40 and the coefficient multiplication circuit 42, and output a signal with output circuit 38 of the allocation of circuits sredstvenno the adders 34r, 34g, 34b contours.

 In this embodiment, the ring core unit 64 in the loop isolation circuit 38 suppresses signals whose level is below a certain level of the component loops from the loop synthesis circuit 62, thereby eliminating the effects of noise, but the presence of the ring core block 64 is also optional.

Industrial applicability
As mentioned above, the underline circuit according to the invention can be used to obtain high-quality images with visually highlighted contours from the input analog color signals in a display device (e.g., a matrix type display device) operating on digital color video signals, e.g., PD, LCD and etc. In addition, the invention allows to prevent the occurrence of distortions due to processing aimed at underlining the contours, in the part of the image (for example, on the periphery) corresponding to the boundary part of the actual video signal.

Claims (7)

 1. An underline circuit in a display device with underline contour control by means of a digital video signal, characterized in that it contains an analog-to-digital conversion (ADC) circuitry for converting analog color video signals to digital color video signals, a signal processing circuitry for processing signals, such as converting the number of image elements, gamma correction, on the output signal of the ADC circuit, the signal generating circuit Y (bright ty) from the output signal of the above-mentioned ADC circuits, a loop extraction circuit designed to extract the loop component from the signal Y generated by the signal conditioning circuit Y, and a loop adder for generating digital color video signals with underlined loops by adding the loop component highlighted by the loop select circuit, s the output signal of the aforementioned signal processing circuit, wherein the circuit component highlighted by the aforementioned circuit allocation circuit sets a resolution circuit for naming the loops to control the period during which the loop component extracted by the loop allocation circuit is supplied to the loop adder, and the loop underlining resolution circuit consists of a resolution signal generating circuit for generating the loop underlining resolution signal based on the image area signal, and the circuit control of adding loops, designed to determine whether or not to feed the component of the loops, selected by the circuit selection circuit, in the adder cont a level based on the presence of the underline resolution enable signal inserted between the circuit allocation circuit and the circuit adder and formed by the resolution signal circuit introduced between the circuit allocation circuit and the circuit combiner and on the basis of the presence of the underline resolution circuit generated by the circuit of the enable signal generation circuit and a resolution signal generating circuit consists of a vertical resolution signal generating circuit for generating a resolution signal delineating the contours in the vertical direction based on the signal of the vertical image region, the horizontal resolution signal generation circuit designed to generate the horizontal underscore resolution signal on the basis of the horizontal image region signal, and the And circuit designed to generate logical product signals (logical AND) from underline resolution signals in the vertical direction and the horizontal direction are formed x a vertical resolution signal generation circuit and a horizontal resolution signal generation circuit as contour underline resolution signals.  2. An underline circuit in a display device with underline contour control by means of a digital video signal, characterized in that it contains an analog-to-digital conversion (ADC) circuitry for converting analog color video signals to digital color video signals, a signal processing circuitry for processing signals, such as converting the number of image elements, gamma correction, on the output signal of the ADC circuit, the signal generation circuit Y from you one signal of the aforementioned ADC circuit, a circuit allocation circuitry for extracting a circuit component from a signal Y generated by the signal conditioning circuit Y, and a circuit adder for generating digital color video signals with underlined circuits by adding the circuit component selected by the circuit circuitry with the output signal of the aforementioned signal processing circuits, wherein the loop component highlighted by said loop allocation circuit sets an underline resolution circuit the control loop for a period during which the loop component extracted by the loop select circuit is supplied to said loop combiner, and the loop underline enable circuit consists of a loop underline enable signal generation circuit for generating a enable signal based on the image area signal, an output control circuit deciding whether to output a resolution signal generated by a resolution signal generating circuit with a signal indicating whether l underlining the contours, and the control circuit adding loops, determining whether to apply the component of the circuits, highlighted by the circuit allocation circuitry, in the circuit adder, on the basis of the presence of the resolution signal underlining circuits generated by the circuit generating the permission signal entered between the circuit allocation circuitry and the circuit adder, circuit the formation of the permission signal consists of a circuit for generating a vertical resolution signal for generating an enable underline enable signal ditch in the vertical direction on the basis of the signal of the vertical image region, the horizontal resolution signal generation circuitry designed to generate the underline resolution signal in the horizontal direction based on the horizontal image region signal, and the AND circuit designed to generate logical product signals (logical AND) from the signals resolution underline contours in the vertical direction and horizontal direction formed by the circuit formed a signal of vertical resolution and a circuit for generating a horizontal resolution signal, as resolution signals for underlining the contours.  3. The outline underline circuit according to claim 1 or 2, characterized in that the outline extraction circuit consists of a vertical circuit allocation circuit for allocating the first and second line memory for delaying the Y signals generated by the Y signal generating circuit, sequentially by 1 line, and a component of the vertical circuits based on the Y signals generated by the signal conditioning circuit Y and delayed respectively, the circuit for setting the underline frequency of the circuits for generating the signal Y delayed by the first memory, and two types of signals delayed by 2 points and 4 points of a raster, a horizontal contour extraction circuit designed to extract a component of horizontal contours based on a Y signal delayed in the first line memory, and two types of delayed Y signals generated by the circuit for setting the frequency of underlining circuits, and circuit synthesis circuits intended for the synthesis of component circuits, highlighted respectively by a circuit for selecting vertical circuits and a circuit for allocating horizontal circuits, wherein The vertical resolution signal consists of a delay circuit for the vertical direction, designed to delay the signals VW of the vertical image region sequentially by 1 line, and an AND circuit for the vertical direction, designed to generate logical product signals (logical AND) from the signals VW1 and VW2 of the vertical image region delayed by 1 line and 2 lines of the VW signal of the vertical image region, and delay circuits for the vertical direction as resolution signals n deletion of contours, and delay circuits for the horizontal direction for delaying the signals HW of the horizontal image region sequentially by 2 raster points, and circuits AND for the horizontal direction for generating logical product signals (logical AND) from the signals HW2 and HW4 of the horizontal image region, delayed by the horizontal signal HW image areas, and delay circuits for the horizontal direction by 2 points and 4 points of the raster as signals for allowing underline contours in the horizontal direction.  4. The outline underline contours according to any one of paragraphs. 1-3, characterized in that it contains a block of an annular core for suppressing component circuits that are below a certain level, based on the entered selected component circuits.  5. The outline underline contours according to any one of paragraphs. 1-4, characterized in that the ADC circuit is configured to convert the analog signals R, G and B into digital signals, the signal conditioning circuit Y is configured to generate Y signals by adding Kr, Kg and Kb to the digital signals R, G and B from the ADC circuit and additionally contains a gain controller of the component circuits, configured to adjust the size of the component circuits received through the resolution circuit underlining circuits and a multiplication circuit by a factor for outputting to the adder circuits, which ribavlyaet coefficients Kr, Kg and Kb of less than 1, multiplied by the signals R, G, B in the circuit of the signal Y, the signals at the output of the gain regulator circuit components.  6. The underline circuit according to claim 1 or 2, characterized in that the said vertical resolution signal generating circuit consists of two 1H shift circuits connected in series to delay the input signals of the vertical image region sequentially by 1 line and AND circuits for generating logical product signals ( logical AND) the input signal of the vertical region, the signal of the vertical region, delayed by 1 line, and the signal of the vertical region, delayed by 2 lines, and the signal generation circuit horizontal resolution consists of four series-connected delay circuits per 1 raster point for delaying the input signals of the horizontal image region sequentially by 1 dot raster and circuit And for generating signals of the logical product (logical AND) of the input signal of the horizontal region of the image, the signal of the horizontal region, delayed by 2 raster points, and a horizontal region signal delayed by 4 raster points.  7. The underline circuit according to claim 1 or 2, characterized in that the underline circuit contains a vertical contour extraction circuit for isolating a component of the vertical contours based on the Y signals, respectively, first and second line memory for delaying the Y signals generated by the generating circuit signal Y, sequentially for 1 line, signal Y, formed by the circuit for generating signal Y and the first and second memory lines, a circuit for setting the frequency of underlining circuits, designed to form two types of delayed Y signals, consisting of a Y signal delayed by n raster points from the nth delay element by 1 raster point, and Y signals delayed by 2n raster points from the second delay element by 1 raster point based on the Y signal, delayed in the first line memory, a circuit for allocating horizontal circuits, designed to extract a component of the horizontal circuits based on the signal Y, delayed by the first memory of the lines, and two types of delayed signals Y, formed by the underscore frequency setting circuit loops, and a loop synthesis circuit designed to synthesize constituent loops, respectively identified by a vertical loop extraction circuit and a horizontal loop extraction circuit, wherein the vertical resolution signal generating circuit consists of a delay circuit for the vertical direction for delaying the VW signals of the vertical image region sequentially on 1 line, and AND circuits for the vertical direction, designed to generate logical product signals (logical oh) from the signals VW1 and VW2 of the vertical image area delayed by 1 line and 2 lines by the signal VW of the vertical image area, and the delay circuit for the vertical direction as vertical underline resolution signals, and the horizontal resolution signal generation circuit consists of a delay circuit designed to delay the HW signals of a horizontal image region sequentially by 2 raster points, and an AND circuit for a horizontal direction intended to form signals the logical product (Logical AND) of the signals HW2 and HW4 horizontal image region delayed for 2 or 4 points on the horizontal raster image area signal HW and a delay circuit for horizontal direction as contour emphasizing enable signals in horizontal direction.

Images