RU2137313C1 - Device to form signals of two- and four-frequency telegraphy - Google Patents

Abstract

FIELD: radio engineering, transmitting equipment for telegraphic communication. SUBSTANCE: device to form signals of two- and four-frequency telegraphy includes multiplexer to which controlling input outside instruction comes, third storage and first multiplier connected in series, fourth storage and second multiplier connected in series, adder whose inputs are connected to outputs of multipliers, address counter, fifth and sixth storages whose inputs are connected to output of address counter and whose outputs are connected to second inputs of multipliers. Inputs of third and fourth storages are connected to output of collecting adder. Outputs of adder and first storage are linked to first and second inputs of multiplexer correspondingly and output of multiplexer is connected to input of digital- to-analog converter. Clock input of address counter is connected to output of multitap frequency divider. EFFECT: provision for formation of multifrequency signal of two- and four-frequency telegraphy. 2 dwg

Description

 The invention relates to radio engineering and can be used in transmitting telegraph communication equipment.

 A device for generating a multi-frequency signal, comprising a reference generator, a phase setting unit, a phase shifter, an output adder and two signal generation channels, each of which is made in the form of series-connected frequency divider units with controlled phases, a channel adder and a multiplier.

 However, the known device cannot generate multi-frequency signals of two-frequency and four-frequency telegraphy.

 The closest in technical essence to the invention is a device for generating signals of two-frequency and four-frequency telegraphy, containing a series-connected reference oscillator and a multi-tap frequency divider, series-connected encoder, code sequence generator, second memory block, accumulating adder, first memory block, digital-to-analog converter and filter low frequencies, and the clock inputs of the accumulating adder and the code sequence generator are connected to the outputs of the multi-tap frequency divider.

 However, the known device is not intended to generate a multi-frequency signal.

 The objective of the invention is to provide the formation of a multi-frequency signal of two-frequency and four-frequency telegraphy.

 To do this, in a device for generating signals of two-frequency and four-frequency telegraphy, containing a series-connected reference generator and a multi-tap frequency divider, series-connected encoder, code sequence generator, a second memory unit, an accumulating adder and a first memory unit, a digital-to-analog converter and a low-pass filter connected in series, while the clock inputs of the accumulating adder and the generator of the code sequence are connected to the outputs of many of the output frequency divider, a multiplexer is introduced, to the control input of which an external command is supplied, a third memory block and a first multiplier connected in series, a fourth memory block and a second multiplier connected in series, an adder whose inputs are connected to the multiplier outputs, an address counter, fifth and sixth memory blocks whose inputs are connected to the output of the address counter, and the outputs are connected to the second inputs of the multipliers, while the inputs of the third and fourth memory blocks are connected to the output of the accumulating the motherboard, the outputs of the adder and the first memory block are connected to the first and second inputs of the multiplexer, respectively, the output of the multiplexer is connected to the input of the digital-analog converter, and the clock input of the address counter is connected to the output of the multi-tap frequency divider.

 The proposed solution meets the criteria of the invention of "novelty", because differs from the prototype in the presence of new functional elements and new relationships between the elements.

 In FIG. 1 shows a structural electrical diagram of the proposed device, FIG. 2 - spectrum of the output signal.

 The device comprises a reference generator 1 (OG), a multi-tap frequency divider 2 (MDC), an encoder 3 (III), a code sequence generator 4 (PCF), a second memory unit 5 (BP2), an accumulating adder 6 (HC), a first memory unit 7 (BP1), digital-to-analog converter 8 (DAC), low-pass filter 9 (low-pass filter), multiplexer 10 (MX), third memory block 11 (BP3), fourth memory block 12 (BP4), fifth memory block 13 (BP5), sixth memory unit 14 (BP6), the first multiplier 15 (UM1), the second multiplier 16 (UM2), the adder 17 (CM), the address counter 18 (CA).

 All of the listed blocks are connected as follows: 3-4-5-6-7-10-8-9, 6-11-15-17-10, 6-12-16-17, 1-2-6, 2-18 -13-15, 18-14-16, 2-4.

 The device operates as follows.

 The device can operate both in single-frequency and in multi-frequency modes; an external command arriving at the control input of multiplexer 10 serves for switching.

 In the single-frequency operation mode, the signal from the output of the first memory unit 7 is connected to the output of the multiplexer 10, which performs the functions of a code functional converter, where each code combination of the current phase is associated with a code that carries information about the instantaneous value of the signal at a given time.

 The address inputs of the first memory unit 7 are connected to the code outputs of the accumulating adder 6.

 The code at the output of the accumulating adder 6 with each clock pulse coming from the multi-tap frequency divider 2 changes by A (the setup code of the accumulating adder) and at each clock moment corresponds to the current phase of the output signal and at the same time determines the sample address of the sine amplitude code from the first memory unit 7, where the phase code is converted into an amplitude code.

 The amplitude code from the output of the first memory unit 7 through the multiplexer 10 is fed to the inputs of the digital-to-analog converter 8, the output of which is a multi-level step voltage, from which a generated signal is extracted using a low-pass filter 9.

 When A changes (with fixed values of the clock frequency and capacitance of the accumulating adder), the number of samples per sinusoidal period and, accordingly, the frequency of the output signal changes.

 Thus, the first memory unit 7 performs the functions of a code functional converter, codes of the values of the amplitudes of one period of the sinusoid are recorded in it.

 The codes of the settings of the accumulating adder 6 are recorded in the second memory block 5, the address inputs of which are connected to the outputs of the code sequence generator 4, i.e., the codes at the output of the code sequence generator 4 are the addresses of the codes of the accumulating adder 6 recorded in the second memory block 5.

 The first and second memory blocks are typical elements made on standard hardware-programmable memory chips 556РТ7.

 The manipulation signals at the first and second inputs are fed to the encoder 3, which generates control codes for the shaper 4 of the code sequence.

 Frequency telegraphy signals are generated at the output of the device when two values of codes corresponding to two values of characteristic frequencies are sequentially input to the accumulating adder 6.

 The signals of double frequency telegraphy are generated when four values of codes corresponding to four values of characteristic frequencies are received at the input of the accumulating adder 6.

 The codes of the settings of the accumulating adder 6, which generate signals of characteristic and intermediate frequencies at the output of the device, are sewn into the second memory unit 5, the code is sampled at the addresses specified by the code sequence generator 4.

 To reduce the level of out-of-band components of the spectrum of the output signal, a smooth transition from one characteristic frequency to another is organized.

 In the steady state of the device, when the state of the manipulation inputs does not change and any of the pause or send signal sets arrives at the manipulation inputs, the code at the output of the code sequence generator 4 sets the cell address of the second memory unit 5 in which the accumulator adder code is recorded 6, forming a signal at the output of the device, the frequency of which is equal to the characteristic frequency, for a set of manipulation signals.

 At the moment of changing the sign of the manipulation signal at one or two inputs of the device, at the outputs of the code sequence generator 4, a sequence of codes begins to form that specify the addresses of the second memory unit 5, according to which the setting codes of the accumulating adder 6 are recorded, forming a signal with intermediate frequency values at the device output whose numerical values are in the interval between the previous characteristic frequency and the one that will be established with a new set of manipulation signals.

 At the end of the transition process, the duration of which is usually up to 30% of the duration of a single sending, the formation of a sequence of codes at the output of the code sequence generator 4 is completed and a code is set at this output that sets the cell address of the second memory unit 5 in which the setup code of the accumulating adder is recorded 6, generating a signal at the output of the device, the frequency of which is equal to the characteristic frequency, for a newly established set of manipulation signals.

 The law of change in the frequency of the output signal during manipulation affects the level of out-of-band spectral components and can be any, for example, sinus, linear, parabolic.

 The number of intermediate frequency values during the transition process determines the accuracy of the reproduction of a given law.

 By changing the firmware of the second memory unit 5, it is possible to implement with sufficient accuracy almost any law of changing the frequency of the output signal during a smooth transition from one characteristic frequency to another.

 The purpose of the shaper 4 of the code sequence is to form a code sequence of access addresses to the second memory unit 5 during the smooth transition from one characteristic frequency to another.

 The code sequence generator 4 assumes any hardware implementation that performs the functions described above, for example, a circuit for the base of a reversible counter can be used, the operation mode of which is controlled by signals from encoder 3.

 Encoder 3 is a logic circuit generating control codes defining the operating modes of the code sequence generator 4, for example, counting direction, beginning and stopping of the counting. When the state of one of the manipulation inputs changes, the control code at the encoder output changes and the process of a smooth transition from one characteristic frequency to another begins in the device circuit.

 In multi-frequency operation, the output from the output of the adder 17 is connected to the output of the multiplexer 10.

 The required multi-frequency signal is the sum of narrow-band frequency-spaced signals carrying the same information.

где Wo - начальная несущая частота (частота любой из частотных составляющих многочастотного сигнала),
dW - интервал частотного разнесения многочастотного сигнала,
фk - начальная фаза каждой частотной составляющей многочастотного сигнала,
n - количество частотных составляющих многочастотного сигнала,
k - порядковый номер частотной составляющей.Consider the analytical justification of the proposed device for a multi-frequency signal without manipulation:

where Wo is the initial carrier frequency (the frequency of any of the frequency components of the multi-frequency signal),
dW is the frequency diversity interval of the multi-frequency signal,
fk is the initial phase of each frequency component of the multi-frequency signal,
n is the number of frequency components of a multi-frequency signal,
k is the serial number of the frequency component.

Рассмотрим полученную формулу. Многочастотный сигнал образуется путем перемножения одночастотного представленного в цифровом виде сигнала на низкочастотную огибающую многочастотного сигнала.After transformations of formula (1), the output signal will be presented in the following form:

Consider the resulting formula. A multi-frequency signal is formed by multiplying a single-frequency digitally presented signal by the low-frequency envelope of the multi-frequency signal.

Each specific multi-frequency signal has previously known parameters:
- the number of frequency components - n;
- frequency diversity interval - dW;
- the initial phases of each of the frequency components - fk.

 The initial phases of the frequency components are selected based on minimizing the output signal peak factor.

 Given the previously known parameters (n, dW, fk), we can calculate the sine and cosine components of the envelope of the multi-frequency signal and write them into memory blocks.

 The sine and cosine components of the envelope of the multi-frequency signal are read from BP5 13 and BP6 14 with a clock frequency supplied to the input of the address counter 18.

 The sine and cosine components of a single-frequency signal are read from BP3 11 and BP4 12 at the address determined by the output of the accumulating adder 6.

 The clock frequency controlling the operation of the accumulating adder 6 coincides with the clock frequency of the address counter 18, samples from memory units BP5 13, BP6 14, BP3 11, BP4 12 are performed simultaneously.

 As a result of multiplying the digital multipliers 15, 16 of the single-frequency signal and the envelope of the multi-frequency signal and adding them to the adder 17, a digital multi-frequency signal is generated.

 Upon receipt of the manipulation signals, similarly to how this happens in the single-frequency mode, the encoder 3 generates control signals for the code sequence generator 4, which, in turn, generates addresses of access to the second memory unit 5, from which the codes for setting the accumulating adder 6 are selected, code the output of which determines the address of the sample from BP3 11 and BP4 12.

 The conversion of a digital signal into an analog one is performed in the same way as when forming a single-frequency signal.

 Figure 2 shows the spectrum of a five-frequency manipulated signal.

 If it is necessary to have several different multi-frequency signals in the device that differ in the number of frequency components, the frequency diversity interval and the initial phases, it is possible to carry out the proposed calculations for each of the multi-frequency signals, record their results in various memory areas of BP5 13 and BP6 14 and, by issuing external commands to inclusion (not shown in the diagram), connect to the multipliers the corresponding memory areas of BP5 13 and BP6 14.

 Thus, the proposed device allows you to generate a multi-frequency signal, which is the sum of narrow-band multiple frequency-spaced signals that carry the same information.

Claims (1)

 A device for generating signals of two-frequency and four-frequency telegraphy, comprising a series-connected reference generator and a multi-tap frequency divider, series-connected encoder, code sequence generator, a second memory block, an accumulating adder and a first memory block, a digital-to-analog converter and a low-pass filter connected in series, the inputs of the accumulating adder and the code sequence generator are connected to the outputs of the multi-tap frequency divider, characterized in that a multiplexer is introduced into it, to the control input of which an external command is supplied, a third memory block and a first multiplier connected in series, a fourth memory block and a second multiplier connected in series, an adder whose inputs are connected to the outputs of the multipliers, an address counter, the fifth and sixth memory blocks, the inputs of which are connected to the output of the address counter, and the outputs are connected to the second inputs of the multipliers, while the inputs of the third and fourth memory blocks are connected to the output of of the accumulating adder, the outputs of the adder and the first memory block are connected to the first and second inputs of the multiplexer, respectively, the output of the multiplexer is connected to the input of the digital-analog converter, and the clock input of the address counter is connected to the output of the multi-tap frequency divider.

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