RU213672U1 - CONTROLLED FREQUENCY DIVIDER OF THE HARMONIC SIGNAL - Google Patents

Abstract

The utility model relates to the field of radio electronics and can be used in various radio engineering devices that require frequency division with a variable division factor. The technical result of the claimed utility model is to expand the functionality of the harmonic signal frequency divider by providing an adjustable division factor, including its fractional values. The device contains a controlled phase shifter, two adders, a voltage-frequency converter, a single vibrator, an integrator with reset, a multiplier and a constant voltage source, the input of the frequency divider is connected to the input of the controlled phase shifter, the control input of which is connected to the output of the first adder, the first input of which is connected to the output integrator with reset, the input of which is connected to the output of a multiplier, the second input of which is connected to the output of a constant voltage source and the second input of the first adder, the output of the second adder is connected through a voltage-frequency converter to the input of a one-shot, the output of which is connected to the reset input of the integrator with reset, and the control input of the frequency divider is connected to the first inputs of the second adder and the multiplier, the second input of which is connected to the output of the second adder. 3 ill.

Description

The utility model relates to the field of radio electronics and can be used in various radio engineering devices that require frequency division with a variable division factor.

Known frequency divider of a harmonic signal [USSR author's certificate No. 668062 IPC H03B 19/12, publ. 06/15/1979], containing a square root extraction unit, a signal multiplier, a zero level discriminator, a counting trigger, a constant voltage source equal to the amplitude of the input signal, and a signal adder, the inputs of which are connected to the frequency divider input and a constant voltage source, and the output connected to the input of the square root extraction unit, the output of which is connected to the inputs of the signal multiplier directly and through a series-connected zero-level discriminator and a counting trigger.

The disadvantage of this frequency divider is its low accuracy, due to the fact that it does not provide equality of the amplitudes of the input and output voltages in the operating range of input signal values. In addition, in it the amplitude of the input signal is set by a constant voltage source, and is not measured automatically. This limits the performance of the frequency divider only by the amplitude of the input signal, equal to the specified one.

The closest analogue to the proposed utility model is the frequency divider of the harmonic signal [RF Patent No. 206322 IPC H03V 19/12, H03K 21/00 publ. 09/06/2021], containing a controlled phase shifter, a comparator, a counting trigger, a single vibrator, an integrator with a reset, a frequency-voltage converter, a multiplier, a DC voltage source, an adder and an inverter, and the output of the DC voltage source is connected to the first input of the adder, the divider input frequency is connected to the input of the controlled phase shifter and the input of the comparator, the output of which is connected through the counting trigger to the input of the single vibrator, the output of which is connected to the reset input of the integrator with reset, the output of which is connected to the second input of the adder, the output of which is connected through the inverter to the control input of the controlled phase shifter, the output which is connected to the output of the frequency divider, the output of the comparator through the frequency-voltage converter is connected to the first input of the multiplier, the second input of which is connected to the output of the DC voltage source, and the output of the multiplier is connected to the input of the integrator.

This technical solution was chosen as a prototype.

The disadvantage of this frequency divider is that it divides the frequency of the input signal by two, i.e. to a fixed division factor.

The technical result of the claimed utility model is to expand the functionality of the harmonic signal frequency divider by providing an adjustable division factor, including its fractional values.

The specified technical result is achieved by the fact that in a known frequency divider of a harmonic signal containing a controlled phase shifter, a single vibrator, an integrator with a reset, a multiplier, the first adder and a constant voltage source, the input of the frequency divider is connected to the input of the controlled phase shifter, the control input of which is connected to the output of the first adder, the first input of which is connected to the output of the integrator with reset, the input of which is connected to the output of the multiplier, the second input of which is connected to the output of the DC voltage source and the second input of the first adder, and the output of the one-shot is connected to the reset input of the integrator with reset, characterized in that in It additionally includes a voltage-frequency converter and a second adder, the output of which is connected through the voltage-frequency converter to the input of a single vibrator, and the control input of the frequency divider is connected to the first inputs of the second adder and multiplier, the second input of which is connected to the output of the second adder.

The essential differences of the proposed device are the introduction of a voltage-frequency converter, a second adder and the organization of new connections between the elements of the device. The combination of elements and connections between them ensure the achievement of a positive effect - expanding the functionality of the harmonic signal frequency divider by providing an adjustable division factor.

The essence of the utility model is illustrated by drawings. In FIG. 1 shows a functional diagram of a controlled frequency divider, in Fig. 2 - time diagrams of voltages u _in , U _y , u ₃ , u ₆ , u ₇ and u _out , in fil. 3 - adjusting characteristic.

The controlled frequency divider (Fig. 1) contains a controlled phase shifter 1, adders 2 and 8, a voltage-frequency converter (VFC) 3, a single vibrator 4, an integrator with a reset 5, a multiplier 6 and a constant voltage source 7.

с частотой

подается на вход управляемого фазовращателя 1. При этом напряжение управления U_y подается на вход сумматора 2, где суммируется с выходным напряжением U₅=+5 В источника постоянного напряжения 7 (фиг. 2). Полученное напряжение u₁ поступает на вход ПНЧ 7 и преобразуется в импульсное напряжение u₂ частотой f_ПНЧ, определяемой выражением:Controlled frequency divider works as follows. Input sinusoidal voltage

with frequency

is supplied to the input of the controlled phase shifter 1. In this case, the control voltage U _y is supplied to the input of the adder 2, where it is added to the output voltage U ₅ =+5 V of the DC voltage source 7 (Fig. 2). The resulting voltage u ₁ is fed to the input of the PFC 7 and is converted into a pulsed voltage u ₂ frequency f _PFC defined by the expression:

- коэффициент передачи ПНЧ 3.where

- transmission coefficient of VLF 3.

The transmission coefficient K _VLF VCh 3 is selected so that at an input voltage of 10 V, the frequency of its output pulses corresponds to twice the frequency of the input voltage _{2f in} or the maximum operating frequency f _{pmax of the} sawtooth voltage of the integrator with reset 5, i.e.

On the front of the output pulses VLF u ₂ starts single vibrator 4, as a result of its output are short-duration pulses frequency f _VLF , which are fed to the reset input of the reset integrator 5 (Fig. 2).

The output voltage of the DC voltage source 7 is selected with positive polarity, equal to the maximum value of the control voltage U _ymax equal to +5 V, i.e. U ₅ \u003d +5 V.

At the same time, a voltage u ₄ is formed at the input of the integrator with a reset 5, equal to the result of multiplying the voltages U _y and U ₅ in the multiplier 6:

where K _p =0.1 - the transfer coefficient of the multiplier 6;

U ₅ \u003d 5 V - output voltage of a constant voltage source 7.

At the output of the integrator with reset 5, a sawtooth voltage u _{6 of} negative polarity is formed with a frequency of _{2f in} , the amplitude of which is determined by the formula (Fig. 2):

where U ₄ - the value of the input voltage of the integrator with reset 5;

f _PFC - frequency of the output voltage of the PFC 3;

f _{PFC max} - the maximum frequency of the output voltage of the PFC 3;

R is the resistance of the integrator resistor with reset 5;

C - integrator capacitor capacitance with reset 5.

To select the parameters of the timing elements of the circuit R and C with the amplitude of the output sawtooth voltage of the integrator with reset 5 equal to U _6m = -10 V, it is necessary to maintain the following relationship:

As a result, the amplitude of the output sawtooth voltage of the reset integrator 5 is always constant U _6m =-10 V and does not depend on the control voltage U _y over its entire operating range.

The output voltage u _{4 of} the integrator with reset 5 is added in the adder 8 with a constant voltage U ₅ = +5 V from a constant voltage source 7, as a result of which an alternating falling sawtooth voltage u ₇ with an amplitude of 5 V is formed at the output of the adder 8. This voltage is applied to the control the input of the controlled phase shifter 1 (Fig. 2).

The device uses a controlled phase shifter 1, which allows you to linearly change the phase ϕ of the input signal from -180° to +180° when the control voltage changes from -5 V to +5 V (Fig. 2). This sawtooth control voltage, acting on the controlled phase shifter 1, changes the phase ϕ of its input signal from -180° to +180° (Fig. 2).

As a result, at the output of the controlled phase shifter 1 and at the output of the frequency divider, the output voltage u _out is formed:

- коэффициент деления делителя частоты.where

- division factor of the frequency divider.

It can be seen from the obtained expression that the frequency ω _out of the output voltage u _out of the frequency divider depends on the division factor K _del , which in turn depends on the control voltage U _y . By changing the voltage U _y , you can smoothly change the values of the division coefficient K _div . In this case, the amplitude of the output voltage U _{m out} of the frequency divider is equal to the amplitude of the input voltage U _{m in} .

The dependence of the division factor K _div on the control voltage U _y is an adjustment characteristic K _div =f(U _y )=1/(0.2(U _y ), which is shown in Fig. 3. The characteristic is a hyperbolic dependence. If you need to have directly proportional to a linear dependence, then it is necessary to turn on the hyperbolic converter at the control input.

Thus, the given controllable frequency divider of the harmonic signal makes it possible to obtain an adjustable frequency division factor, including its fractional values.

It should be noted that with a small difference between the frequencies of the input voltage and the sawtooth voltage, a fairly stable sinusoidal voltage of infra-low frequencies can be obtained at the output.

The use of the second adder 2 and the voltage-frequency converter 3 in the adjustable frequency divider of the harmonic signal allows to achieve the desired technical result - expanding the functionality of the frequency divider of the harmonic signal by providing an adjustable division factor.

In the practical implementation of the proposed controlled frequency divider, the controlled phase shifter 1 can be made according to the scheme (Patent for PM No. 206198 of the Russian Federation, G01R19 / 22. Controlled phase shifter, publ. 08/30/2021). Adders 2 and 8 are non-inverting op-amp adders. As a voltage-frequency converter 3, you can use a converter on the KR1108PP1 chip. Single vibrator 4 can be performed on the K561AG1 chip. An integrator with reset 5 can be performed on an operational amplifier (op-amp) according to the scheme (V.G. Gusev, Yu.M. Gusev. Electronics and microprocessor technology. - M .: Higher school, 2005. - p. 459, fig. 6.18, c). Multiplier 6 can be performed on the KR525PS3 chip. The constant voltage source 7 is a conventional stable voltage source.

Claims (1)

A controlled frequency divider of a harmonic signal, containing a controlled phase shifter, a single vibrator, an integrator with a reset, a multiplier, a first adder and a constant voltage source, the input of the frequency divider is connected to the input of the controlled phase shifter, the control input of which is connected to the output of the first adder, the first input of which is connected to the output integrator with reset, the input of which is connected to the output of the multiplier, the second input of which is connected to the output of the DC voltage source and the second input of the first adder, and the output of the one-shot is connected to the reset input of the integrator with reset, characterized in that it additionally includes a voltage-frequency converter and the second adder, the output of which is connected through the voltage-frequency converter to the input of the single vibrator, and the control input of the frequency divider is connected to the first inputs of the second adder and the multiplier, the second input of which is connected to the output of the second adder.

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