RU2123758C1 - Digital filter - Google Patents

Abstract

FIELD: real-time digital signal processing for miscellaneous devices and systems. SUBSTANCE: filter has series-connected digital Fourier transform unit, multiplying unit, spectral resolution raising unit, as well as inverse digital Fourier transform unit; connected to second input of multiplying unit is output of storage unit. This requires approximately twice as low hardware cost required for filtering which is equivalent to actually twice as high speed of device. EFFECT: enlarged functional capabilities; improved speed of digital filter. 3 dwg

Description

 The inventive object relates to the field of digital signal processing and can be used in the implementation of preselectors (band-pass filters that emit a signal in the working frequency range), or spatial filters (i.e., shapers of directivity characteristics in phased antenna arrays), for example, in communication systems, as well as other real-time digital signal processing systems.

 One of the significant problems in designing a digital filter is the problem of choosing its structure in which the computational costs (the number of operations per second) necessary for its implementation are minimized. Minimizing the computational cost required to implement the filter is equivalent to increasing the speed of the device (special processor).

 The so-called direct form of a digital filter with impulse response of finite duration is known (see L. Rabiner, B. Gould. Theory and application of digital signal processing. M: Mir, 1978, Fig. 9.1 on page 598). The disadvantage of this analogue is the large computational costs necessary for its implementation.

The most common structure of a digital filter in practice, characterized by minimal (among known analogues) computational costs, is a structure of the form "fast Fourier transform (FFT) - multiplying the spectrum by an array of amplitude-frequency filter characteristics (AFC) - inverse FFT" (see the cited book L. Rabiner, pp. 804 ... 807). This digital filter is closest to the claimed object in technical essence, therefore, it is further considered as a prototype. A characteristic feature of the prototype is the implementation of the FFT procedure (block) with a significant overlap of the input signal in the time domain, which is due to the need to obtain an aperiodic convolution of this signal with the pulse response of the filter. The overlapping mode of operation is illustrated graphically in the cited source in FIG. 13.10; there are also shown the possible relationships between the duration of the window of spectral analysis (FFT dimension) and the duration of the pulse response of the filter (in the case of the implementation of a matched filter, the latter is equal to the duration of the useful signal, which is what O. Rabiner means) According to the cited source (see p. 806, 6th line from the top), the most appropriate option is to implement the filter parameters in which the spectral analysis window length L _s exceeds the filter impulse length L _{h by} 2 times (overlap by 50 %).

At the same time, at each step of updating the input signal, half of the samples of this signal undergo almost the same processing procedures as in the previous step. In addition, in the prototype, the unit for multiplying the signal spectrum by the AFC array fulfills its function 2 times for the time interval L _s (i.e., once for the time L _h = L _s / 2), while the correlation interval for the samples generated by the FFT block equal to L _s . Thus, the payment for the need to obtain samples of aperiodic convolution, i.e. useful samples (and the need to discard the samples of cyclic convolution, i.e. useless samples) in the prototype is the development of its functions by a number of blocks at double speed (i.e., in time L _s / 2 instead of a potentially sufficient option in time L _s ), which increases the required computing costs.

The specified disadvantage can be quantitatively illustrated as follows. For a given duration of the filter impulse response L _h due to the above circumstances (associated with the need to calculate aperiodic convolution) in the prototype, the FFT block must perform spectral decomposition in the interval L _s = 2L _h (or in the general case L _s > L _h ), while while potentially sufficient, the value L _s = L _h could be realized (of course, this potentially sufficient value of L _s could not be realized in the prototype). In this case, the computational costs for the implementation of the FFT block at L _s = 2L _h increase by more than 2 times. At the same time, the cost of implementing a unit for multiplying the spectrum of the signal by the array of the frequency response of the preselector increases.

 Thus, the disadvantage of the prototype are the relatively high required computing costs.

 It should be noted that the FFT procedure is a variant of the technical implementation of the discrete Fourier transform (DFT) procedure, therefore, we further consider the names of these procedures synonyms.

 The purpose of the proposed technical solution is to reduce the required computing costs for the implementation of the filter, which can be interpreted as an equivalent increase in performance (in the same sense, the cost of computing costs is treated, for example, in the facility according to AS N 1361574). The goal is achieved by the fact that in the digital filter containing the DFT block, the output of which is connected to the signal input of the multiplication block, to the reference input of which the output of the memory block is connected, as well as the inverse DFT block, the information input and output of the filter being the input of the DFT block and the output, respectively block inverse DFT, a doubling unit is introduced, included between the output of the multiplication block and the input of the block of the inverse DFT.

The block diagrams of the claimed object and the embodiment of the doubling unit, as well as the timing diagram of the operation of the individual blocks of the claimed object are shown in FIG. 1-3, respectively, where indicated:
1 - block discrete Fourier transform (DFT);
2 - multiplication block;
3 - doubling unit;
4 - block inverse DFT;
5 - memory block;
6 - interpolator;
7 and 9 - delay elements;
8 - subtractor;
10 - adder;
11 - the second block of multiplication;
12 - the second block of memory.

 All communications shown in FIG. 1 and 2 double arrows are vector (data arrays are transmitted along them).

 The inventive object can be implemented both in the embodiment of the function of purely temporal filtering, and in the embodiment of the function of spatio-temporal filtering. First, the first filter option is described.

 The dynamics of the blocks 1-4 of the inventive object is illustrated in FIG. 3, where on the first time base from the top, the moments of fulfilling its function by the DFT unit are shown, on the second - by the multiplication unit 2, on the third - by the doubling unit 3 and on the fourth - by the inverse DFT unit 4.

 The disclosure (including the dynamics of operation) of the DFT 1 and the implementation option of the doubling unit 3 of the claimed object is given in the description to A. with. N 1361574 (G 06 F 15/332) according to the application N 4097683 / 24-24 from 07.25.86. The implementation and dynamics of the unit DFT 1 of the proposed facility are fully consistent with those in the above description. Doubling unit 3 may be implemented, for example, in accordance with the block diagram of FIG. 2 of the present description, or is completely analogous to the corresponding block in the description of A. with. N 1361574. In the latter case, blocks 11 and 12 in FIG. 2 of the present description as part of the doubling unit 3 are absent.

 (Note. In Fig. 1, the description of the object by A.S. N 1361574 in the display of one of the connections of blocks 7 and 8 is inaccurate, namely, both of these connections are included in block 8; in Fig. 2 of the present description (where these blocks appear under numbers 9 and 10, respectively), this inaccuracy is corrected).

 Doubling unit 3 provides a 2-fold increase in spectral resolution. The principle of its operation is based on the interpolation of intermediate samples of the DFT results obtained in two adjacent time cycles of updating the results at the output of the DFT block, and "stitching" of the two spectra obtained. “Stitching” is realized by pairwise (vector) summing of the corresponding uninterpolated (i.e., obtained directly at the output of the DFT block) spectral samples to obtain the results of the desired DFT for even numbers of DFT coefficients and pairwise subtraction of the interpolated spectral samples (from the interpolated samples at the current DFT step the corresponding samples obtained at the previous step of the DFT are subtracted) to obtain the results of the desired DFT with odd numbers of coefficients. In accordance with the terminology of the description to A.S. N 1361574 in the inventive object, the doubling unit 3 operates in a sliding mode, i.e. fulfills its function with each update of the result at the output of the multiplication block.

 The synchro input of node 3 is shown in block diagrams of FIG. 1 and 2 conditionally. In the case of implementing a filter using programmable digital computer technology, a sync input is not needed; in the case of a hardware implementation, a sequence of clock pulses corresponding to the 3rd from the top in FIG. 3, or slightly ahead of her in time. (The clock generator in the composition of the claimed object is not considered for brevity).

Multiplication block 2 is a collection of LxAxB (where L is the number of points or the DFT dimension in block 1, A is the number of elementary processing channels, i.e., elements of the antenna array, B is the number of spatial processing channels, i.e., formed directivity characteristics , with purely temporal filtration A = B = 1) of independently operating elementary multipliers, each of which multiplies the value of the lth (for A = B = 1, l = 1 ... L) DFT coefficient by the lth reference spectrum reading stored in the corresponding l-th cell of the memory block 5. Lock 5 presents a set of no more than LxAxB long-term memory devices (cells) that store pre-recorded therein multi-bit words, each l-th of which corresponds to a count of l-th frequency response of the digital filter. The content of each cell is continuously fed to the corresponding input of the corresponding elementary multiplier, which is part of block 2. The inverse DFT block 4 is basically implemented in the same way as the DFT block 1, with the only difference being that the number of points (array dimension) of the inverse DFT is in total case can be greater (2 times), equal to or less (2 ⁿ times, where n is an integer) than the number of DFT points (L).

 The inventive object can be implemented on elements of digital technology of a combination type. In this case, the time diagram of the filter operation (FIG. 3) is implemented by itself with the corresponding block diagram in FIG. 1, the order of connecting the elements and controlling the operation of block 3 (blocks 7 and 9) by supplying control pulses to the one shown in FIG. 1 and 2 sync inputs. At the same time, of greatest interest is the implementation of the claimed object using programmable digital computing technology. Modern programmable tools are asynchronous (i.e., each subsequent procedure begins to be executed after the completion of the previous procedure; the sequence of procedures is determined by the content of the flowcharts in Fig. 1 and 2). In the latest version of the technical implementation of the filter, there is no need for a sync input.

 When implementing a filter that solves the problem of space-time filtering, the above description requires the following refinements.

 Typical initial fragments of the block diagrams of space-time filters are given, for example, in the book of A. G. Gusev "Systems of spatio-temporal processing of g / a information." L., Shipbuilding, 1988, fig. 1.2 on page 15, or in the book by B. Widrow and S. Stirnz "Adaptive Signal Processing", M., Radio and Communications, 1989, fig. 2.3 on page 24. In this case, the DFT unit 1 is a collection of A independently operating DFT subunits (A is the number of elementary channels of the antenna array). Each of the DFT subunits in this case coincides with that DFT block 1, which is realized in the case of solving the problem of purely temporary filtering. Block 5 stores the frequency response of the spatial or space-time filter. In this version of the filter, the multiplication of the spectrum of the signal obtained as a result of spatial filtering (for simplicity, we assume that B = 1) can also be carried out immediately before the inverse DFT block. At the same time, we believe that, as part of the doubling unit 3, along with its traditional elements (as in the description above for A.S. N 1361574), namely, an interpolator, two delay elements, an adder and a subtractor, and the outputs of the latter are combined by OR, included also a multiplication unit 11, as well as a memory unit 12. In the last embodiment, the implementation of the doubling unit 3 is implemented and the functions of the multiplication units 11 and memory 12 included in it are the same as the blocks 2 and 5, respectively, in the block diagram of FIG. 1 with purely temporary filtration.

The principle of operation of the claimed object differs from the principle of operation of the prototype only in that in it, the DFT 1 and multiplication 2 blocks fulfill their functions on arrays containing 2 times less samples than in the prototype (the technical implementation of blocks 1, 2, 4 and 5 the claimed object, in principle, coincides with the technical implementation of these objects in the prototype). The possibility of reducing the dimension of these arrays (i.e., decreasing the spectral analysis window from L _s = 2L _h to L _s = L _h ) is provided by introducing a doubling node 3 into the filter. The cost of the indicated computational cost is the need to implement a doubling node 3 The last node provides an imitation of the effect of doubling the length of the window of the spectral analysis in the DFT unit 1, which in turn ensures the equivalence of the filtering function performed by the claimed object, the function that the prototype performs.

Let us prove that the computational cost savings achieved in the claimed object in blocks 1 and 2 (and 5) can be more substantial than the additional costs of implementing the doubling node 3. First, we consider the option of purely temporary filtering. Let the DFT block in the prototype perform spectral decomposition into 2N samples, and in the inventive object, respectively, into N samples (we consider the samples of the input signal to be complex). Then the computational costs (the number of valid operations) for the implementation of the DFT block of the prototype and the claimed object for the time L _s are respectively
10 • 0.5 • 2N • log ₂ 2N = 10N (log ₂ N + 1) = 10N • log ₂ N + 10N
(here the first factor of 10 takes into account the fact that one operation of the “butterfly” type is equivalent to 10 operations of the type of “addition” or “multiplication” over real numbers).

and
10 • 0.5N • log ₂ N = 5N • log ₂ N.

The number of operations saved in the claimed object is
5N • log ₂ N + 10N.

Let the inverse DFT in the prototype and the claimed object is carried out according to M complex samples of the spectrum. Then, the multiplication block 2 in the inventive object performs M / 2 complex multiplications or 3M actual operations in one cycle of the filtering procedure (during L _s ) (hereinafter, block 3 simulates an increase in this number to M complex multiplications), and a similar block in the prototype - M complex multiplications or 6M valid operations. (Each complex multiplication in computational cost is equivalent to 6 operations of the type of "addition" or "multiplication" over real numbers). As a result, when implementing the block for multiplying the spectrum of the signal of the frequency response of the filter for the time L _{s, the} saving is 3M, and the total saving (taking into account the DFT 1 block)
5 • N (log ₂ N + 2) + 3M.

The implementation of the doubling node costs the following computational costs. Suppose that when interpolating intermediate samples of the spectrum, the interpolating function contains Q samples (studies have shown that acceptable accuracy is already provided at Q = 4 ... 8). Then the cost of interpolating M spectrum samples (over time L _s ) is
0.5 • M • Q • 8
actual operations (here the last factor of 8 takes into account the fact that a pair of complex multiplication and addition operations is equivalent in cost to 8 actual operations). The cost of “stitching” the spectra is 2M actual operations for the time L _s .

Suppose, for example, N = 1024, M = 128, and Q = 8, then the number of operations saved on the implementation of blocks 1 and 2 in the claimed object is 61824, and the number of additional operations necessary to implement the doubling node 3 is only 4352, those. total savings of 57,472 valid transactions over time L _s . The total computational cost for the implementation of the prototype in this situation is
0.5 • 2N (log ₂ N + 6M + 0.5M • log ₂ M • 10) = 107648,
and the claimed object 107648-57472 = 50176 actual operations for the time L _s . Thus, the implementation of the inventive object provides a reduction in computing costs by about 2 times, which is equivalent to a twofold increase in the speed of the device.

 It should also be noted that the implementation of the claimed object allows to reduce by 2 times the required amount of data stored in memory block 5 (a block with the same functionality is also in the prototype).

 The inventive object is characterized by significant differences, since the known application of the doubling node in the object by a.s. N 1361574 provides a saving in computing costs of less than 2 times (since in this object, unlike the claimed one, there is no saving on the multiplication block 2 due to the absence of such a block). In addition, the implementation of the doubling node in the specified known object does not save the required amount of memory. In addition, the criterion of "significant differences" in the claimed object is provided by new connections of the doubling node.

Claims (1)

 A digital filter containing a discrete Fourier transform unit, the output of which is connected to the signal input of the multiplication unit, to the reference input of which a memory block output is connected, as well as an inverse discrete Fourier transform unit, the information input and output of the filter being the input of the discrete Fourier transform unit and the output, respectively discrete inverse Fourier transform unit, characterized in that between the output of the multiplication unit and the input of the inverse Fourier transform unit, the input node is included increase spectral resolution.

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